9/17/2002

Overview
• Motivation
ECE 553: TESTING AND • What is simulation?
TESTABLE DESIGN OF • Design verification
• Circuit modeling
DIGITAL SYSTES • Determining signal values
• True-value simulation algorithms
• Compiled-code simulation
• Event-driven simulation
• Summary
Logic Simulation
9/17/2002 2

Motivation Simulation Defined

• Definition: Simulation refers to modeling of a design,
• Logic simulation is used to verify or its function and performance.
ascertain assertions (design, device, …) • A software simulator is a computer program; an
emulator is a hardware simulator.
• It avoids building costly hardware • Simulation is used for design verification:
• Can help debug a design in many more • Validate assumptions
• Verify logic
ways than the real hardware could • Verify performance (timing)

• Understanding simulation will help • Types of simulation:

• Logic or switch level
understand the limitations of the simulation • Timing
process and the simulator(s) in question • Circuit
• Fault
9/17/2002 3 9/17/2002 4

Simulation for Verification

Modeling for Simulation
• Modules, blocks or components described by
Specification • Input/output (I/O) function
• Delays associated with I/O signals
Synthesis • Examples: binary adder, Boolean gates, FET, resistors and
capacitors
Response Design Design
• Interconnects represent
analysis changes (netlist ) • ideal signal carriers, or
• ideal electrical conductors
• Netlist: a format (or language) that describes a
Computed True- value design as an interconnection of modules. Netlist
Input stimuli
responses simulation may use hierarchy.

9/17/2002 5 9/17/2002 6

1
 9/17/2002

Logic Model of MOS Circuit Options for Inertial Delay

(simulation of a NAND gate)
V DD Transient
pMOS FETs a
region

Inputs
a Da
a Dc c b

Ca b Db
c c (CMOS)

b Cc
D a and Db are c (zero delay)

Logic simulation
Cb interconnect or
nMOS FETs
propagation delays c (unit delay)

X
c (multiple delay) rise=5, fall=5
D c is inertial delay
C a , Cb and C c are of gate c (minmax delay)
Unknown (X)
min =2, max =5
parasitic capacitances
0 5 Time units
9/17/2002 7 9/17/2002 8

Signal States Determining Gate Values

• Two-states (0, 1) can be used for purely • Use of software logic primitives such as
combinational logic with zero-delay. AND, OR, NOT instructions
• Three-states (0, 1, X) are essential for timing
hazards and for sequential logic initialization. • Search the truth table
• Four-states (0, 1, X, Z) are essential for MOS • Use cubes and cube intersection rules for
devices. See example below. processing
• Analog signals are used for exact timing of digital
logic and for analog circuits. • Use of X value and its processing
– Example: x value simulation, problems
Z associated with it, possible fixes and conservative
(hold previous value)
processing
0
0
9/17/2002 9 9/17/2002 10

True-Value Simulation Algorithms Compiled-Code Algorithm

• Compiled-code simulation
• Applicable to zero-delay combinational logic • Step 1: Levelize combinational logic and encode in a
• Also used for cycle -accurate synchronous sequential circuits for logic compilable programming language
verification
• Efficient for highly active circuits, but inefficient for low -activity circuits • Step 2: Initialize internal state variables (flip-flops)
• High-level (e.g., C language) models can be used • Step 3: For each input vector
• Event-driven simulation – Set primary input variables
• Only gates or modules with input events are evaluated ( event means a – Repeat (until steady-state or max. iterations)
signal change ) • Execute compiled code
• Delays can be accurately simulated for timing verification
– Report or save computed variables
• Efficient for low-activity circuits
• Can be extended for fault simulation

9/17/2002 11 9/17/2002 12

2
 9/17/2002

Event-Driven Algorithm Time Wheel (Circular Stack)

Scheduled Activity
(Example) events list
a =1 e =1 Current max
t=0 c= 0 d, e
c =1 0 2 time t=0
1 pointer Event link-list
g =1 1
2
2 2 d = 1, e = 0 f, g 2
d=0

Time stack
3 3
4 f =0
b =1 4 g= 0 4

5 5
g 6 f =1 g
6
0 4 8 7
Time, t 7

8 g= 1
9/17/2002 13 9/17/2002 14

Efficiency of Event-driven
Summary
Simulator • Logic or true-value simulators are essential tools for
• Simulates events (value changes) only
design verification.
• Speed up over compiled-code can be ten times • Verification vectors and expected responses are
or more; in large logic circuits about 0.1 to generated (often manually) from specifications.
10% gates become active for an input change • A logic simulator can be implemented using either
compiled-code or event-driven method.
Steady 0 Large logic • Per vector complexity of a logic simulator is
Steady 0
block without approximately linear in circuit size.
(no event) activity
0 to 1 event
• Modeling level determines the evaluation procedures
used in the simulator.
9/17/2002 15 9/17/2002 16