Digital Logic Design

-Decoder/Encoder – Mux/DeMux-
 Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input.
Two simple decoders that detect the presence of the binary code
A3A2A1A0 = 0011 are shown. (A3 is MSB, A0 is LSB)
The first has an active HIGH output
The second has an active LOW output.
A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

Instr: Dr. Awais M. Kamboh. 2

 Decoders

Assume the output of the decoder shown is a

logic 1. What are the inputs to the decoder?
(A3 is MSB, A0 is LSB)

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

Instr: Dr. Awais M. Kamboh. 3

 Decoders
Only one output of the decoder is ON or 1, for a specific Input
sequence
Assuming 2 inputs there are four possible outputs.
2 Input, 4 Outputs. Can be written as
2-to-4 Decoder or 2x4 Decoder

Input Output Number

A1 A0 D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Instr: Dr. Awais M. Kamboh. 4

 Decoders

IC decoders have multiple outputs to decode any combination of

inputs. For example, the binary-to-decimal decoder shown here
has 16 outputs – one for each combination of binary inputs.

Bin/Dec
0 1
For the input 1010, what 1 1
2 1
is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

Instr: Dr. Awais M. Kamboh. 5

 Decoders
For an active high decoder, only one output of decoder is ON or 1, for
a specific Input sequence

Input Output Number

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

Instr: Dr. Awais M. Kamboh. 6

 Decoders
One Output of Decoder is ON or 1, for a specific Input sequence
Assuming 3 inputs one of 8 outputs is ON

Instr: Dr. Awais M. Kamboh. 7

 Decoders
BCD/DEC (1)
BCD-to-decimal decoders accept a binary 0
(2)
coded decimal input and activate one of ten 1
(3)
2
possible decimal digit indications. (15) (4)
A0 1 3
A1 (14) 2 4
(5)
A2 (13) 4 5
(6)
(12) (7)
A3 8 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
decoder are the sequence 0101, 0110, 9
0011, and 0010. Describe the output.
74HC42

All lines are HIGH except for one active output, which is
LOW. The active outputs are 5, 6, 3, and 2 in that order.

Instr: Dr. Awais M. Kamboh. 8

 Decoders

X/Y
A specific integrated circuit decoder is 0
the 74HC154 (shown as a 4-to-16 1
2
decoder). 3
4
It includes two enable (EN) inputs which A0
5
1 6
must be active to enable the outputs. If A1 2 7
A2
any of these lines is disabled, then all the 4 8
A3 8 9
outputs are disabled. 10
11
Some chips have only one EN pin. 12
13
14
EN1 & 15
EN2 EN
74HC154

Instr: Dr. Awais M. Kamboh. 9

 Decoders
Can you make a 4 x 16 Decoder using two 3 x 8 Decoders ?
D = MSB, A = LSB

Instr: Dr. Awais M. Kamboh. 10

 Encoders
An encoder accepts an active logic level on one of its inputs
and converts it to a coded output, such as to binary.

Input Output
Input = 1 A2 A1 A0
D0 0 0 0
D1 0 0 1
D2 0 1 0
D3 0 1 1
D4 1 0 0
D5 1 0 1
D6 1 1 0
D7 1 1 1

Instr: Dr. Awais M. Kamboh. 11

 Encoders
An encoder accepts an active logic level on one of its inputs
and converts it to a coded output, such as Octal to binary.
Input Output 0
Input=1 A2 A1 A0 1 A0
D0 0 0 0
2
D1 0 0 1
D2 0 1 0
3
A1
D3 0 1 1 4
D4 1 0 0 5
D5 1 0 1 A2
6
D6 1 1 0
D7 1 1 1 7

Instr: Dr. Awais M. Kamboh. 12

 Encoders
An encoder accepts an active logic level on one of its inputs
and converts it to a coded output, such as BCD or binary.

1
A0
Inputs from 1 to 9 2
3
The decimal to BCD is an encoder A1
with an input for each of the ten 4
5 A2
decimal digits and four outputs that 6
7
represent the BCD code for the active 8
digit. A3
9

Instr: Dr. Awais M. Kamboh. 13

 Encoders

Show how the decimal-to-BCD encoder converts the decimal number 3 into a
BCD 0011.

The top two OR gates have ones as indicated with the red lines.
Thus the output is 0011.
1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

Instr: Dr. Awais M. Kamboh. 14

 Multiplexers

A multiplexer (MUX) selects one data line from two or more input
lines and routes data from the selected line to the output. The
particular data line that is selected is determined by the select
inputs.

Two select lines are shown here MUX

0
to choose any of the four data Data
S0 0
1 1
inputs. select S1
D0 0 Data
D1 1 output
Data
D 2
inputs D2
Which data line is selected if 3 3
S1S0 = 10?
D2

Instr: Dr. Awais M. Kamboh. 15

 Multiplexers
Circuit of a 4x1 MUX
S1 S’1 S0 S’0
MUX
S0 0
Data
S1 1
select
Data
D0
D0 0
D 1 output
Data D1
2
inputs D2
3 3

D1
Remember
1. When Select lines 00 Output= D0
2. When Select lines 01 Output= D1 D2
3. When Select lines 10 Output= D2
4. When Select lines 11 Output= D3
D3

Instr: Dr. Awais M. Kamboh. 16

 Demultiplexers

A demultiplexer (DEMUX) performs the opposite function from a

MUX. It switches data from one input line to two or more data
lines depending on the select inputs.

The 74LS138 was introduced previously

DEMUX
as a decoder but can also serve as a A0
Y0
Data
DEMUX. When connected as a DEMUX, select A1
Y1
Y2
data is applied to one of the enable inputs, lines A2 Data
Y3
and routed to the selected output line Y4
outputs
depending on the select variables. Note Input G1
Y5
Enable1 G2A
that the outputs are active-LOW as G2B
Y6
illustrated in the following example… Enable2 Y7

74LS138

Instr: Dr. Awais M. Kamboh. 17

 Demultiplexers

Instr: Dr. Awais M. Kamboh. 18

 Demultiplexers A0
A1
Determine the outputs, given the
A2
inputs shown.
G1
G2A LOW
The output logic is opposite to the input because G2B LOW
of the active-LOW convention. (Red shows the
selected line).
Y0
Y1
DEMUX
Y0 Y2
Data A0
select A1
Y1 Y3
lines Y2
A2 Data Y4
Y3
outputs
Data input G1
Y4 Y5
Y5
Enable1 G2A Y6
Y6
Enable2 G2B
Y7 Y7
74LS138
Instr: Dr. Awais M. Kamboh. 19