SECOND SEMESTER 2023-2024
Course Handout Part II
Date: 09-01-2024
In addition to part-I (General Handout for all courses appended to the time table) this portion gives further
specific details regarding the course.
Course No. : EEE F348
Course Title : FPGA Based System Design Laboratory
Instructor-in-Charge : Dr. Amit Kumar Panda
Instructors : Himanshi Awasthi
Scope and Objective of the Course:
HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to
quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify
operation of the physical implementation. It combines together the flexibility of a microprocessor and high
performance of an Application Specific Integrated Circuit (ASIC). The ease of programming and debugging
with FPGAs, as compared to ASICs, decreases the overall non-recurring-engineering (NRE) costs and time-to-
market of FPGA-based products. In this lab-oriented course, students will develop their skills by working on
more challenging digital system design using Verilog hardware description language (HDL) in an industry-
standard design environment. Students will also implement real-world designs in field programmable gate
arrays (FPGAs) as well as test and optimize the FPGA-implemented systems.
Textbooks :
1. FPGA prototyping by Verilog examples By Pong P. Chu., Wiley, 2008
2. FPGA tutorial by Xilinx (http://www.xilinx.com/training/fpga-tutorials.htm#ISE)
3. Wolf Wayne, FPGA Based System Design, Pearson Edu, 2004.
4. Verilog HDL: A Guide to Digital Design and Synthesis Book by Samir Palnitkar
Course Plan:
The practices are intended to provide hands-on experience on the simple Verilog code writing to implement on
fpga. Then the real life examples will be taken and will be implemented. Then some interface examples will be
experimented. Finally, some complex problem will be taken and will be worked by students in project mode.
PTO.
List of Experiments
INTRO LAB: Introduction to FPGA Based System Design and Basic Verilog (1 to 2 classes)
LAB 1a: Demonstration of Design and Synthesis of digital block using Verilog
LAB 1b: Verilog modeling style and synthesis results
LAB 2: Implementation of simple combinational design in Xilinx ZED Board
LAB 3: Implementation of simple Sequential design in Xilinx ZED Board
LAB 4: Design of A Counter Using the On Board Clock
LAB 5: Design and implement Finite State Machine (FSM)
LAB 6: Design and implement a traffic light control circuit
LAB 7: Demonstration of IP Integrator
LAB 8: FPGA System design Using IP
Integrator LAB 9: Hardware Debugging using
VIO
LAB 10: Design of an ALU and hardware debugging using VIO
LAB 11: Integrated logic analyzer (ILA) core for hardware debugging
LAB 12: Creating a MAC Using the Xilinx System Generator and Implementation on Hardware
LAB 13: FIR Filter design Using the Xilinx System Generator and Verilog – Analysis of resourse utilization.
LAB 14: Black Box Using the Xilinx System Generator: Importing a Verilog Module
LAB 15: Designing FIR filter using theVivado System Generator’s FIR and FDA Tool blocks
Assignment
Final Project
Evaluation Scheme:
Weightage Nature of
Component Duration Date & Time
(%) Component
Laboratory Practical 4 hours/
35% Regular lab Performance Open book
Regular class work week
Project/Assignment 30% Will be announced Open book
Lab Quiz 20% Will be announced Closed book
To be
Lab Exam 15% Will be announced
announced
Chamber Consultation Hour: Chamber consultation hours of Instructors will be announced separately.
Notices: All notices of this course will be displayed in CMS
Make-up Policy: No makeup is allowed for lab evaluation. The best n-1 labs will be considered, where n is the total
number of labs that will be conducted. However, a student can perform the missed experiment in a free time slot available
in the lab.
Academic Honesty and Integrity Policy: Academic honesty and integrity are to be maintained by all the students
throughout the semester and no type of academic dishonesty is acceptable.
INSTRUCTOR-IN-CHARGE
