SMPS IC

SmartrectifierTM
IR11688S

DUAL SYNCHRONOUS RECTIFICATION CONTROL IC

Features Product Summary

• Secondary-side high speed synchronous
Topology LLC Half-bridge
rectification controller for resonant half bridge
converters VD 200V
• Direct sensing of MOSFET drain voltage up to 200V
• Operates up to 400kHz switching frequency VOUT Vcc
• Programmable Minimum On Time Io+ & I o- +1A & -4A
• Anti-bounce logic and UVLO protection
• Linear turn-off phase to compensate for premature
switch off due to parasitic inductance Package Options
• 4A peak turn off drive current
• Micropower start-up & ultra-low quiescent current
• 50ns turn-off propagation delay
• Wide Vcc operating range 4.75V to 18V
• Cycle by Cycle MOT Protection
• Auto low power mode standby mode
• Improved noise immunity 8-Pin SOIC
• Compatible with Energy Star low standby power
• Lead-free

Typical Applications
• Desktop SMPS, Server SMPS, AC-DC adapters,
LCD & PDP TV, Telecom SMPS

Ordering Information
Standard Pack
Base Part Number Package Type Complete Part Number
Form Quantity

IR11688S SOIC8N Tape and Reel 2500 IR11688STRPBF

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 IR11688S

Typical Connection Diagram

Gate1 Gate2
1 8
VCC GND

IR11688
2 7
Cout LOAD
MOT VS
3 6
VD1 VD2
4 5

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Table of Contents Page

Ordering Information 1

Description 4

Absolute Maximum Ratings 5

Electrical Characteristics 6

Functional Block Diagram 8

Input/Output Pin Equivalent Circuit Diagram 9

Pin Definitions 10

Pin Assignments 10

Application Information and Additional Details 12

Package Details 23

Tape and Reel Details 24

Part Marking Information 25

Qualification Information 26

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 IR11688S

Description
The IR11688 is a dual smart secondary-side controller IC optimized to drive two N-Channel power MOSFETs
configured for synchronous rectification in resonant converter applications. Each channel can drive one or multiple
parallel MOSFETs to emulate the behavior of Schottky diode rectifiers, bypassing the body diodes for the majority
of each conduction period to minimize power dissipation and remaining off during the blocking period.
The drain to source voltage of each rectifier MOSFET is sensed to determine the source to drain current and turn
each gate on rapidly at the start of each conduction cycle and off in close proximity to the zero current transitions
for each branch of the output rectifier circuit. Ruggedness and noise immunity are accomplished using an
advanced blanking scheme and double-pulse suppression that allows reliable operation in fixed and variable
frequency applications.
The programmable minimum on time (MOT) function provides flexibility to work over a wide range of switching
frequencies. The cycle-by-cycle MOT protection circuit is able to automatically detect a light or no load condition so
that the gate drives may be disabled to avoid unwanted reverse currents flowing through the MOSFETs.
The IR11688 has a wide Vcc supply voltage range from 4.75V to 18V, enabling its supply to be derived from the
output and eliminating the need for an auxiliary supply circuit in systems with output voltage as low as 5V.
The IR11688 also has very low quiescent current when the gate drives are not switching to offer minimal power
consumption in standby mode.

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Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any pin. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.

Parameters Symbol Min. Max. Units Remarks

Supply Voltage VCC -0.3 20 V
Cont. Drain Sense Voltage VD1,2 -1 200 V
Pulse Drain Sense Voltage VD1,2 -3 200 V
Source Sense Voltage VS -1 5 V
Gate Voltage VGATE1,2 -0.3 Vcc+0.3 V
MOT Voltage VMOT -0.3 3.5 V
Operating Junction Temperature TJ -40 150 °C
Storage Temperature TS -55 150 °C
Thermal Resistance RθJA 128 °C/W SOIC-8
Package Power Dissipation PD 970 mW SOIC-8, TAMB=25°C

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.
Symbol Definition Min. Max. Units
VCC Supply voltage 4.75 18
① V
VD Drain Sense Voltage -3 200
TJ Junction Temperature -40 125 °C
Fsw Switching Frequency --- 400 kHz

① VD -3V negative spike width ≤100ns

Recommended Component Values

Symbol Component Min. Max. Units
RMOT MOT pin resistor value 20 150 kΩ

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 IR11688S

Electrical Characteristics
VCC=12V, TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are
referenced to GND (pin7).

Supply Section
Parameters Symbol Min. Typ. Max. Units Remarks
Supply Voltage Operating
Range VCC 4.75 18 V
VCC Turn On Threshold VCC ON 4.35 4.55 4.75 V
VCC Turn Off Threshold
VCC UVLO 4.15 4.35 4.55 V
(Under Voltage Lock Out)
VCC Turn On/Off Hysteresis VCC HYST --- 0.2 --- V
CLOAD =1nF, fSW = 400kHz,
Operating Current
ICC --- 13 15 mA RMOT=50kΩ
No switching at VD pins and after
Quiescent Current TWAIT is exceeded, VD=2V,
IQCC --- 320 500 µA RMOT=50kΩ
Start-up Current ICC START --- 40 80 µA VCC=VCC ON - 0.1V
Quiescent waiting time TWAIT 340 570 800 µS

Comparator Section
Parameters Symbol Min. Typ. Max. Units Remarks
Turn-off Threshold VTH1 -7 -4 0 mV VS=0V
Regulation Threshold VTHR -50 -40 -30 mV 10mV hysteresis (-50mV/-40mV)
Turn-on Threshold VTH2 -263 -230 -197 mV
Hysteresis VHYST --- 230 --- mV GBD
Input Bias Current IIBIAS1 -7.5 -5 --- µA VD = -50mV
Input Bias Current IIBIAS2 --- 7 10 µA VD = 200V
Turn-on Blanking time TBon --- 150 --- ns GBD

One-Shot Section
Parameters Symbol Min. Typ. Max. Units Remarks
Blanking pulse duration tBLANK 8 15 24 µs
Reset Threshold VTH3 1.06 1.18 1.31 V
Reset Delay tBRST --- 400 --- ns
Hysteresis VHYST3 --- 40 --- mV GBD

Minimum On Time Section

Parameters Symbol Min. Typ. Max. Units Remarks
375 500 625 ns RMOT =24kΩ, VCC=5V
Minimum on time TOnmin
0.75 1 1.25 µs RMOT =50kΩ, VCC=5V

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 IR11688S

Electrical Characteristics
VCC=12V, TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are
referenced to GND (pin7).

Gate Driver Section

Parameters Symbol Min. Typ. Max. Units Remarks
Gate Low Voltage VGLO --- 0.15 0.25 V IGATE = 100mA
--- 11.9 --- GBD
Gate High Voltage VGTH V
--- 4.9 --- GBD
Rise Time tr --- 20 38 ns CLOAD = 1nF
Fall Time tf --- 10 22 ns CLOAD = 1nF
VDS to VGATE – VDS goes down
Turn on Propagation Delay tDon --- 200 250 ns from 6V to -1V
VDS to VGATE –VDS goes up from
Turn off Propagation Delay tDoff --- 42 60 ns -1V to 6V
Pull up Resistance rup --- 6 --- Ω GBD
Pull down Resistance rdown --- 1.5 --- Ω IGATE = -100mA
Output Peak Current
(source) IO source --- 1 --- A GBD
Output Peak Current (sink) IO sink --- 4 --- A GBD

GBD – parameter is guaranteed by design and is not tested.

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Functional Block Diagram

VCC

UVLO
&
VTHR Internal Bias

VTH3 RESET

VCC
Min ON Time
(With Cycle by Cycle
150ns
MOT Check Circuit)

VD1
VS

Min OFF Time GATE1

MOT
MOT
PGEN
Shoot-through
Protection
Logic

Min ON Time
150ns
(With Cycle by Cycle
MOT Check Circuit)

VD2

GATE2
VCC Min OFF Time
GND

RESET

VTH3 VTHR

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I/O Pin Equivalent Circuit Diagram

VCC
VD1
VD2 RESD
ESD ESD
Diode Diode

GATE1
GATE2
ESD
200V Diode
Diode

GND GND

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Pin Definitions

PIN# Symbol Description

1 GATE1 Gate Drive Output 1
2 VCC Supply Voltage
3 MOT Minimum On Time Programmable pin
4 VD1 Sync FET 1 Drain Voltage Sense
5 VD2 Sync FET 2 Drain Voltage Sense
6 VS Sync FET Source Voltage Sense
7 GND Analog and Power Ground
8 GATE2 Gate Drive Output 2

Pin Assignments

Gate1 Gate2
1 8
VCC GND
IR11688

2 7
MOT VS
3 6
VD1 VD2
4 5

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Detailed Pin Description

VCC: Power Supply

This is the supply voltage pin of the IC, monitored by the under voltage lockout circuit. It is possible to turn off the
IC entering UVLO mode by pulling this pin below the minimum turn off threshold voltage for micro power
consumption.
To prevent noise interfering with operation, a ceramic decoupling capacitor should be connected from Vcc to GND
and located as close to the IC as possible. A low value series resistor may also be added to the Vcc supply circuit
for filtering if required. Vcc is internally clamped at around 20V.

GND: Ground
This is power ground connection to the IC. Internal circuit blocks and gate drivers are referenced to this point.

MOT: Minimum On Time

The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed at either VD input, the
corresponding gate drive output will transition high to turn on the SR MOSFET. Spurious ringing and oscillations
can falsely trigger the input comparator to prematurely switch the output off. During the MOT period the input
comparator is disabled maintaining conduction through the MOSFET on for this preset minimum period.
The MOT is typically programmed between 500ns and 2us by means of an external resistor referenced to GND.

VD1 and VD2: Drain Voltage Sense

The VD pins are the voltage sensing inputs for the SR MOSFET drains. These are high voltage inputs therefore
particular care must be taken in properly routing the connections. Additional RC filters can be placed at these
inputs to improve noise immunity, however only a small resistor (≤1kΩ) and capacitor value (in the pF range) may
be used to avoid introducing excessive delay to the control input.

VS: Source Voltage Sense

This is the signal ground for the sources of the two SR power MOSFETs to provide an accurate differential voltage
measurement. Kelvin connect this pin to the source of MOSFET2 (channel 2 MOSFET) is recommended if the two
MOSFETs are far apart to each other.

GATE1 and GATE2: Gate Drive Outputs

Each gate driver output has +1A/-4A peak drive capability. Although these pins can be directly connected to the
SR MOSFET gates the use of gate resistors is recommended, especially when using several MOSFETs in parallel.
Care must be taken to keep the gate loop as short and as tight as possible in order to achieve optimal switching
performance.

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Application Information and Additional Details

State Diagram
POWER ON
Gate Inactive

UVLO/SLEEP MODE
VCC < VCCon
Gate Inactive
ICC max = 200uA

VCC > VCCon,

VDS>VTH3 two edges
VCC < VCCuvlo
or
NORMAL No VD edge > Twait
Gate Active
Gate PW ≥ MOT
Cycle by Cycle MOT Check Enabled

VDS>VTH1 @ MOT VDS<VTH1 @ MOT

MOT PROTECTION MODE

Gate Output Disabled

UVLO/SLEEP Mode
The IC remains in the UVLO/SLEEP condition until the voltage at the VCC pin first exceeds the VCC turn on
threshold voltage, VCC ON. While in the UVLO/SLEEP state, the gate drive outputs are inactive and only a very small
quiescent current of ICC START is drawn. UVLO mode is accessible from any other state of operation whenever the IC
supply voltage condition of Vcc < VCC UVLO occurs. If during normal operation, the drain inputs remain inactive such
that no edges are detected for a period longer than TWAIT the IC enters SLEEP mode. It remains in a low power
state until woken up by a voltage transition at either VD input.

Normal Mode
The IC enters into normal operating mode when the VCC ON threshold has been exceeded. On entering Normal
Mode from the UVLO Mode the GATE outputs remain disabled until VDS transitions above VTH3 two times. This
ensures that the GATE output cannot be enabled in the middle of a switching cycle since this can cause undesired
reverse conduction. The cycle by cycle minimum on time (MOT) protection circuit also becomes activated to
prevent reverse currents occurring when conduction time is short, which may also happen during system power up
and down. The gate drives will continuously drive the MOSFETs after this startup sequence is completed.

MOT Protection Mode

If secondary current conduction time in either rectifier circuit branch is shorter than the set MOT, the subsequent
gate driver output pulse is skipped. This function avoids reverse current from occurring when the system is
switching at very low duty-cycles under very light or zero load conditions. The cycle by cycle MOT check circuit
always remains active in Normal Mode and MOT Protection Mode so that the IC will automatically resume normal
operation only after the load increases to a level where the secondary current conduction time exceeds MOT.
System standby power consumption is significantly reduced in this mode while the gate outputs are inactive.

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 IR11688S

General Description
TM
The IR11688 dual SMART RECTIFIER controller is a high-voltage IC for synchronous rectification designed for
resonant converter applications. As stated, it emulates the operation of two diodes configured with a center tapped
transformer secondary by correctly switching on and off the synchronous rectifier MOSFETs in the two rectifier
circuit branches.
The core of this device consists of two high-voltage drain sensing inputs feeding high speed comparators to
differentially sense the drain to source voltage at each SR MOSFET. The SR MOSFET source to drain current is
detected from the voltage across the conducting body diode or the RDSON resistance when switched on. Internal
control logic allows the corresponding gate drive output to be switched on and off at the correct time to bypass the
body diode for the majority of the conduction period.

The IR11688 further simplifies synchronous rectifier control by offering the following power management features:

• Wide VCC operating range allows the IC to be supplied from the converter output
• Shoot through protection logic that prevents both GATE outputs from ever being high at the same time
• Turn-off phase regulation to compensate for power device package inductance and avoid premature turn-
off
• Optimized negative turn on voltage threshold detection and leading edge noise filter to minimize false
triggering due to ringing oscillations

The IR11688 control technique senses SR MOSFET source to drain voltages comparing them with three different
negative thresholds (VTH1, VTH2 and VTHR) to precisely control gate turn on and off as shown in figure 1:

VGATE

VTH2 VTHR VTH1 VDS

Figure 1: Input comparator thresholds

Turn-on phase
When the conduction phase of each SR MOSFET begins, the device is off so therefore current starts to flow
through the body diode producing a negative VDS voltage across it. The body diode has a much higher voltage
drop than the one resulting from the MOSFET on resistance and is therefore sufficient to trigger the turn-on
threshold VTH2.
When either VDS input remains below VTH2 for more than TBon (150ns), the gate of the corresponding SR MOSFET
is driven high, which causes VDS to reduce rapidly to ID x RDSON. The internal delay timer will be reset if VDS rises
above VTH2 before TBon times out. This turn-on blanking time helps to avoid misfiring that could be triggered by high
frequency ringing in DCM operation. The voltage drop at switch on is usually accompanied by some amount of
ringing, which could potentially trigger the input comparator to turn off the gate drive very quickly. However the
minimum on time (MOT) blanking period prevents this. The turn-on blanking time (TBon) and the MOT limit the
minimum conduction time for the secondary rectifiers determining the switching frequency upper limit that the
IR11688 may effectively operate at.

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Regulation phase
After the gate has been driven high at switch on, the SR MOSFET remains on until the source to drain current falls
to the level where VDS reaches the regulation threshold VTHR. At the end of the MOT, the gate output is no longer
driven high and reverts to a high impedance state. When VDS<VTHR a weak pull down gradually discharges the
gate voltage held by the SR MOSFET input capacitance. As the gate voltage drops, the MOSFET channel
resistance increases as it enters the linear region. This causes VDS to once again exceed VTHR so that weak pull
down will cease until the conduction current falls to the point where VDS again drops below VTHR. This regulating
process continues so that the conduction period is extended until the current has fallen to a very low level. In this
way premature turn off, which can arise due to parasitic inductances in PCB traces and the MOSFET package, is
prevented. This period of conduction through the SR MOSFET body diodes is thereby reduced to a minimum
improving overall system efficiency.

Turn-off and reset phases

At the end of the switching cycle the conduction rectifier current reduces to zero so the VDS voltage will cross the
turn-off threshold VTH1. When this happens the gate is driven low to switch off the SR MOSFET. Any residual
current will again start flowing through the body diode causing a negative step in VDS. When this occurs VDS could
potentially trigger turn-on once again by crossing VTH2. To prevent this possibility, turn on is blanked for a time
period, tBLANK after turn off has occurred. The blanking time is internally set and can be reset only when VDS
crosses the positive threshold VTH3. Reset occurs only when VDS remains higher than VTH3 for more than the reset
blanking time, tBRST. This protects against false triggering due to ringing after the turn-off phase. Once reset the
IR11688 is re-armed so that turn on may be triggered for the next conduction cycle.

VTH3
IDS DCM ringing

VDS
(across
MOSFET)

T1 T2
VTH1
VTHR

VTH2

Tbrst
TDon TBon
TDoff
Gate Drive <TBon

VDS pulse < TBon VDS pulse > TBon

Gate stays off Gate turns on
Blanking

MOT tBLANK MOT

time

Figure 2: Secondary currents and voltages

Programmable Minimum On Time

The minimum on time is set by an external resistor (RMOT) connected between the MOT pin and ground. The
minimum on time can be calculated based on below equation:

TMOT = RMOT x 2 x 10-11 + 20ns

where 20ns is the typical internal comparator propagation delay.

RMOT value should remain within the upper and lower limits specified under recommended operating conditions.

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 IR11688S

MOT protection
Under very light load or zero load conditions, the current in the SR MOSFETs becomes discontinuous and may be
shorter than the MOT time in some cases. If this happens, reverse current will flow from the drain to source at the
end of the MOT since the gate drive has been kept on. This reverse current discharges the converter output
capacitor sending energy back to the transformer and resonating to cause voltage ringing at VDS at switch off.
Such ringing may potentially trigger gate turn on leading to further reverse current and subsequent multiple falsely
triggered erroneous gate pulses as illustrated below in Figure 4:
VDS

IDS
Gate

MOT
Figure 3: Waveform without MOT protection

The cycle-by-cycle MOT protection function detects reverse current at the end of the MOT period and disables the
following gate output pulse preventing further reverse current. The internal comparator and MOT pulse generator
continue to operate under the protection mode even when the gate drive is disabled. This enables the circuit to
continuously monitor the system load current and automatically revert to normal operating mode once the load
current conduction time has again increased to be longer than the MOT. This protection function reduces standby
power losses and can also prevent voltage spikes caused by false triggering at light load.

VDS

IDS

Gate Low
Figure 4: Waveform under MOT protection mode

Synchronized Enable Function

Sync Enable function ensures that gate turn on always occurs at the beginning of a switching cycle.

VGATE
VDS
UVLO
Idrain
Vth3

IC activated in the middle of a

VD>Vth3 for 2 cycles Vgate has output from the 3rd cycle
conduction cycle, VGATE stays low.

Figure 5: Synchronized Enable Function

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 IR11688S

Driving Logic Level MOSFET

An external gate clamping circuit is recommended when driving logic level SR MOSFETs. The clamping circuit
keeps the gate voltage below 1V during system power up when the IR11688 is not fully biased in UVLO mode,
especially when Vcc is less than 2V. It is not recommended to drive logic level MOSFETs with the IR11688 without
a safety clamping circuit.
Note the gate regulation feature will be lost when using PNP transistor clamping circuit. Use MOSFET clamping
circuit (figure 7) if regulation function is needed.

SR MOSFET 1 SR MOSFET 2
Rg1 Gate1 Gate2 Rg2
1 8
VCC GND

IR11688
2 7
CVcc MOT VS
3 6
VD1 VD2
4 5

Rb1 RMOT Rb2

Figure 6: PNP transistor gate clamping circuit for driving logic level MOSFET

SR MOSFET
Rg1 Gate1 Gate2 Rg2
1 8 SR MOSFET
VCC GND
IR11688

2 7
CVcc
3 6

4 5 Clamp FET2

Clamp FET1 250k

2M
Clamp FET3
1M

Figure 7: Signal MOSFET gate clamping circuit for driving logic level MOSFET

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 IR11688S

VTH1

VDS

VTH2

t Don t Doff
VGate
90%

10%

t rise tfall

Figure 8: VD and gate drive output timing

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 IR11688S

Figure 9: Undervoltage Lockout vs. Temperature Figure 10: Icc Quiescent Current vs. Temperature

Figure 11: Icc supply current at 1nF load vs. Temperature Figure 12: Icc Startup Current vs. Temperature

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 IR11688S

Figure 13: VD bias at -50mV vs. Temperature Figure 14: VD bias at 200V vs. Temperature

Figure 15: VTH1 Threshold vs. Temperature Figure 16: VTH2 Threshold vs. Temperature

(Red curve channel 1, Blue curve channel 2)

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Figure 17: VTH3 Threshold vs. Temperature Figure 18: TBRST Reset Time vs. Temperature

Figure 19: VTHR+ Threshold vs. Temperature Figure 20: VTHR- Threshold vs. Temperature

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 IR11688S

Figure 21: Minimum On Time vs. Temperature Figure 22: TWAIT Wait Time vs. Temperature

Figure 23: TBLANK Blanking Time vs. Temperature Figure 24: Gate Pull Down Resistance vs. Temperature

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 IR11688S

Figure 25: Gate Rise and Fall Time vs. Temperature (CH1) Figure 26: Gate Rise and Fall Time vs. Temperature (CH2)

Figure 27: TDON Propagation Delay vs. Temperature Figure 28: TDOFF Propagation Delay vs. Temperature

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 IR11688S

Package Details: SOIC8N

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 IR11688S

Tape and Reel Details: SOIC8N

LOADED TAPE FEED DIRECTION

B A H

F C

NOTE : CONTROLLING
DIM ENSION IN M M E

CARRIER TAPE DIMENSION FOR 8SOICN

Metric Imperial
Code Min Max Min Max
A 7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D 5.45 5.55 0.214 0.218
E 6.30 6.50 0.248 0.255
F 5.10 5.30 0.200 0.208
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062

B
C
A
E

REEL DIMENSIONS FOR 8SOICN

Metric Imperial
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 18.40 n/a 0.724
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566

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 IR11688S

Part Marking Information

Part number 11688

Date code YWW ? IR logo

Pin 1 C XXXX Lot Code

Identifier
(Prod mode –
4 digit SPN code)
? MARKING CODE
P Lead Free Released
Assembly site code
Per SCOP 200-002

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 IR11688S

Qualification Information†
††
Industrial
Comments: This family of ICs has passed JEDEC’s Industrial
Qualification Level
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
†††
MSL2 260°C
Moisture Sensitivity Level SOIC8N
(per IPC/JEDEC J-STD-020)
Class A
Machine Model
(per JEDEC standard JESD22-A115)
ESD
Class 1C
Human Body Model
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I Level A
IC Latch-Up Test
(per JESD78)
RoHS Compliant Yes

† Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-

info/reliability/
†† Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
††† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.

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 IR11688S

Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated
herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims
any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of
intellectual property rights of any third party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated
in this document and any applicable legal requirements, norms and standards concerning customer’s products
and any use of the product of Infineon Technologies in customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.

For further information on the product, technology, delivery terms and conditions and prices please contact your
nearest Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications
where a failure of the product or any consequences of the use thereof can reasonably be expected to result in
personal injury.

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