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L08-09 Verilog - Assignment Statements

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26 views16 pages

L08-09 Verilog - Assignment Statements

Uploaded by

Moazzam Nafees
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE-421: Digital System Design

Assignment Statements:
Blocking (=) vs Non-Blocking (<=)

Dr. Rehan Ahmed [[email protected]]


Statements Ordering in an
Always Block

2
Always Block: Statements Order
• An important property of the always block is that:
– the statements it contains are evaluated in the order given
in the code:
▪ [STATEMENTS ORDER IS IMPORTANT]

– [!!!] This contrasts with the continuous assignment


statements (recall assign statement), which are evaluated
concurrently and hence have no meaningful order!

3
Example: Statement Ordering inside an Always
block
module mux (w0, w1, s, f); module mux (w0, w1, s, f);
input w0, w1, s; input w0, w1, s;
output reg f; output reg f;
always @(w0, w1, s) always @(w0, w1, s)
begin begin
f = w0; if (s == 1)
if (s == 1) f = w1;
f = w1; f = w0;
end end
endmodule endmodule
Still a MUX Not a MUX Anymore

Verilog semantics specify that a signal assigned multiple values in


an always construct retains the last assignment.

4
Verilog Procedural
Assignment Statements

5
Procedural Assignment Statements
• There are two kinds of assignments in an always block:
1. Blocking assignments,
▪ denoted by the = symbol

2. Non-blocking assignments,
▪ denoted by the <= symbol.

6
Blocking and Non-Blocking Assignments

Blocking (=) Non-blocking (<=)


always @ (a) always @ (a)
begin begin
a = 2’b01; a <= 2’b01;
// a is 2’b01 b <= a;
b = a; // all assignments are made here
// b is now 2’b01 as well // b is not (yet) 2’b01
end end

◼ Each assignment is made ◼ All assignments are made


immediately at the end of the block
◼ Process waits until the first ◼ All assignments are made
assignment is complete, it in parallel, process flow is
blocks progress not-blocked

7
Example:
Blocking and Non-Blocking Assignments

Credit: Altera Tutorial – Verilog HDL Basics 8


Example: Blocking Assignment

◼ Assume all inputs are initially ‘0’

always @ ( * )
begin
p = a ^ b ; // p = 0 1
g = a & b ; // g = 0 0
s = p ^ cin ; // s = 0 1
cout = g | (p & cin) ; // cout = 0 0
end

◼ If a changes to ‘1’
❑ All values are updated in order they are specified!

9
The Same Example:
Non-Blocking Assignment

◼ Assume all inputs are initially ‘0’

always @ ( * )
begin
p <= a ^ b ; // p = 0 1
g <= a & b ; // g = 0 0
s <= p ^ cin ; // s = 0 0
cout <= g | (p & cin) ; // cout = 0 0
end

◼ If a changes to ‘1’
❑ All assignments are concurrent
❑ When s is being assigned, p is still 0

10
Summary:
Blocking and Non-Blocking Assignments
• There are two kinds of assignments in an always block:
1. Blocking assignments,
▪ denoted by the = symbol
▪ Executed in the order they are specified in a sequential block

2. Non-blocking assignments,
▪ denoted by the <= symbol
▪ Allow scheduling of assignments without blocking execution of
the statements that follow in a sequential block

11
Synthesis of
Blocking vs Non-Blocking
Assignments

16
Example: Blocking vs Non-Blocking
• Draw the circuit (netlist) corresponding to each of the
following code snippets:

21
Example: Blocking vs Non-Blocking

• There are two key aspects of the Verilog semantics relevant to this code:
– 1. The results of non-blocking assignments are visible only after all of
the statements in the always block have been evaluated.
– 2. When there are multiple assignments to the same variable inside an
always block, the result of the last assignment is maintained.
22
Blocking vs Non-Blocking: Avoid Confusion
• Notion of “current time step” is tricky in synthesis, so to
guarantee that your simulation matches the behavior of
the synthesized circuit, follow these rules:
1. Use blocking assignments to model combinational logic
within an always block.
2. Use non-blocking assignments to implement sequential
logic.
3. Do not mix blocking and non-blocking assignments in the
same always block.
▪ It is not possible to model both a combinational output and a
sequential output in a single always block.
4. Do not make assignments to the same variable from more
than one always block:
▪ Would yield multi-driver synthesis error; example ahead
– not possible electrically, by the way!

23
THANK YOU

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