Unit -2

In ripple carry adders, for each adder block, the two bits that are to be added are
available instantly. However, each adder block waits for the carry to arrive from
its previous block. So, it is not possible to generate the sum and carry of any

block until the input carry is known. The ith block waits for the i-1 block
to produce its carry. So there will be a considerable time delay which is carry
propagation delay.
Here a carry signal will be generated in two cases:
1. Input bits A and B are 1
2. When one of the two bits is 1 and the carry-in is 1.

Consider the above 4-bit ripple carry adder. The sum S3 is produced by the
corresponding full adder as soon as the input signals are applied to it. But the
carry input C1 is not available on its final steady-state value until carry C3 is

available at its steady-state value. Similarly C3 depends on C2 and C1.

Therefore, though the carry must propagate to all the stages in order that
output S3 and carry C4 settle their final steady-state value.

Carry Look-ahead Adder :

A carry look-ahead adder reduces the propagation delay by introducing more

complex hardware. In this design, the ripple carry design is suitably transformed
such that the carry logic over fixed groups of bits of the adder is reduced to two-
level logic. Let us discuss the design in detail.
Consider the full adder circuit shown above with corresponding truth table. We

define two variables as ‘carry generate’ Gi and ‘carry propagate’ Ci

then,
The sum output and carry output can be expressed in terms of carry generate Gi
and carry propagate Pi as

From the above Boolean equations we can observe that C4 does not have to wait
for C3 and C2 to propagate but actually C4 is propagated at the same time as C3
and C2.

.
BOOTH ALGORITHM:
Multiply the two numbers 23 and -9 by using the Booth's multiplication
algorithm.

Array multiplier
Shift Micro-Operations

Shift micro-operations are those micro-operations that are used for serial transfer
of information. These are also used in conjunction with arithmetic micro-
operation, logic micro-operation, and other data-processing operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for logical
shift-left and shr for shift-right.
Logical Shift Left

Right Logical Shift

2. Arithmetic :

This micro-operation shifts a signed binary number to the left or to the right
position. In an arithmetic shift-left, it multiplies a signed binary number by 2 and
In an arithmetic shift-right, it divides the number by 2.

Left Arithmetic Shift

Right Arithmetic Shift

3. Circular :

The circular shift circulates the bits in the sequence of the register around the
both ends without any loss of information.

Left Circular Shift

Right Circular Shift

Hardware Implementation Of Unsigned Binary Multiplication:

Multiplying Positive Numbers:

M=11(1011)

Q=13(1101)
Binary Adder-Subtractor

A Binary Adder-Subtractor is one which is capable of both addition and

subtraction of binary numbers in one circuit itself. The operation being
performed depends upon the binary value the control signal holds. It is one of the
components of the ALU (Arithmetic Logic Unit).
This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and
Subtraction, Full Adder.
Lets consider two 4-bit binary numbers A and B as inputs to the Digital Circuit
for the operation with digits
o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder
and when the mode input is at a high logic, i.e. '1', the circuit act as a
subtractor.
o The exclusive-OR gate connected in series receives input M and one of the
inputs B.
o When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit
performs A plus B.
o When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The
circuit performs the operation A plus the 2's complement of B.
Restoring Division Algorithm For Unsigned Integer

Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A
will contain value 0, register M will contain Divisor, register Q will contain Dividend, and N is
used to specify the number of bits in dividend.

Step 2: In this step, register A and register Q will be treated as a single unit, and the value of
both the registers will be shifted left.

Step 3: After that, the value of register M will be subtracted from register A. The result of
subtraction will be stored in register A.

Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then the
least significant bit of register Q will be set with a value 1. If the most significant bit of A is 1,
then the least significant bit of register Q will be set to with value 0, and restore the value of A
that means it will restore the value of register A before subtraction with M.

Step 5: After that, the value of N will be decremented. Here n is used as a counter.
Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to
step 2.

Step 7: This is the last step. In this step, the quotient is contained in the register Q, and the
remainder is contained in register A.

Perform Division Restoring Algorithm

Dividend = 11
Divisor = 3

Floating Point Addition and subtraction

 We follow these steps to add/sub two numbers:

1. Align the significant

2. Add the significant

3. Normalize the result

ALU Design
ALU is a major component in the processor, the ALU's design and function may be different in
the different processors. For case, some ALUs are designed to perform only integer calculations,
and some are for floating-point operations. Some processors include a single arithmetic logic unit
to perform operations, and others may contain numerous ALUs to complete calculations. The
operations performed by ALU are:

o Arithmetic Operations: Although it performs multiplication and division, this refers to bit
addition and subtraction. But multiplication and division operations are more costly to make. In
the place of multiplication, addition can be used as a substitute and subtraction for division.
o Logical Operations: The logical operations consist of NOR, NOT, AND, NAND, OR, XOR,
and more.
o Bit-Shifting Operations: It is responsible for displacement in the locations of the bits to the by
right or left by a certain number of places that are known as a multiplication operation.

1. Arithmetic Circuit

The circuit whose one stage is given in the below diagram provides 8 arithmetic operations, 4
logic operations, and 2 shift operations, and Each operation is selected by the 5 variables S3,
S2, S1, S0, and Cin.
The below table shows the 14 operations perform by the Arithmetic Logic Unit:
1. The first 8 are arithmetic operations which are selected by S3 S2 = 00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 = 10 & 11
4.

2. Logic unit
.Figure below shows one stage of a circuit that generates the four basic logic rnicrooperations .It
consists of four gates and a multiplexer. Each of the four logic operations is generated through
a gate that performs the required logic. The outputs of the gates are applied to the data inputs of
the multiplexer. The two selection inputs S 1 and S0 choose one of the data inputs of the
multiplexer and direct its value to the output.
The diagram shows one typical stage with subscript i. For a logic circuit with n bits, the
diagram must be repeated n times for i = 0, 1, 2, ... , n - 1.The selection variables are applied to
all stages. The function table in Fig. below lists the logic rnicrooperations obtained for each
combination of the selection variables.
Hardware Implementation

A possible choice for a shift unit would be a bidirectional shift register with parallel load
Information can be transferred to the register in parallel and then shifted to the right or left. In
this type of configuration, a clock pulse is needed for loading the data into the register, and
another pulse is needed to initiate the shift.

In a processor unit with many registers it is more efficient to implement the shift operation with
a combinational circuit.
In this way the content of a register that has to be shifted is first placed onto a common bus
whose output is connected to the combinational shifter, and the shifted number is then loaded
back into the register.This requires only one clock pulse for loading the shifted value into the
register.
A combinational circuit shifter can be constructed with multiplexers as shown in Fig. below.
The 4-bit shifter has four data inputs, A0 through A3, and four data outputs, H0 through H3.
 There are two serial inputs, one for shift left
4 Bit-ALU design

Arithmetic Logic Shift Unit (ALSU) is a member of the Arithmetic Logic Unit (ALU) in a
computer system. It is a digital circuit that performs logical, arithmetic, and shift operations.
Rather than having individual registers calculating the micro operations directly, the computer
deploys a number of storage registers which is connected to a common operational unit known as
an arithmetic logic unit or ALU.

Now, to implement the micro operation, the contents of specified registers are allocated in the
inputs of the common Arithmetic Logic Unit. The Arithmetic Logic Unit performs an operation
that leads as a result and gets transferred to a destination register. Arithmetic Logic Unit may be
a combinatory circuit in order that the complete register transfer operation from the supply
registers through the ALU and into the destination register is performed throughout one clock
pulse amount. Sometimes, the shift micro operations are performed in a separate unit, but
sometimes it is made as a part of full ALU.
Floating Point Representation
The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for
floating-point computation which was established in 1985 by the Institute of Electrical and
Electronics Engineers (IEEE). The standard addressed many problems found in the diverse
floating point implementations that made them difficult to use reliably and reduced their
portability. IEEE Standard 754 floating point is the most common representation today for
real numbers on computers, including Intel-based PC’s, Macs, and most Unix platforms.
There are several ways to represent floating point number but IEEE 754 is the most efficient
in most cases. IEEE 754 has 3 basic components:

1. The Sign of Mantissa

This is as simple as the name. 0 represents a positive number while 1 represents a
negative number.
2. The Biased exponent
The exponent field needs to represent both positive and negative exponents. A bias is
added to the actual exponent in order to get the stored exponent.
3. The Normalised Mantissa

The mantissa is part of a number in scientific notation or a floating-point number,

consisting of its significant digits. Here we have only 2 digits, i.e. O and 1. So a
normalised mantissa is one with only one 1 to the left of the decimal.
IEEE 754 numbers are divided into two based on the above three components: single
precision and double precision.
85.125

85 = 1010101

0.125 = 001

85.125 = 1010101.001

=1.010101001 x 2^6

sign = 0

1. Single precision:

biased exponent 127+6=133

133 = 10000101

Normalised mantisa = 010101001

add 0's to complete the 23 bits

The IEEE 754 Single precision is:

= 0 10000101 01010100100000000000000

2. Double precision:

biased exponent 1023+6=1029

1029 = 10000000101

Normalised mantisa = 010101001

add 0's to complete the 52 bits

The IEEE 754 Double precision is:

= 0 10000000101 0101010010000000000000000000000000000000000000000000