14 Introduc on to Embedded Systems

Keywords
Embedded system: An electronic/electro-mechanical system which is designed to perform a specific func on
and is a combina on of both hardware and firmware [LO 1]
Opera ng system: A piece of so ware designed to manage and allocate system resources and execute other
pieces of so ware [LO 2]
RAM: Random Access memory. Vola le memory [LO 3]
Microprocessor: A silicon chip represen ng a Central Processing Unit (CPU) [LO 4]
Microcontroller: A highly integrated chip that contains a CPU, scratchpad RAM, special and general purpose
register arrays and integrated peripherals [LO 4]
SCADA: Supervisory Control and Data Acquisi on System. A data acquisi on system used in industrial control
applica ons [LO 4]
DSP: Digital Signal Processor is a powerful special purpose 8/16/32 bit microprocessor designed specifically to
meet the computa onal demands and power constraints [LO 5]
ASIC: Applica on Specific Integrated Circuit is a microchip designed to perform a specific or unique applica on
[LO 6]
Sensor: A transducer device that converts energy from one form to another for any measurement or control
purpose [LO 6]
Actuator: A form of transducer device (mechanical or electrical) which converts signals to corresponding
physical ac on (mo on) [LO 6]
LED: Light Emi ng Diode. An output device producing visual indica on in the form of light in accordance with
current flow [LO 6]
Buzzer: A piezo-electric device for genera ng audio indica on. It contains a piezo-electric diaphragm which
produces audible sound in response to the voltage applied to it [LO 6]
Electro Cardiogram (ECG): An embedded device for heartbeat monitoring [LO 6]
ADC: Analog to Digital Converter. An integrated circuit which converts analog signals to digital form [LO 6]
Bluetooth: A low cost, low power, short range wireless technology for data and voice communica on [LO 6]
Wi-Fi: Wireless Fidelity is the popular wireless communica on technique for networked communica on of
devices [LO 6]

Objec ve Ques ons

1. Embedded systems are
(a) General purpose (b) Special purpose
2. Embedded system is
(a) An electronic system (b) A pure mechanical system
(c) An electro-mechanical system (d) (a) or (c)
3. Which of the following is not true about embedded systems?
(a) Built around specialised hardware (b) Always contain an operating system
(c) Execution behaviour may be deterministic(d) All of these
(e) None of these
 Introduc on to Embedded Systems 15

4. Which of the following is not an example of a ‘Small-scale Embedded System’?

(a) Electronic Barbie doll (b) Simple calculator
(c) Cell phone (d) Electronic toy car
5. The first recognised modern embedded system is
(a) Apple Computer (b) Apollo Guidance Computer (AGC)
(c) Calculator (d) Radio Navigation System
6. The first mass produced embedded system is
(a) Minuteman-I (b) Minuteman-II
(c) Autonetics D-17 (d) Apollo Guidance Computer (AGC)
7. Which of the following is (are) an intended purpose(s) of embedded systems?
(a) Data collection (b) Data processing (c) Data communication
(d) All of these (e) None of these
8. Which of the following is an (are) example(s) of embedded system for data communication?
(a) USB Mass storage device (b) Network router
(c) Digital camera (d) Music player
(e) All of these (f) None of these
9. A digital multi meter is an example of an embedded system for
(a) Data communication (b) Monitoring
(c) Control (d) All of these
(e) None of these
10. Which of the following is an (are) example(s) of an embedded system for signal processing?
(a) Apple iPOD (media player device) (b) SanDisk USB mass storage device
(c) Both (a) and (b) (d) None of these

Review Ques ons

1. What is an embedded system? Explain the different applications of embedded systems.
[LO 1, LO 2, LO 3]
2. Explain the different classifications of embedded systems. Give an example for each.
[LO 4, LO 5, LO 6, LO7]
3. Explain the various purposes of embedded systems in detail with illustrative examples.
[LO 5, LO 6, LO 7]
 The Typical Embedded System 67

RS-485: The enhanced version of RS-232, which supports mul -drop communica on with up to 32 transmi ng
devices (drivers) and 32 receiving devices on the bus [LO 4]
USB: Universal Serial Bus is a wired high speed serial bus for data communica on [LO 4]
IEEE 1394: A wired, isochronous high speed serial communica on bus [LO 4]
Firewire: The Apple Inc.’s implementa on of the 1394 protocol [LO 4]
Infrared (IrDA): A serial, half duplex, line of sight based wireless technology for data communica on between
devices [LO 4]
Bluetooth: A low cost, low power, short range wireless technology for data and voice communica on [LO 4]
Wi-Fi: Wireless Fidelity is the popular wireless communica on technique for networked communica on of
devices [LO 4]
ZigBee: A low power, low cost, wireless network communica on protocol based on the IEEE 802.15.4-2006
standard. ZigBee is targeted for low power, low data-rate and secure applica ons for Wireless Personal Area
Networking (WPAN) [LO 4]
GPRS: General Packet Radio Service is a communica on technique for transferring data over a mobile
communica on network like GSM [LO 4]
Reset Circuit: A passive circuit or IC device to supply a reset signal to the processor/controller of the embedded
system [LO 6]
Brown-out Protec on Circuit: A passive circuit or IC device to protect the processor from unexpected program
execu on flow due to the drop in power supply voltage [LO 6]
RTC: Real Time Clock is a system component keeping track of me [LO 6]
Watchdog Timer (WDT): Timer for monitoring the firmware execu on [LO 6]
PCB: Printed Circuit Board is the place holder for arranging the different hardware components required to
build the embedded product [LO 4]

Objec ve Ques ons

1. Embedded hardware/software systems are basically designed to
(a) Regulate a physical variable
(b) Change the state of some devices
(c) Measure/Read the state of a variable/device
(d) Any/All of these
2. Little Endian processors
(a) Store the lower-order byte of the data at the lowest address and the higher-order byte of the data at the
highest address of memory
(b) Store the higher-order byte of the data at the lowest address and the lower-order byte of the data at the
highest address of memory
(c) Store both higher order and lower order byte of the data at the same address of memory
(d) None of these
3. An integer variable with value 255 is stored in memory location at 0x8000. The processor word length is 8
bits and the processor is a big endian processor. The size of integer is considered as 4 bytes in the system.
What is the value held by the memory location 0x8000?
(a) 0xFF (b) 0x00 (c) 0x01 (d) None of these
68 Introduc on to Embedded Systems

4. The instruction set of RISC processor is

(a) Simple and lesser in number (b) Complex and lesser in number
(c) Simple and larger in number (d) Complex and larger in number
5. Which of the following is true about CISC processors?
(a) The instruction set is non-orthogonal
(b) The number of general purpose registers is limited
(c) Instructions are like macros in C language
(d) Variable length Instructions
(e) All of these
(f) None of these
6. Which of the following processor architecture supports easier instruction pipelining?
(a) Harvard (b) Von Neumann
(c) Both of them (d) None of these
7. Microprocessors/controllers based on the Harvard architecture will have separate data bus and instruction
bus. This allows the data transfer and program fetching to occur simultaneously on both buses. State True or
False
(a) True (b) False
8. Which of the following is one-time programmable memory?
(a) SRAM (b) PROM (c) FLASH (d) NVRAM
9. Which of the following memory type is best suited for development purpose?
(a) EEPROM (b) FLASH (c) UVEPROM (d) OTP (e) (a) or (b)
10. EEPROM memory is alterable at byte level. State True or False
(a) True (b) False
11. Non-volatile RAM is a Random Access Memory with battery backup. State True or False
(a) True (b) False
12. Execution of program from ROM is faster than the execution from RAM. State True or False
(a) True (b) False
13. Dynamic RAM stores data in the form of voltage. State True or False
(a) True (b) False
14. The control algorithm (Program instructions) and or the configuration settings that are kept in the code
(Program) memory of the embedded system are known as Embedded Software. State True or False
(a) True (b) False
15. Which of the following is an example for Wireless Communication interface?
(a) RS-232C (b) Wi-Fi (c) Bluetooth (d) EEE1394
(e) both (b) and (c)
16. Which of the following is (are) examples for Application Specific Instruction set Processor(s)
(a) Intel Centrino (b) Atmel Automotive AVR
(c) AMD Turion (d) Microchip CAN PIC
(e) All of these (f) both (b) and (d)
17. How many memory cells are present in 1Kb RAM
(a) 1024 (b) 8192 (c) 512 (d) 4096 (e) None of these
18. Which of the following memory supports Execute in Place (XIP)?
(a) EEPROM (b) NOR FLASH (c) NAND FLASH (d) both (b) and (c)
(e) None of these
 The Typical Embedded System 69

19. How many memory cells are present in 1Kb Serial EEPROM
(a) 1024 (b) 8192 (c) 512 (d) 4096 (e) None of these
20. Which of the following is (are) example(s) for the input subsystem of an embedded system dealing with
digital data?
(a) ADC (b) Optocoupler (c) DAC (d) All of them
(e) only (a) and (b)
21. Which of the following is (are) example(s) for the output subsystem of an embedded system dealing with
digital data?
(a) LED (b) Optocoupler (c) Stepper Motor (d) All of these
(e) only (a) and (c)
22. Which of the following is true about optocouplers
(a) Optocoupler acts as an input device only
(b) Optocoupler acts as an output device only
(c) Optocoupler can be used in both input and output circuitry
(d) None of these
23. Which of the following is true about a unipolar stepper motor
(a) Contains only a single winding per stator phase
(b) Contains two windings per stator phase
(c) Contains four windings per stator phase
(d) None of these
24. Which of the following is (are) true about normally open single pole relays?
(a) The circuit remains open when the relay is not energised
(b) The circuit remains closed when the relay is energised
(c) There are two output paths
(d) Both (a) and (b) (e) None of these
25. What is the minimum number I/O line required to interface a 16-Key matrix keyboard?
(a) 16 (b) 8 (c) 4 (d) 9
26. Which is the optimal row-column configuration for a 24 key matrix keyboard?
(a) 6 × 4 (b) 8 × 3 (c) 12 × 2 (d) 5 × 5
27. Which of the following is an example for on-board interface in the embedded system context?
(a) I2C (b) Bluetooth (c) SPI (d) All of them
(e) Only (a) and (c)
28. What is the minimum number of interface lines required for implementing I2C interface?
(a) 1 (b) 2 (c) 3 (d) 4
29. What is the minimum number of interface lines required for implementing SPI interface?
(a) 2 (b) 3 (c) 4 (d) 5
30. Which of the following are synchronous serial interface?
(a) I2C (b) SPI (c) UART (d) All of these
(e) Only (a) and (b)
31. RS-232 is a synchronous serial interface. State True or False
(a) True (b) False
32. What is the maximum number of USB devices that can be connected to a USB host?
(a) Unlimited (b) 128 (c) 127 (d) None of these
33. In the ZigBee network, which of the following ZigBee entity stores the information about the network?
(a) ZigBee Coordinator (b) ZigBee Router
(c) ZigBee Reduced Function Device (d) All of them
70 Introduc on to Embedded Systems

34. What is the theoretical maximum data rate supported by GPRS

(a) 8Mbps (b) 12Mbps (c) 100Kbps (d) 171.2Kbps
35. GPRS communication divides the radio channel into __________ timeslots
(a) 2 (b) 3 (c) 5 (d) 8

Review Ques ons

1. Explain the components of a typical embedded system in detail. [LO 1, LO 7]
2. Which are the components used as the core of an embedded system? Explain the merits, drawbacks, if any,
and the applications/domains where they are commonly used. [LO 1]
3. What is Application Specific Integrated Circuit (ASIC)? Explain the role of ASIC in Embedded System
design? [LO 1]
4. What is the difference between Application Specific Integrated Circuit (ASIC) Application Specific Standard
Product (ASSP)? [LO 1]
5. What is the difference between microprocessor and microcontroller? Explain the role of microprocessors
and controllers in embedded system design? [LO 1]
6. What is Digital Signal Processor (DSP)? Explain the role of DSP in embedded system design? [LO 1]
7. What is the difference between RISC and CISC processors? Give an example for each. [LO 1]
8. What is processor architecture? What are the different processor architectures available for processor/
controller design? Give an example for each. [LO 1]
9. What is the difference between big-endian and little-endian processors? Give an example of each. [LO 1]
10. What is Programmable Logic Device (PLD)? What are the different types of PLDs? Explain the role of
PLDs in Embedded System design. [LO 1]
11. What is the difference between PLD and ASIC? [LO 1]
12. What are the advantages of PLD over fixed logic device? [LO 1]
13. What are the different types of memories used in Embedded System design? Explain the role of each.
[LO 2]
14. What are the different types of memories used for Program storage in Embedded System Design? [LO 2]
15. What is the difference between Masked ROM and OTP? [LO 2]
16. What is the difference between PROM and EPROM? [LO 2]
17. What are the advantages of FLASH over other program storage memory in Embedded System design?
[LO 2]
18. What is the difference between RAM and ROM? [LO 2]
19. What are the different types of RAM used for Embedded System design? [LO 2]
20. What is memory shadowing? What is its advantage? [LO 2]
21. What is Sensor? Explain its role in Embedded System Design? Illustrate with an example. [LO 3]
22. What is Actuator? Explain its role in Embedded System Design? Illustrate with an example. [LO 3]
23. What is Embedded Firmware? What are the different approaches available for Embedded Firmware
development? [LO 5]
 Characteris cs and Quality A ributes of Embedded Systems 81

Objec ve Ques ons

1. Embedded systems are application and domain specific. State True or False
(a) True (b) False
2. Which of the following is true about Embedded Systems?
(a) Reactive and Real Time (b) Distributed (c) Operates in harsh environment
(d) All of these (e) None of these
3. Which of the following is a distributed embedded system?
(a) Cell phone (b) Notebook Computer
(c) SCADA system (d) All of these
(e) None of these
4. Quality attributes of an embedded system are
(a) Functional requirements (b) Non-functional requirements
(c) Both (d) None of these
5. Response is a measure of
(a) Quickness of the system (b) How fast the system tracks changes in Input
(c) Both (d) None of these
6. Throughput of an embedded system is a measure of
(a) The efficiency of the system (b) The output over a stated period of time
(c) Both (d) None of these
7. Benchmark is
(a) A reference point (b) A set of performance criteria
(c) (a) or (b) (d) None of these
8. Mean Time Between Failures (MTBF) and Mean Time To Repair (MTTR) defines the reliability of an
embedded system. State True or False
(a) True (b) False
9. MTBF gives the frequency of failures of an embedded system. State True or False
(a) True (b) False
10. Which of the following is true about the quality attribute ‘maintainability’?
(a) The corrective maintainability requirement for a highly reliable embedded system is very less
(b) Availability of an embedded system is directly related to the maintainability of the system
(c) Both of these
(d) None of these
11. The Mean Time Between Failure (MTBF) for an embedded product is very high. This means:
(a) The product is highly reliable
(b) The availability of the product is very high
(c) The preventive maintenance requirement for the product is very less
(d) All of these
(e) None of these
12. The Mean Time Between Failure (MTBF) of an embedded product is 4 months and the Mean Time To
Repair (MTTR) of the product is 2 weeks. What is the availability of the product?
(a) 100% (b) 50% (c) 89% (d) 10%
13. Which of the following are the three measures of information security in embedded systems?
(a) Confidentiality, secrecy, integrity
(b) Confidentiality, integrity, availability
82 Introduc on to Embedded Systems

(c) Confidentiality, transparency, availability

(d) Integrity, transparency, availability
14. You are working on a mission critical embedded system development project for a client and the client
and your company has signed a Non Disclosure Agreement (NDA) on the disclosure of the project-related
information. You share the details of the project you are working with your friend. Which aspect of
Information security you are violating here?
(a) Integrity (b) Confidentiality (c) Availability (d) None of these
15. Which of the following is an example of ‘gradual’ safety threat from an embedded system?
(a) Product blast due to overheating of the battery
(b) UV emission from the embedded product
(c) Both of these
(d) None of these
16. Non operational quality attributes are
(a) Non-functional requirements (b) Functional requirements
(c) Quality attributes for an offline product (d) (a) and (c)
(e) None of these
17. Which of the following is (are) an operational quality attribute?
(a) Testability (b) Safety (c) Debug-ability (d) Portability
(e) All of these
18. Which of the following is (are) non-operational quality attribute?
(a) Reliability (b) Safety (c) Maintainability (d) Portability
(e) All of these (f) None of these
19. In the Information security context, Confidentiality deals with the protection of data and application from
unauthorised disclosure. State True or False
(a) True (b) False
20. What are the two different aspects of debug-ability in the embedded system development context?
(a) Hardware & Firmware debug-ability (b) Firmware & Software debug-ability
(c) None of these
21. For an embedded system, the quality attribute ‘Evolvability’ refers to
(a) The upgradability of the product (b) The modifiability of the product
(c) Both of these (d) None of these
22. Portability is a measure of ‘system independence’. State True or False
(a) True (b) False
23. For a commercial embedded product the unit cost is high during
(a) Product launching (b) Product maturity
(c) Product growth (d) Product discontinuing
24. For a commercial embedded product the sales volume is high during
(a) Product launching (b) Product maturity
(c) Product growth (d) Product discontinuing

Review Ques ons

1. Explain the different characteristics of embedded systems in detail. [LO 1]
2. Explain quality attribute in the embedded system development context? What are the different Quality
attributes to be considered in an embedded system design. [LO 2]
 Embedded Systems—Applica on- and Domain-Specific 91

Keywords
ECU: Electronic Control Unit. The generic term for the embedded control units in automo ve applica on
[LO 2]
HECU: High-speed Electronic Control Unit. The high-speed embedded control unit deployed in automo ve
applica ons [LO 2]
LECU: Low-speed Electronic Control Unit. The low-speed embedded control unit deployed in automo ve
applica ons [LO 2]
CAN: Controller Area Network. An event driven serial protocol interface used primarily for automo ve
applica ons [LO 2]
LIN: Local Interconnect Network. A single master mul ple slave, low speed serial bus used in automo ve
applica on [LO 2]
MOST: Media Oriented System Transport Bus. A mul media fibre-op c point-to-point network implemented
in a star, ring or daisy-chained topology over op cal fibres cables [LO 2]

Objec ve Ques ons

1. In Automotive systems, High-speed Electronic Control Units (HECUs) are deployed in
(a) Fuel injection systems (b) Antilock brake systems
(c) Power windows (d) Wiper control
(e) Only (a) and (b)
2. In Automotive systems, Low speed electronic control units (LECUs) are deployed in
(a) Electronic throttle (b) Steering controls
(c) Transmission control (d) Mirror control
3. The first embedded system used in automotive application is the microprocessor based fuel injection system
introduced by ______ in 1968
(a) BMW (b) Volkswagen 1600
(c) Benz E Class (d) KIA
4. CAN bus is an event driven protocol for communication. State True or False
(a) True (b) False
5. Which of the following serial bus is (are) used for communication in Automotive Embedded Applications?
(a) Controller Area Network (CAN)
(b) Local Interconnect Network (LIN)
(c) Media Oriented System Transport (MOST) bus
(d) All of these
(e) None of these
6. Which of the following is true about LIN bus?
(a) Single master multiple slave interface (b) Low speed serial bus
(c) Used for sensor/actuator interfacing (d) All of these
(e) None of these
7. Which of the following is true about MOST bus?
(a) Used for automotive audio video system interfacing
(b) It is a fibre optic point-to-point network
92 Introduc on to Embedded Systems

(c) It is implemented in star, ring or daisy-chained topology

(d) All of these
(e) None of these
8. Which of the following is (are) example(s) of Silicon providers for automotive applications?
(a) Maxim/Dallas (b) Analog Devices (c) Xilinx (d) Atmel
(e) All of these (f) None of these

Review Ques ons

1. Explain the role of embedded systems in automotive domain. [LO 1, LO 2]
2. Explain the different electronic control units (ECUs) used in automotive systems. [LO 2]
3. Explain the different communication buses used in automotive application. [LO 2]
4. Give an overview of the different market players of the automotive embedded application domain. [LO 2]
160 Introduc on to Embedded Systems

Program Counter: CPU register which holds the address of the program memory loca on from which the next
instruc on is to be fetched (Its width depends on the processor architecture) [LO 3]
Data Pointer Register (DPTR): 16bit register which holds the address of external data memory address to be
accessed, in 8051 architecture [LO 3]
Special Func on Register: Register holding the status and control informa on and data associated with
the various configura ons, status and data for on-chip peripheral units like Timer, Interrupt Controller, etc.
[LO 3]
Accumulator: CPU register which holds the results of all CPU related arithme c opera ons [LO 3]
B Register: CPU register that acts as an operand in mul ply and division opera ons, in 8051 architecture
[LO 3]
Program Status Word (PSW): 8bit, bit addressable special func on register signalling the status of accumulator
related opera ons and register bank selector for the scratchpad registers R0 to R7, in 8051 architecture
[LO 3]
Stack Pointer (SP): 8bit register holding the current address of stack memory in 8051 architecture [LO 3]
Machine Cycle: The fundamental unit of instruc on execu on. One instruc on execu on may require one or
more machine cycles. Under standard 8051 architecture, one machine cycle corresponds to 12 clock periods
[LO 3]
Source Current: The maximum current a port pin can supply to drive an externally connected device [LO 3]
Sink Current: The maximum current a port pin can absorb through a device which is connected to an external
supply [LO 3]
Interrupt: Signal that ini ates changes in normal program execu on flow [LO 3]
Interrupt Service Rou ne (ISR): Piece of code represen ng the ac ons to be done when an interrupt occurs
[LO 3]
Interrupt Vector: The start address of the program memory where the ISR corresponding to an interrupt is to
be located [LO 3]
Interrupt Latency: The me elapsed between the asser on of the interrupt and the start of the ISR for the
same [LO 3]
Timer: A hardware or so ware unit which generates me delays. Hardware mers generate more precise
me delays [LO 3]
Serial Port: The I/O unit which transmits and receives data in serial format [LO 3]
Mul processor Communica on: A serial communica on implementa on for communica ng between
mul ple processors on the same serial bus. Only one device acts as the master and rest act as slave at any
given point of me [LO 3]
High-Speed Core: A processor core which requires lesser number of clock periods for instruc on fetch, decode
and execu on [LO 3]

Objec ve Ques ons

1. What is the size of internal data memory supported by the standard 8051 architecture
(a) 64 bytes (b) 128 bytes (c) 256 bytes (d) 1024 bytes
(e) No internal data memory
 Designing Embedded Systems with 8bit Microcontrollers—8051 161

2. What is the size of a ‘Special Function Register’ memory supported by the standard 8051 architecture
(a) 64 bytes (b) 128 bytes (c) 256 bytes (d) 1024 bytes
(e) No internal SFR memory
3. What is the size of an internal program memory supported by the standard 8051 architecture
(a) 128 bytes (b) 1024 bytes (c) 2 Kbytes (d) 4 Kbytes
(e) No internal program memory
4. What is the number of general purpose I/O lines supported by the standard 8051 architecture
(a) 8 (b) 16 (c) 32 (d) 64
5. The general purpose I/O lines of a standard 8051 is grouped into
(a) Two 8-bit bi-directional ports (b) Four 8-bit bi-directional ports
(c) Two 16-bit bi-directional ports (d) Four 16-bit bi-directional ports
6. What is the number of timer units supported by a standard 8051 architecture
(a) Two 16-bit timers (b) Three 16-bit timers
(c) Two 8-bit timers (d) One 16-bit timer
7. The UART of the standard 8051 controller is
(a) Half duplex with configurable baudrate (b) Half duplex with fixed baudrate
(c) Full duplex with configurable baudrate (d) Full duplex with fixed baudrate
8. The standard 8051 controller is built around
(a) Harvard Architecture (b) Von Neumann Architecture
(c) None of these
9. Which of the following is True for a 8051 controller?
(a) The program and data memory of 8051 is logically separated
(b) The program and data memory of 8051 physically resides separately.
(c) Separate address spaces are assigned for data memory and program memory
(d) All of these (e) None of these
10. The address bus of 8051 is
(a) 8-bit wide (b) 16-bit wide (c) 32-bit wide (d) 20-bit wide
11. Which of the following is True about external program memory access?
(a) Port 0 acts as the data bus and Port 2 acts as the higher order address bus
(b) Port 2 acts as the data bus and Port 0 acts as the higher order address bus
(c) Port 0 acts as the multiplexed address/data bus and Port 2 acts as the higher order address bus
(d) Port 2 acts as the multiplexed address/data bus and Port 0 acts as the higher order address bus
12. Name the register holding the address of the memory location holding the next instruction to fetch
(a) DPTR (b) PC (c) SP (d) None of these
13. Name the register holding the address of the external data memory to be accessed in 16bit external data
memory operation
(a) DPTR (b) PC (c) SP (d) None of these
14. For standard 8051 architecture, the internal data memory address is
(a) 8bit wide (b) 4bit wide (c) 16bit wide (d) None of these
15. The external data memory is 4 Kbytes in size and it is arranged in paged addressing mode where 1 page
consists of 256 bytes. Port 2 is used as the page selector. How many port bits are required for implementing
the paging?
(a) 1 (b) 2 (c) 3 (d) 4
16. Which of the following conditions should be satisfied to implement the Von-Neumann memory model for
8051?
(a) The data memory and code memory should be stored in a single memory chip (RAM/NVRAM)
162 Introduc on to Embedded Systems

(b) The external access pin should be tied to logic 0

(c) The external access pin should be tied to logic 1
(d) The PSEN\ and RD\ signals of 8051 should be ANDed to generate the output enable (OE\) of the
memory chip
(e) (a) (b) and (d) (f) (a) (c) and (d)
17. What is the number of general purpose registers supported by the standard 8051 architecture
(a) 1 (b) 8 (c) 16 (d) 32
18. What is the number of bit variables supported by 8051 in the internal data memory area?
(a) 8 (b) 16 (c) 32 (d) 64 (e) 128
19. Bit address 07H contains logic 1, what is the value of bit 07H after executing the instruction MOV 20H,
#01H
(a) 0 (b) 1
20. Memory location 81H contains F0H. What will be the value of Accumulator after executing the instruction
MOV A, 81H
(a) 81H (b) 00H (c) F0H (d) Random data
21. The target controller is a standard 8051. Memory location 81H contains F0H. What will be the value of
accumulator after executing the instructions
MOV R0, #81H
MOV A, @R0
(a) 81H (b) 00H (c) F0H (e) Random data
22. Name the register signalling the status of accumulator related operations
(a) A (b) B (c) PSW (d) SP
(e) None of these
23. How many user programmable general purpose bits are available in the status register of 8051?
(a) 0 (b) 1 (c) 2 (d) 3 (e) 4
24. The accumulator content is 02H. What will be the status of the ‘parity bit P’ of the Status Register?
(a) 1 (b) 0
25. The accumulator contains 0FH. The overflow (OV) carry (C) flag and Auxiliary carry flag (AC) are in the
set state. What will be status of these flags after executing the instruction ADD A, #1
(a) OV = 0; C = 0; AC = 0 (b) OV = 0; C = 0; AC = 1
(c) OV = 1; C = 1; AC = 1 (d) OV = 1; C = 1; AC = 0
26. The register bank selector bits RS0, RS1 are 0 and 1. What is the physical address of register R0?
(a) 00H (b) 08H (c) 0FH (d) 10H (e) 18H
27. The machine cycle for a standard 8051 controller consists of
(a) 2T States (b) 4T States (c) 6T States (d) 8T States
28. Which port of 8051 is ‘true-bidirectional’?
(a) Port 0 (b) Port 1 (c) Port 2 (d) Port 3
29. For configuring a port pin as input port, the corresponding port pins bit latch should be at
(a) Logic 0 (b) Logic 1
30. Port 2 latch contains A5H. What will be the value of Port 2 latch after executing the following
instructions?
MOV DPTR, #0F00H
MOV A, #0FFH
MOVX @DPTR, A
(a) 00H (b) 0FH (c) A5H (d) FFH
 Designing Embedded Systems with 8bit Microcontrollers—8051 163

31. The alternate I/O function for the pins of Port 3 will come into action only when the corresponding bit latch
is
(a) 1 (b) 0
32. The interrupts Timer 0 and serial interrupt are enabled individually in the interrupt enable register and high
priority is given to Timer 0 interrupt by setting the Timer 0 priority selector in the interrupt priority register.
It is observed that the serial interrupt is not at all occurring. What could be the reasons for this?
(a) The global interrupt enable bit (EA) is not in the set state
(b) The Serial interrupt always occurs with Timer 0 interrupt
(c) There is no Serial data transmission or reception activity happening in the system
(d) None of these (e) (a) or (b) or (c)
33. Timer 0 and External 0 interrupts are enabled in the system and are given a priority of 1. Incidentally, the
Timer 0 interrupt and External 0 interrupt occurred simultaneously. Which interrupt will be serviced by the
8051 CPU?
(a) Timer 0 (b) External 0
(c) External 0 interrupt is serviced first and after completing it Timer 0 interrupt is serviced
(d) None of them are serviced
34. What is the maximum ISR size allocated for each interrupt in the standard 8051 Architecture
(a) 1 Byte (b) 4 Byte (c) 8 Byte (d) 16 Byte
35. What is the minimum interrupt acknowledgement latency in a single interrupt system for standard 8051
architecture
(a) 1 Machine cycle (b) 2 Machine cycle (c) 3 Machine cycle (d) 8 Machine cycle
36. External 0 interrupt is asserted and latched at S5P2 of the first machine cycle of the instruction MUL AB.
What will be the minimum interrupt acknowledgement latency time?
(a) 6 Machine cycles (b) 5 Machine cycles (c) 3 Machine cycles (d) 2 Machine cycles
37. What is the minimum duration in which the external interrupt line should be asserted to identify it as a valid
interrupt for level triggered configuration?
(a) 1 Machine cycle (b) 3 T States (c) 2 Machine cycles (d) 3 Machine cycles
38. What is the timer increment rate for timer operation for standard 8051 architecture
(a) Oscillator Frequency/6 (b) Oscillator Frequency/12
(c) Same as Oscillator Frequency (d) Oscillator Frequency/24
39. What is the maximum count rate for counting external events for standard 8051 architecture
(a) Oscillator Frequency/6 (b) Oscillator Frequency/12
(c) Same as Oscillator Frequency (d) Oscillator Frequency/24
40. Which is the ‘Timer’ used for baudrate generation for serial communication?
(a) Timer 0 (b) Timer 1
41. The ‘Timer’ used for baudrate generation should run in
(a) Mode 0 (b) Mode 1 (c) Mode 2 (d) Mode 3
42. For ‘Mode 0’ operation, the 13 bit register is formed by
(a) 8 bits of TH0/TH1 and least significant 5 bits of TL0/TL1
(b) 8 bits of TH0/TH1 and most significant 5 bits of TL0/TL1
(c) 8 bits of TL0/TL1 and least significant 5 bits of TH0/TH1
(d) 8 bits of TL0/TL1 and most significant 5 bits of TH0/TH1
43. The serial port of the standard 8051 architecture is
(a) Full duplex (b) Half duplex (c) ‘Receive’ buffered (d) (a) and (c) (e) (b) and (c)
44. Name the ‘Register’ which acts as the ‘Receive’ and ‘Transmit’ buffer in serial communication operation?
(a) SCON (b) PCON (c) SBUF (d) Accumulator
164 Introduc on to Embedded Systems

45. Which of the following is (are) true about ‘Mode 0’ operation of serial communication
(a) The baudrate is variable
(b) The baudrate is given as oscillator frequency/12
(c) The baudrate is same as oscillator frequency
(d) The baudrate is given as oscillator frequency/2
46. The ‘Auto Reload’ count for ‘Timer 1’ is FDH and the operating frequency is 11.0592 MHz and baudrate
doubler bit SMOD is 0. What is the baudrate for communication?
(a) 2400 (b) 4800 (c) 9600 (d) 19200
47. What will be the value of ‘Program Counter (PC)’ after a proper power on reset?
(a) FFFFH (b) 0000H (c) Random value (d) 0001H
48. What will be the value of internal RAM after a reset?
(a) 00H (b) FFH
(c) The value before reset if the system is resetted during operation
(d) Random if the system is resetted immediately after Power ON
(e) (c) or (d)
49. Which of the following is (are) ‘True’ about ‘IDLE’ mode?
(a) The internal clock to the processor is temporarily suspended
(b) The various CPU status like SP, PC, PSW, Accumulator and all other register values are preserved
(c) All port pins will retain their logical state
(d) ALE and PSEN are pulled high
(e) All of these (f) (a), (b) and (c) only
50. A reset signal is applied to the 8051 processor when it is in the ‘Idle’ mode. How will the system behave?
(a) The idle mode setting bit IDL is cleared
(b) The processor resumes program execution from where it left off
(c) The processor resumes program execution from 0000H
(d) (a) and (b) only (e) (a) and (c) only

Review Ques ons

1. Explain the various factors to be considered while selecting a microcontroller for an embedded system
design. [LO 1, LO 2]
2. Explain the architecture of the 8051 microcontroller with a block diagram. [LO 3]
3. Explain the different operating modes of 8051 (Hint: normal operation mode, power saving mode and ONCE
mode) [LO 3]
4. Explain the code memory organisation for 8051 for internal and external program memory access. [LO 3]
5. Explain the data memory organisation for standard 8051 controller. [LO 3]
6. Explain the Von-Neumann memory model implementation for 8051 based system. What are the merits and
demerits of using a Von-Neumann memory model? [LO 3]
7. Explain the memory organisation for lower 128 bytes of internal RAM for standard 8051 architecture.
[LO 3]
8. Explain how Port 0 acts as a normal I/O port and multiplexed address data bus for external data/program
memory access? [LO 3]
 Programming the 8051 Microcontroller 201

Data Exchange Instruc ons: Instruc ons for exchanging data between a memory loca on and the accumulator
register in 8051 architecture [LO 2]
External Data Memory Instruc on: Instruc on for transferring data between external memory and processor
[LO 2]
Arithme c Instruc ons: Instruc ons for performing basic arithme c opera ons including addi on, subtrac on,
mul plica on, division, increment and decrement [LO 2]
2’s Complement: A binary data representa on used in subtrac on opera on [LO 2]
Binary Coded Decimal (BCD): Numbers with base 10. Represented using digits 0 to 9 [LO 2]
Unpacked BCD: A single BCD digit (0 to 9) represented in a single byte [LO 2]
Packed BCD: Two BCD digits (00 to 99) represented using a single byte [LO 2]
Decimal Adjust Accumulator (DAA): An instruc on for adjus ng the accumulator content to give a meaningful
BCD, a er BCD arithme c [LO 2]
Logical Instruc ons: Instruc ons for performing logical opera ons such as ‘ORing’, ‘ANDing’, ‘XORing’,
complemen ng, clearing, bit rota on and swapping nibbles of a byte, etc [LO 2]
Boolean Instruc ons: Instruc ons for performing various opera ons like bit transfer, bit manipula on, logical
opera ons on bits, program control transfer based on bit state, etc [LO 2]

Objec ve Ques ons

1. What are the different addressing modes supported by 8051?
(a) Direct Addressing (b) Indirect Addressing
(c) Register Addressing (d) Indexed Addressing
(e) Immediate Addressing (f) All of these
2. Which is the addressing mode for the instruction MOV A, #50H
(a) Direct (b) Indirect (c) Immediate (d) None of these
3. Which is the addressing mode for the instruction MOV A, 50H
(a) Direct (b) Indirect (c) Immediate (d) None of these
4. Which is the addressing mode for the instruction MOV A, @R0
(a) Direct (b) Indirect (c) Immediate (d) None of these
5. Which is the addressing mode for the instruction MOVC A, @A+DPTR
(a) Direct (b) Indirect (c) Immediate (d) None of these
6. Code memory starting from 0050H holds a lookup table of 10 bytes. The first element of the lookup table is
00H. What is the content of accumulator after executing the following piece of code?
MOV A, #00H
LCALL TABLE
NOP
ORG 004EH
TABLE: MOVC A, @A+PC
RET
(a) 00H (b) 22 (c) 22H (d) Undefined
(e) None of these
202 Introduc on to Embedded Systems

7. Register R0 contains 50H and Accumulator contains 01H. What will be the contents of R0 and A after
executing the instruction MOV A,R0
(a) R0 = 01H; A = 01H (b) R0 = 50H; A = 01H
(c) R0 = 01H; A = 50H (d) R0 = 50H; A = 50H
(e) None of these
8. Data memory location 00H contains F0H and Stack Pointer (SP) contains 07H. What will be the contents of
memory location 00H and SP after executing the instruction PUSH 00H
(a) Data memory location 00H = 07H; SP = 07H
(b) Data memory location 00H = F0H; SP = 07H
(c) Data memory location 00H = F0H; SP = 08H
(d) Data memory location 00H = F0H; SP = 06H
(e) None of these
9. Data memory location 00H contains F0H and Stack Pointer (SP) contains 08H. The memory location 08H
contains 0FH. What will be the contents of memory location 00H, 08H and SP after executing the instruction
POP 00H
(a) Memory location 00H = 0FH; Memory location 08H = F0H; SP = 08H
(b) Memory location 00H = F0H; Memory location 08H = F0H; SP = 07H
(c) Memory location 00H = 0FH; Memory location 08H = 0FH; SP = 07H
(d) Memory location 00H = 0FH; Memory location 08H = 0FH; SP = 09H
(e) None of these
10. Data memory location 0FH contains 00H and the accumulator contains FFH. What will be the contents of
data memory location 0FH and the accumulator after executing the instruction XCH A, 0FH
(a) Memory location 0FH = 00H; Accumulator = FFH
(b) Memory location 0FH = 00H; Accumulator = 00H
(c) Memory location 0FH = FFH; Accumulator = 00H
(d) Memory location 0FH = FFH; Accumulator = FFH
(e) None of these
11. Data memory location 0FH contains A5H, Accumulator contains 5AH and register R0 contains 0FH.
What will be the contents of data memory location 0FH, Register R0 and accumulator after executing the
instruction XCHD A, @R0
(a) Memory location 0FH = A5H; Accumulator = 5AH; R0 = 0FH
(b) Memory location 0FH = 55H; Accumulator = AAH; R0 = 0FH
(c) Memory location 0FH = AAH; Accumulator = 55H; R0 = 0FH
(d) Memory location 0FH = A5H; Accumulator = 55H; R0 = AAH
(e) None of these
12. Register DPTR holds 2050H. Explain the result of executing the instruction MOVX @DPTR, A
(a) P2 SFR = 20H; P1 SFR = 50H during the first machine cycle; RD\ signal is asserted once
(b) P2 SFR = 50H; P1 SFR = 20H during the first machine cycle; RD\ signal is asserted once
(c) P2 SFR = 20H; P1 SFR = 50H during the first machine cycle; WR\ signal is asserted once
(d) P2 SFR = 50H; P1 SFR = 20H during the first machine cycle; WR\ signal is asserted once
(e) None of these
13. The Program Strobe Enable (PSEN) signal is asserted during program fetching if
(a) The program memory is external to the controller
(b) The Program memory is internal to the controller
(c) The Program memory is either internal or external to the controller
14. How many program fetches occur per machine cycle?
(a) 1 (b) 2 (c) 3 (d) 4
 Programming the 8051 Microcontroller 203

15. How many ‘program memory fetches’ are skipped during the execution of MOVX instruction?
(a) 1 (b) 2 (c) 3 (d) 4
16. The Address Latch Enable (ALE) signal is asserted how many times in a machine cycle?
(a) 1 (b) 2 (c) 3 (d) 4
17. How many times the ALE signal is skipped during the execution of a MOVX instruction?
(a) 1 (b) 2 (c) 3 (d) 4
18. Which of the following is true about MOVC instruction
(a) Used for reading from Program memory (b) Uses Indexed Addressing technique
(c) Both a & b (d) None of these
19. The content of Accumulator is FFH and the Carry Flag is in the cleared state. What will be the contents of
Accumulator and carry flag after executing the instruction ADD A,#1
(a) Accumulator = 01H; Carry flag = 1 (b) Accumulator = 01H; Carry flag = 0
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
20. Accumulator register contains 0FH and the Carry flag CY is in the set state. What will be the state of Carry
flag after executing the instruction ADD A,#0F0H
(a) 1 (b) 0 (c) Indeterminate
21. The content of the accumulator is FFH and the Carry flag is in the cleared state. What will be the contents of
the accumulator and carry flag after executing the instruction ADDC A,#1
(a) Accumulator = 01H; Carry flag = 1 (b) Accumulator = 01H; Carry flag = 0
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
22. Accumulator register contains 0FH and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and Accumulator after executing the instruction SUBB A,#0F0H
(a) Accumulator = E1H; Carry flag = 1 (b) Accumulator = E1H; Carry flag = 0
(c) Accumulator = 1FH; Carry flag = 0 (d) Accumulator = 1FH; Carry flag = 1
23. Accumulator register contains F0H and the Carry flag CY is in the cleared state. What will be the contents
of the Carry flag and the accumulator after executing the instruction SUBB A,#0FH
(a) Accumulator = E1H; Carry flag = 1 (b) Accumulator = E1H; Carry flag = 0
(c) Accumulator = 1FH; Carry flag = 0 (d) Accumulator = 1FH; Carry flag = 1
24. Accumulator register contains 0FFH and the B register contains 02H. What will be the contents of the
Accumulator and B register after executing the instruction MUL AB
(a) Accumulator = 0FEH; B = 01H (b) Accumulator = 00H; B = 0FEH
(c) Accumulator = 0FEH; B = 00H (d) Accumulator = 01H; B = 0FEH
25. Accumulator register contains 0FFH, B register contains 02H and the Carry flag is in the cleared state. What
will be the contents of the Carry flag and Overflow flag after executing the instruction MUL AB
(a) Carry flag = 1; Overflow flag = 0
(b) Carry flag = 0; Overflow flag = Remains same as the previous value
(c) Carry flag = 1; Overflow flag = 1
(d) Carry flag = 0; Overflow flag = 1
26. Accumulator register contains 0FFH, B register contains 02H and the Overflow flag is in the cleared state.
What will be the contents of the Carry flag and Overflow flag after executing the instruction MUL AB
(a) Carry flag = remains same as the previous value; Overflow flag = 0
(b) Carry flag = remains same as the previous value; Overflow flag = 1
(c) Carry flag = 1; Overflow flag = 1
(d) Carry flag = 0; Overflow flag = 1
27. Accumulator contains 0FFH and the B Register contains 02H. What will be the contents of the accumulator
and B register after executing the instruction DIV AB
204 Introduc on to Embedded Systems

(a) Accumulator = 01H; B = 7FH (b) Accumulator = 7FH; B = 01H

(c) Accumulator = 7FH; B = 00H (d) Accumulator = 00H; B = 7FH
28. Accumulator register contains 0FFH and the B register contains 0H. What will be the contents of the
accumulator, B register and Overflow flag after executing the instruction DIV AB
(a) Accumulator = 00H; B = 00H; Overflow flag = 1
(b) Accumulator = 0FFH; B = 00H; Overflow flag = 0
(c) Accumulator = Undefined; B = Undefined; Overflow flag = 1
(d) Accumulator = Undefined; B = Undefined; Overflow flag = 0
29. Accumulator register contains 0FFH and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and the accumulator after executing the instruction INC A
(a) Accumulator = 00H; Carry flag = 1 (b) Accumulator = 00H; Carry flag = 0
(c) Accumulator = 01H; Carry flag = 0 (d) Accumulator = 01H; Carry flag = 1
30. Accumulator register contains 00H and the Carry flag CY is in the cleared state. What will be the contents
of Carry flag and Accumulator after executing the instruction DEC A
(a) Accumulator = 00H; Carry flag = 1 (b) Accumulator = 00H; Carry flag = 0
(c) Accumulator = FFH; Carry flag = 0 (d) Accumulator = FFH; Carry flag = 1
31. DPTR contains 2050H. What will be the content of DPTR after executing the following instructions
XCH A, DPL
DEC A
CJNE A, #0FFH, skip_dec
DEC DPH
skip_dec:
XCH A, DPL
(a) 2050H (b) 2049H (c) 2051H (d) 204FH
32. Accumulator register contains 0FH. What will be the content of the accumulator after executing the instruction
DA A
(a) 0FH (b) 15 H (c) 15 (d) 00H
33. Accumulator register contains the BCD number 28. What will be the content of the accumulator after
executing the instruction ADD A,#12H
(a) 40H (b) 3AH (c) 40 (d) None of these
34. Accumulator register contains the BCD number 28. What will be the content of the accumulator after
executing the following instructions
ADD A,#12H
DAA
(a) 40H (b) 3AH (c) 40 (d) None of these
35. Accumulator register contains 0FH. What will be the content of the accumulator after executing the
instruction ORL A, #0F0H
(a) 0FH (b) F0H (c) FFH (d) 00H
36. Accumulator register contains 0FH. What will be the content of the accumulator after executing the
instruction ANL A, #0F0H
(a) 0FH (b) F0H (c) FFH (d) 00H
37. Accumulator register contains 0AAH. What will be the content of the accumulator after executing the
instruction XRL A, #0D5H
(a) AAH (b) 7FH (c) D5H (d) FFH
38. Accumulator register contains 7FH and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction CLR A
 Programming the 8051 Microcontroller 205

(a) Accumulator = 7FH; Carry flag = 0 (b) Accumulator = 7FH; Carry flag = 1
(c) Accumulator = 00H; Carry flag = 0 (d) Accumulator = 00H; Carry flag = 1
39. What changes will happen on executing the instruction CLR 00H
(a) The code memory location 00H becomes 00H
(b) The data memory location 00H becomes 00H
(c) The external data memory location 00H becomes 00H
(d) The LS Bit of the data held by data memory location 20H becomes 0
40. Accumulator register contains 0FH and carry flag is in the set state. What will be the contents of the
Accumulator and carry flag after executing the instruction CPL A
(a) Accumulator = 0FH; Carry flag = 0 (b) Accumulator = 0FH; Carry flag = 1
(c) Accumulator = F0H; Carry flag = 0 (d) Accumulator = F0H; Carry flag = 1
41. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction RL A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 80H; Carry flag = 0 (d) Accumulator = 80H; Carry flag = 1
42. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of Accumulator
and carry flag after executing the instruction RLC A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 03H; Carry flag = 0 (d) Accumulator = 03H; Carry flag = 1
43. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of the
accumulator and carry flag after executing the instruction RR A
(a) Accumulator = 02H; Carry flag = 0 (b) Accumulator = 02H; Carry flag = 1
(c) Accumulator = 80H; Carry flag = 0 (d) Accumulator = 80H; Carry flag = 1
44. Accumulator register contains 01H and carry flag is in the set state. What will be the contents of the
accumulator and carry flag after executing the instruction RRC A
(a) Accumulator = 80H; Carry flag = 0 (b) Accumulator = 80H; Carry flag = 1
(c) Accumulator = 03H; Carry flag = 0 (d) Accumulator = 03H; Carry flag = 1
45. Accumulator register contains 5FH. What will be the content of the accumulator after executing the instruction
SWAP A
(a) 00H (b) F5H (c) 5FH (d) 00H
46. What changes will happen on executing the instruction CPL 00H
(a) The code memory location 00H becomes 00H
(b) The data memory location 00H becomes 00H
(c) The external data memory location 00H becomes 00H
(d) The LS Bit of the data held by data memory location 20H is complemented
47. The carry bit is in the set state and the port status bit P1.0 is in the cleared state. What will be the values of
Carry bit and P1.0 after executing the instruction ANL C, /P1.0
(a) Carry flag = 0; P1.0 = 0 (b) Carry flag = 0; P1.0 = 1
(c) Carry flag = 1; P1.0 = 0 (d) Carry flag = 1; P1.0 = 1
48. The Carry bit is in the cleared state and the Port status bit P1.0 is in the cleared state. What will be the values
of Carry bit and P1.0 after executing the instruction ORL C, /P1.0
(a) Carry flag = 0; P1.0 = 0 (b) Carry flag = 0; P1.0 = 1
(c) Carry Flag = 1; P1.0 = 0 (d) Carry flag = 1; P1.0 = 1
49. Which of the following Jump instruction is the optimal instruction if the offset (relative displacement of
jump location from the current instruction location) of the jump location is greater than 127 and less than
–128 and is within the same 2K block of the current instruction
206 Introduc on to Embedded Systems

(a) AJMP (b) SJMP (c) LJMP (d) All of these

50. The program execution needs to be diverted to a location within the 2K memory block of the current instruction
and the 11 least significant bits of the code memory address to which the jump is intended is 050FH. The
AJMP instruction is used for implementing the jump. What is the machine code for implementing the AJMP
instruction for jumping to the specified location?
(a) 01H, 0FH, 05H (b) 01H, 05H, 0FH (c) A1H, 0FH (d) None of these
51. Which of the following Jump instruction encodes the jump location as absolute memory address
(a) SJMP (b) AJMP (c) LJMP (d) All of these
(e) only (b) and (c)
52. All the conditional branching instructions specify the destination address by
(a) Relative offset method
(b) Absolute address method
(c) Either relative or absolute address method
(d) None of these

Review Ques ons

1. Explain with examples the different addressing modes supported by 8051 CPU. [LO 1]
2. What is the difference between Register Instructions and Register Specific Instructions? Give an example for
each. [LO 2]
3. What is the difference between Immediate addressing and Indexed addressing? State where these addressing
techniques are used. Give an example for each. [LO 1]
4. What is Data transfer instruction? Explain the different data transfer instructions supported by 8051 CPU.
[LO 2]
5. Explain the arithmetic operations/instructions supported by 8051 CPU. [LO 2]
6. Accumulator register contains 01H and Carry flag is in the state. What will be the contents of accumulator
and Carry flag on executing the instruction [LO 1, LO 2]
RR A
RR C A
7. Examine the following piece of code and explain whether the program will work in the expected way. Justify
your statement [LO 1, LO 2]
MOV P1.0, P1.2
8. In the following code snippet, the jump location is intended to a memory address with offset beyond +127.
Suggest a workaround to solve this issue [LO 1, LO 2]
CJNE A,#01H, JUMP_HERE
..............................
...............................
;The relative address of label ‘ JUMP_HERE ‘ is greater than 127 JUMP_HERE: XCH A,B
9. Explain the stack memory related data transfer instructions in detail. [LO 1, LO 2]
10. Explain the data exchange instructions in detail with examples. [LO 1, LO 2]
11. Explain the timing diagram for the MOVX instruction execution when the program memory is internal to the
processor. [LO 1, LO 2]
228 Introduc on to Embedded Systems

Objec ve Ques ons

1. Which of the following programming model is best suited for modelling a data driven embedded system
(a) State Machine (b) Data Flow Graph
(c) Harel Statechart Model (d) None of these
2. Which of the following programming model is best suited for modelling a Digital Signal Processing (DSP)
embedded system
(a) Finite State Machine (b) Data Flow Graph
(c) Object Oriented Model (d) UML
3. Which of the following architecture is best suited for implementing a Digital Signal Processing (DSP)
embedded system
(a) Controller Architecture (b) CISC
(c) Datapath Architecture (d) None of these
4. Which of the following is a multiprocessor architecture?
(a) SIMD (b) MIMD (c) VLIW (d) All
(e) (a) and (b) (f) (b) and (c)
5. Which of the following model is best suited for modelling a reactive embedded system?
(a) Finite State Machine (FSM) (b) DFG
(c) Control DFG (d) Object Oriented Model
6. Which of the following models is best suited for modelling a reactive real time embedded system?
(a) Finite State Machine (b) DFG
(c) Control DFG (d) Hierarchical/Concurrent Finite State Machine Model
7. Which of the following model is best suited for modelling an embedded system demanding multitasking
capabilities with data sharing?
(a) Finite State Machine (b) DFG
(c) Control DFG (d) Communicating Process Model
8. Which of the following is a hardware description language?
(a) C (b) System C (c) VHDL (d) C++ (e) (b) and (c)
9. Which of the following is a structural thing in UML?
(a) Class (b) Interaction (c) State Machine (d) Activity
(e) None of these
10. Which of the following is a behavioural thing in UML?
(a) Class (b) Interface (c) State Machine (d) Component
(e) None of these
11. Which of the following is not a static diagram in UML?
(a) Class Diagram (b) Object Diagram (c) Use case Diagram (d) Component Diagram
(e) None of these
12. Which of the following is not a behavioural diagram in UML?
(a) State Diagram (b) Object Diagram (c) Use case Diagram (d) Sequence Diagram
(e) None of these
13. Which of the following UML diagrams is best suited for Requirements Capturing?
(a) State Diagram (b) Use case Diagram (c) Object Diagram (d) Sequence Diagram
(e) None of these
 Hardware So ware Co-Design and Program Modelling 229

14. Which of the following UML diagram represents object interactions with respect to time?
(a) State Diagram (b) Sequence Diagram (c) Object Diagram (d) Use case Diagram
(e) None of these
15. Which of the following UML interaction diagram(s) emphasises on structural organisation of objects?
(a) Collaboration Diagram (b) Sequence Diagram
(c) State Diagram (d) Use case Diagram
(e) None of these
16. Which of the following is (are) trade-offs in hardware software partitioning?
(a) Processing speed (b) Memory requirement
(c) Cost (d) All of these
(e) None of these

Review Ques ons

1. What is hardware software co-design? Explain the fundamental issues in hardware software co-design.
[LO 1]
2. Explain the difference between SIMD, MIMD and VLIW architecture. [LO 1]
3. What is Computational model? Explain its role in hardware software co-design. [LO 2]
4. Explain the different computational models in embedded system design. [LO 2]
5. What is the difference between Data Flow Graph (DFG) and Control Data Flow Graph (CDFG) model?
Explain their significance in embedded system design. [LO 2]
6. What is State and State Machine? Explain the role of State Machine in embedded system design. [LO 2]
7. What is the difference between Finite State Machine Model (FSM) and Hierarchical/Concurrent Finite State
Machine Model (HCFSM)? [LO 2]
8. What is ‘Statechart’? Explain its role in embedded system design. [LO 2]
9. Explain the ‘Sequential’ Program model with an example. [LO 2]
10. Explain the ‘Concurrent/Communicating’ program model. Explain its role in ‘Real Time’ system design.
[LO 2]
11. Explain the ‘Object-Oriented’ program model for embedded system design. Under which circumstances an
Object- Oriented model is considered as the best suited model for embedded system design? [LO 2]
12. Explain the role of programming languages in system design. [LO 2]
13. What are the building blocks of UML? Explain in detail. [LO 3]
14. Explain the different types of UML diagrams and their significance in each stage of the system development
life cycle. [LO 3]
15. Explain the important hardware software ‘trade-offs’ in hardware software partitioning? [LO 4]
 Embedded Hardware Design and Development 301

Double Sided PCB: PCB with track rou ng and component placement done on both sides of the PCB [LO 8]
Mul layer PCB: PCB with mul ple layers for track rou ng [LO 8]
Piggy-back/plug-in/daughter PCB: PCB designed to plug into some other PCBs [LO 8]
Flexible PCB: PCB with flexible substrate for copper deposi ng for tracks and footprint [LO 8]
Solder Mask: A plas c layer deposited on the copper tracks of the PCB to protect it from corrosion and
abrasion [LO 8]
Silk Screen: The legend for prin ng readable informa on on the PCB [LO 8]
Conformal Coa ng: A protec ve coa ng made up of dilute solu on of silicon rubber or epoxy for protec ng
the PCB from extreme environmental condi ons [LO 8]

Objec ve Ques ons

1. Which of the following analog electronic component is used for clamping of voltage in electronic circuits
(a) Schottky diode (b) Transistor (c) TRIAC (d) Zener diode
2. Which of the following analog electronic component(s) is (are) used for noise signal filtering in electronic
circuits
(a) Capacitor (b) Transistor (c) Inductor (d) All of these
(e) Only (a) and (c)
3. Which of the following is (are) true about Open Collector configuration?
(a) The emitter of the transistor is grounded (b) The emitter of the transistor is open
(c) The collector of the transistor is open (d) The collector of the transistor is grounded
(e) (a) and (c) __
(f) (b) and (d)
__
4. The logic expression Y = AB + AB represents the logic gate
(a) AND (b) NAND (c) OR (d) XOR (e) NOR
5. Which of the following is an example for Buffer IC?
(a) 74LS00 (b) 74LS244 (c) 74LS08 (d) 74LS373
(e) None of these
6. Which of the following digital circuits is used for selecting one input from a set of inputs and connecting it
to an output line
(a) Buffer (b) Latch (c) Multiplexer (d) De-Multiplexer
(e) None of these
7. Combinational circuits contain a memory element. State True or False
(a) True (b) False
8. Half Adder is an example of Sequential circuit. State True or False
(a) True (b) False
9. Which of the following flip-flop is known as Delay Flip-Flop
(a) S-R (b) J-K (c) D (d) T
10. For an S-R flip-flop, the previous output state is 0 and the current input state is S = R = 1, what is the current
output state?
(a) 1 (b) 0 (c) Undefined
11. Which of the following flip-flop is known as Toggle Flip-Flop
(a) S-R (b) J-K (c) D (d) T
302 Introduc on to Embedded Systems

12. For a J-K Flip-Flop, the previous output state is 1 and the current input state is J = K = 0, what is the current
output state?
(a) 1 (b) 0 (c) Undefined
13. For a J-K Flip-Flop, the previous output state is 0 and the current input state is J=K=1, what is the current
output state?
(a) 1 (b) 0 (c) Undefined
14. For a T Flip-Flop, the previous output state is 1 and the current input state is 1, what will be the current
output state on applying a clock pulse?
(a) 1 (b) 0 (c) Undefined
15. The number of logic gates present in an IC is 500. The integration type of the IC is?
(a) MSI (b) SSI (c) LSI (d) VLSI
16. The type of integration for a microprocessor chip is
(a) MSI (b) SSI (c) LSI (d) VLSI
17. The design of an integrated circuit with built-in ADC is an example for
(a) Analog (b) Digital (c) Mixed signal (d) None of these
18. In embedded hardware design context, schematic represents
(a) The physical arrangement of various components present in the hardware product
(b) The different components involved in a hardware product and the interconnection among them
(c) Both of these (d) None of these
19. In embedded hardware design context, Bill of Materials (BoM) represents
(a) The type and value of each components present in the hardware
(b) The quantity of different components present in the hardware
(c) Both of these (d) None of these
20. In embedded hardware design context, ‘Netlist’ is
(a) The soft form representation of the different components of a hardware and the interconnection among
them
(b) The output file generated from schematic design
(c) The input file for the PCB layout design
(d) All of these (e) None of these
21. In embedded hardware design context, ‘Layout’ is
(a) A soft form representation of the PCB
(b) Software ‘Blueprint’ representing the physical placement of components in a hardware
(c) All of these (d) None of these
22. Which of the following are the building blocks of a ‘layout’?
(a) Footprints (b) Routes (c) Layers (d) Vias
(e) All of these (f) (a) and (b)
23. What is ‘Footprint’ in the ‘Layout’ context?
(a) The ‘Top view’ of a component
(b) The three-dimensional representation of a component
(c) Both of these (d) None of these
24. Which of the following package(s) contain pins/pads on only one side of the component?
(a) Zigzag In-line Package (ZIP) (b) Single In-line Package (SIP)
(c) Dual In-line Package (DIP) (d) All of these (e) None of these
25. Which of the following is a Surface Mount Package?
(a) PDIP (b) TSSOP (c) SOIC (d) All of these
(e) only (b) and (c)
 Embedded Hardware Design and Development 303

26. Which of the following package(s) contain(s) pins/pads on the four sides of the component?
(a) VQFP (b) SOICS (c) TSSOP (d) PQFP
(e) (a) and (d)
27. The representation of interconnection among various components of a hardware in ‘Layout’ is known as
(a) Footprint (b) Route/Trace (c) Layer (d) None of these
28. In embedded hardware design context, a ‘via’ is a
(a) conductive drill hole (b) interconnection among two components
(c) Ground line (d) Power line (e) None of these
29. Which is (are) the layers of ‘Layout’ used for printing ‘Assembly Notes’?
(a) AST (b) ASB (c) TOP (d) BOT (e) (a) and (b)
30. What is gerber file in the PCB Design context?
(a) File containing the component PCB layout info, routing info, drill details, etc. in a universally accepted
file exchange protocol format
(b) File containing the component PCB layout info, routing info, drill details, etc. in a proprietary file
exchange protocol format
(c) A collection of art works in a gerber format for each layer of the PCB
(d) (a) and (c) (e) None of these
31. Which of the following is(are) true about a single sided PCB?
(a) Only a single layer is used for routing the connections between components
(b) Components are placed on only one side of the PCB
(c) All of these (d) None of these
32. Which of the following is(are) true about flexible PCB?
(a) Highly flexible compared to normal PCB
(b) Uses flexible substrate for etching
(c) Commonly used for the fabrication of Antennas, membrane keyboards, etc.
(d) All of these (e) None of these
33. Which of the following technique(s) is(are) used for PCB fabrication
(a) Photo Engraving (b) PCB Milling (c) PCB printing (d) All of these
34. Which of the following is(are) subtractive process for PCB fabrication?
(a) Photo Engraving (b) PCB printing (c) PCB Milling (d) All of these
(e) None of these (f) only (a) and (c)
35. Which of the following is(are) true about ‘Solder Mask’?
(a) It is a conductive layer
(b) It is a non-conductive layer
(c) It protects the copper tracks from corrosion
(d) It prevents the ‘wetting’ of solder
(e) (b), (c) and (d)
36. Which of the following is(are) true about ‘Conformal Coating’?
(a) It is a conductive layer (b) It is a non-conductive layer
(c) It is a coating over the PCB to protect PCB
(d) Dilute solution of silicon rubber or epoxy, or plastic is used as the conformal coating material
(e) (b), (c) and (d)
378 Introduc on to Embedded Systems

Objec ve Ques ons

1. Which of the following is a processor understandable language?
(a) Assembly language (b) Machine language (c) High level language
2. Assembly language is the human readable notation of?
(a) Machine language (b) High level language (c) None of these
3. Consider the following piece of assembly code
ORG 0000H
LJMP MAIN

Here ‘ORG’ is a
(a) Pseudo-op (b) Label (c) Opcode (d) Operand
4. Translation of assembly code to machine code is performed by the
(a) Assembler (b) Compiler (c) Linker (d) Locator
5. A cross-compiler converts an embedded ‘C’ program to
(a) The machine code corresponding to the processor of the PC used for application development
(b) The machine code corresponding to a processor which is different from the processor of the PC used for
application development
6. ‘ptr’ is an integer pointer holding the address of an integer variable say x which holds the value 10. Assume
the address of the integer variable x as 0x12ff7c. What will be the output of the below piece of code? Assume
the storage size of integer is 4
ptr+=2;
//Print the address holding by the pointer
printf(“0x%x\n”, ptr);
(a) 0x12ff7c (b) 0x12ff7e (c) 0x12ff84 (d) None
7. ‘ptr’ is a char pointer holding the address of a char variable say x which holds the value 10. Assume the
address of the char variable x as 0x12ff7c. What will be the output of the below piece of code?
//Print the address holding by the pointer
printf(“0x%x\n”, ptr++);
(a) 0x12ff7c (b) 0x12ff7d (c) 0x12ff80 (d) None
8. ‘ptr’ is a char pointer holding the address of a char variable say x which holds the value 10. Assume the
address of the char variable x as 0x12ff7c. What will be the output of the below piece of code?
//Print the address holding by the pointer
printf(“0x%x\n”, ++ptr);
(a) 0x12ff7c (b) 0x12ff7d (c) 0x12ff80 (d) None
9. ‘ptr1’ is a char pointer holding the address of the char variable say x which holds the value 10. ‘ptr2’ is a
char pointer holding the address of the char variable say y which holds the value 20. Assume the address of
char variable x as 0x12ff7c and char variable y as 0x12ff78. What will be the output of the following piece
of code?
//Print the address holding by the pointer
printf(“%x\n”, (ptr1+ptr2));
 Embedded Firmware Design and Development 379

(a) 30 (b) 4 (c) Compile error (cannot add two pointers)

(d) 0x25fef4
10. ‘ptr1’ is a char pointer holding the address of the char variable say x which holds the value 10. Assume the
address of char variable x as 0x12ff7c. What will be the output of the following piece of code?
++*ptr1;
printf(“%x\n”, *ptr1);
(a) 0x0a (b) 0x0b (c) 0x12ff7c (d) 0x12ff7d
11. ‘ptr1’ is a char pointer holding the address of the char variable say x which holds the value 10. Assume the
address of char variable x as 0x12ff7c. What will be the output of the following piece of code?
++*ptr1;
printf(“%x\n”, ptr1);
(a) 0x0a (b) 0x0b (c) 0x12ff7c (d) 0x12ff7d
12. ‘ptr1’ is a char pointer holding the address of the char variable say x which holds the value 10. Assume the
address of char variable x as 0x12ff7c. What will be the output of the following piece of code?
*ptr1++;
printf(“%x\n”, *ptr1);
(a) 0x0b (b) The contents of memory location 0x12ff7d (c) 0x12ff7c
(d) 0x12ff7d
13. ‘ptr1’ is a char pointer holding the address of the char variable say x which holds the value 10. Assume the
address of char variable x as 0x12ff7c. What will be the output of the following piece of code?
*ptr1++;
printf(“%x\n”, ptr1);
(a) 0x0b (b) The contents of memory location 0x12ff7d (c) 0x12ff7c
(d) 0x12ff7d
14. Which of the following is the string termination character?
(a) ‘\n’ (b) ‘\t’ (c) ‘\0’ (d) ‘\a’
15. What is the output of the following piece of code?
char name[6] = {‘H’,’E’,’L’,’L’,’O’,’\0’};
printf(“%d”,strlen(name));
(a) 6 (b) 5 (c) 7 (d) None of the above
16. What is the output of the following piece of code?
char str1[] = “Hello ”
char str2[] = “World!”;
str1+= str2;
printf(“%s\n”,str1);
(a) Hello (b) Hello World! (c) Compile error (d) World!
17. What is the output of the following piece of code?
char str1 [ ] = “Hello world!”;
char str2 [ ] = “Hello World!” ;
int n;
380 Introduc on to Embedded Systems

n= stricmp(str1, str2);
printf(“%d”, n);
(a) 1 (b) 0 (c) –1
18. What is the output of the following piece of code?
char str1[] = “Hello ”
char str2[] = “World!”;
strcpy(str1,str2);
printf(“%s\n”,str1);

(a) Hello (b) Hello World! (c) Compile error (d) World!
19. What is the output of the following piece of code?
char str1[] = “Hello ”
char str2[] = “World!”;
str1 = str2;
printf(“%s\n”,str1);

(a) Hello (b) Hello World! (c) Compile error (d) World!
20. Consider the following structure declaration
typedef struct
{
unsigned char command; // command to pass to device
unsigned char status; //status of command execution
unsigned char BytesToSend; //No. of bytes to send
unsigned char BytesReceived; //No. of bytes received
}Info;

Assuming the size of unsigned char as 1 byte, what will be the memory allocated for the structure?
(a) 1 byte (b) 2 bytes (c) 4 bytes (d) 0 bytes
21. Consider the following structure declaration
typedef struct
{
unsigned char hour; // command to pass to device
unsigned char minute; //status of command execution
unsigned char seconds; //No. of bytes to send
}RTC_Time;

Assuming the size of unsigned char as 1 byte, what will be the output of the following piece of code when
compiled for Keil C51 cross compiler
static volatile RTC_Time xdata *current_time = (void xdata *) 0x7000;
void main()
{
unsigned char test;
test = current_time->minute;
printf(“%d”, test);
}
 Embedded Firmware Design and Development 381

(a) 0x7000 (b) 0x7001 (c) Content of memory location 0x7000

(d) Content of memory location 0x7001
22. Consider the following structure declaration
typedef struct
{
unsigned char hour; // Hour Reg value
unsigned char minute; // Minute value
unsigned char seconds; // Seconds value
}RTC_Time;

Assuming the size of unsigned char as 1 byte, what will be the output of the following piece of code when
compiled for Keil C51 cross compiler
void main(void)
{
unsigned char test;
test = offsetof(RTC_Time, seconds);
printf(“%d”,test);
}
(a) 1 (b) 2 (c) Compile error (d) 0
23. Consider the following union definition
typedef union
{
int intVal;
unsigned char charVal[3];
} union_ichar;

What will be the output of the following piece of code? Assume the storage size of int as 2 and unsigned char
as 1
union_ichar int_char;
void main(void)
{
unsigned char test;
test = sizeof (int_char);
printf(“%d”,test);
}
(a) 0 (b) 2 (c) 3 (d) 5
24. The default initialiser for a union with static storage is the default for
(a) The first member variable
(b) The last member variable
(c) The member variable with the highest storage requirement
25. Which of the following is (are) True about pre-processor directives?
(a) compiler/cross-compiler directives
(b) executable code is generated for pre-processor directives on compilation
(c) No executable code is generated for pre-processor directives on compilation
(d) Start with # symbol (e) (a), (b) and (d) (f) (a), (c) and (d)
382 Introduc on to Embedded Systems

26. The ‘C’ pre-processor directive instruction always ends with a semicolon (;). State ‘True’ or ‘False’
(a) True (b) False
27. Which of the following is the file inclusion pre-processor directive?
(a) #define (b) #include (c) #ifdef (d) None of these
28. Which of the following pre-processor directive is used for indicating the end of a block following #ifdef or
#else?
(a) #define (b) #undef (c) #endif (d) #ifndef
29. Which of the following preprocessor directive is used for coding macros?
(a) #ifdef (b) #define (c) #undef (d) #endif
30. What will be the output of the following piece of code?
#define A 2+8
#define B 2+3
void main(void)
{
unsigned char result ;
result = A/B ;
printf(“%d”, result) ;
}
(a) 0 (b) 2 (c) 9 (d) 8
31. The instruction
const unsigned char* x;

represents:
(a) Pointer to constant data (b) Constant pointer to data
(c) Constant pointer to constant data (d) None of these
32. The instruction
unsigned char* const x;

represents:
(a) Pointer to constant data (b) Constant pointer to data
(c) Constant pointer to constant data (d) None of these
33. The instruction
const unsigned char* const x;

represents:
(a) Pointer to constant data (b) Constant pointer to data
(c) Constant pointer to constant data (d) None of these
34. The instruction
volatile unsigned char* x;

represents:
(a) Volatile pointer to data (b) Pointer to volatile data
(c) Volatile pointer to constant data (d) None of these
 Embedded Firmware Design and Development 383

35. The instruction

volatile const unsigned char* x;

represents:
(a) Volatile pointer to data (b) Pointer to volatile data
(c) Pointer to constant volatile data (d) None of these
36. The constant volatile variable in Embedded application represents a
(a) Write only memory location/register (b) Read only memory location/register
(c) Read/Write memory location/register
37. What will be the output of the following piece of code? Assume the data bus width of the controller on which
the program is executed as 8 bits.
void main(void)
{
unsigned char flag = 0x00;
flag |= (1<<7)
printf(”%d”, flag);
}
(a) 0x00 (b) 0x70 (c) 0x80 (d) 0xFF
38. The variable ‘x’ declared with the following code statement
const int x = 5;

will be stored in which section of the memory allocated to the program?

(a) Constant Data Memory (b) Heap Memory (c) Alterable Data Memory
(d) Stack Memory (e) Register
39. What will be the memory allocated on successful execution of the following memory allocation request?
Assume the size of int as 2 bytes
x = (int *) malloc(100);
(a) 2 Bytes (b) 100 Bytes (c) 200 Bytes (d) 4 Bytes
40. Which of the following memory management routine is used for changing the size of allocated bytes in a
dynamically allocated memory block
(a) malloc() (b) realloc() (c) calloc() (d) free()

Review Ques ons

1. Explain the different ‘embedded firmware design’ approaches in detail. [LO 1]
2. What is the difference between ‘Super loop’ based and ‘OS’ based embedded firmware design? Which one
is the better approach? [LO 1]
3. What is ‘Assembly Language’ Programming? [LO 2]
4. Explain the format of assembly language instruction. [LO 2]
5. What is ‘pseudo-ops’? What is the use of it in Assembly Language Programming? [LO 2]
6. Explain the various steps involved in the assembling of an assembly language program. [LO 2]
 Real-Time Opera ng System (RTOS) based Embedded System Design 489

Racing: The situa on in which mul ple processes compete (race) each other to access and manipulate shared
data concurrently [LO 8]
Deadlock: A situa on where none of the processes are able to make any progress in their execu on. Deadlock
is the condi on in which a process is wai ng for a resource held by another process which is wai ng for a
resource held by the first process [LO 8]
Livelock: A condi on where a process always does something but is unable to make any progress in the
execu on comple on [LO 8]
Starva on: The condi on in which a process does not get the CPU or system resources required to con nue
its execu on for a long me [LO 8]
Dining Philosophers’ Problem: A real-life representa on of the deadlock, starva on, livelock and racing issues
in shared resource access in opera ng system context [LO 8]
Producer-Consumer problem: A common data sharing problem where two processes concurrently access a
shared buffer with fixed size [LO 8]
Readers-Writers problem: A data sharing problem characterised by mul ple processes trying to read and
write shared data concurrently [LO 8]
Priority inversion: The condi on in which a medium priority task gets the CPU for execu on, when a high
priority task needs to wait for a low priority task to release a resource which is shared between the high
priority task and the low priority task [LO 8]
Priority inheritance: A mechanism by which the priority of a low-priority task which is currently holding a
resource requested by a high priority task, is raised to that of the high priority task to avoid priority inversion
[LO 8]
Priority Ceiling: The mechanism in which a priority is associated with a shared resource (The priority of the
highest priority task which uses the shared resource) and the priority of the task is temporarily boosted to
the priority of the shared resource when the resource is being held by the task, for avoiding priority inversion
[LO 8]
Task/Process synchronisa on: The act of synchronising the access of shared resources by mul ple processes
and enforcing proper sequence of opera on among mul ple processes of a mul tasking system [LO 8]
Mutual Exclusion: The act of preven ng the access of a shared resource by a task/process when it is being
held by another task/process [LO 8]
Semaphore: A system resource for implemen ng mutual exclusion in shared resource access or for restric ng
the access to the shared resource [LO 8]
Mutex: The binary semaphore implementa on for exclusive resource access under certain OS kernel [LO 8]
Device driver: A piece of so ware that acts as a bridge between the opera ng system and the hardware
[LO 9]

Objec ve Ques ons

Operating System Basics
1. Which of the following is true about a kernel?
(a) The kernel is the core of the operating system
(b) It is responsible for managing the system resources and the communication among the hardware and
other system services
(c) It acts as the abstraction layer between system resources and user applications.
490 Introduc on to Embedded Systems

(d) It contains a set of system libraries and services

(e) All of these
2. The user application and kernel interface is provided through
(a) System calls (b) Shared memory (c) Services (d) None of these
3. The process management service of the kernel is responsible for
(a) Setting up the memory space for the process
(b) Allocating system resources
(c) Scheduling and managing the execution of the process
(d) Setting up and managing the Process Control Block (PCB), inter-process communication and
synchronisation
(e) All of these
4. The Memory Management Unit (MMU) of the kernel is responsible for
(a) Keeping track of which part of the memory area is currently used by which process
(b) Allocating and de-allocating memory space on a need basis (Dynamic memory allocation)
(c) Handling all virtual memory operations in a kernel with virtual memory support
(d) All of these
5. The memory area which holds the program code corresponding to the core OS applications/services is
known as
(a) User space (b) Kernel space (c) Shared memory (d) All of these
6. Which of the following is true about Privilege separation?
(a) The user applications/processes runs at user space and kernel applications run at kernel space
(b) Each user application/process runs on its own virtual memory space
(c) A process is not allowed to access the memory space of another process directly
(d) All of these
7. Which of the following is true about monolithic kernel?
(a) All kernel services run in the kernel space under a single kernel thread.
(b) The tight internal integration of kernel modules in monolithic kernel architecture allows the effective
utilisation of the low-level features of the underlying system
(c) Error prone. Any error or failure in any one of the kernel modules may lead to the crashing of the entire
kernel
(d) All of these
8. Which of the following is true about microkernel?
(a) The microkernel design incorporates only the essential set of operating system services into the kernel.
The rest of the operating system services are implemented in programs known as ‘servers’ which runs in
user space.
(b) Highly modular and OS neutral
(c) Less Error prone. Any ‘Server’ where error occurs can be restarted without restarting the entire kernel
(d) All of these
Real-Time Operating System (RTOS)
1. Which of the following is true for Real-Time Operating Systems (RTOSes)?
(a) Possess specialised kernel (b) Deterministic in behaviour
(c) Predictable performance (d) All of these
2. Which of the following is (are) example(s) for RTOS?
(a) Windows CE (b) Windows XP (c) Windows 2000 (d) QNX (e) (a) and (d)
3. Interrupts which occur in sync with the currently executing task are known as
(a) Asynchronous interrupts (b) Synchronous interrupts
(c) External interrupts (d) None of these
 Real-Time Opera ng System (RTOS) based Embedded System Design 491

4. Which of the following is an example of a synchronous interrupt?

(a) TRAP (b) External interrupt (c) Divide by zero (d) Timer interrupt
5. Which of the following is true about ‘Timer tick’ for RTOS?
(a) The high resolution hardware timer interrupt is referred as ‘Timer tick’
(b) The ‘Timer tick’ is taken as the timing reference by the kernel
(c) The time parameters for tasks are expressed as the multiples of the ‘Timer tick’
(d) All of these
6. Which of the following is true about hard real-time systems?
(a) Strictly adhere to the timing constraints for a task
(b) Missing any deadline may produce catastrophic results
(c) Most of the hard real-time systems are automatic and may not contain a human in the loop
(d) May not implement virtual memory based memory management
(e) All of these.
7. Which of the following is true about soft real-time systems?
(a) Does not guarantee meeting deadlines, but offer the best effort to meet the deadline are referred
(b) Missing deadlines for tasks are acceptable
(c) Most of the soft real-time systems contain a human in the loop
(d) All of these
Tasks, Process and Threads
1. Which of the following is true about Process in the operating system context?
(a) A ‘Process’ is a program, or part of it, in execution
(b) It can be an instance of a program in execution
(c) A process requires various system resources like CPU for executing the process, memory for storing the
code corresponding to the process and associated variables, I/O devices for information exchange, etc.
(d) A process is sequential in execution
(e) All of these
2. A process has
(a) Stack memory (b) Program memory (c) Working Registers (d) Data memory
(e) All of these
3. The ‘Stack’ memory of a process holds all temporary data such as variables local to the process. State ‘True’
or ‘False’
(a) True (b) False
4. The data memory of a process holds
(a) Local variables (b) Global variables
(c) Program instructions (d) None of these
5. A process has its own memory space, when residing at the main memory. State ‘True’ or ‘False’
(a) True (b) False
6. A process when loaded to the memory is allocated a virtual memory space in the range 0x08000 to 0x08FF8.
What is the content of the Stack pointer of the process when it is created?
(a) 0x07FFF (b) 0x08000 (c) 0x08FF7 (d) 0x08FF8
7. What is the content of the program counter for the above example when the process is loaded for the first
time?
(a) 0x07FFF (b) 0x08000 (c) 0x08FF7 (d) 0x08FF8
8. The state where a process is incepted into the memory and awaiting the processor time for execution, is
known as
(a) Created state (b) Blocked state (c) Ready state (d) Waiting state
492 Introduc on to Embedded Systems

(e) Completed state

9. The CPU allocation for a process may change when it changes its state from _______?
(a) ‘Running’ to ‘Ready’ (b) ‘Ready’ to ‘Running’
(c) ‘Running’ to ‘Blocked’ (d) ‘Running’ to ‘Completed’
(e) All of these
10. Which of the following is true about threads?
(a) A thread is the primitive that can execute code
(b) A thread is a single sequential flow of control within a process
(c) ‘Thread’ is also known as lightweight process
(d) All of these (e) None of these
11. A process can have many threads of execution. State ‘True’ or ‘False’
(a) True (b) False
12. Different threads, which are part of a process, share the same address space. State ‘True’ or ‘False’
(a) True (b) False
13. Multiple threads of the same process share ________?
(a) Data memory (b) Code memory (c) Stack memory (d) All of these
(e) only (a) and (b)
14. Which of the following is true about multithreading?
(a) Better memory utilisation
(b) Better CPU utilisation
(c) Reduced complexity in inter-thread communication
(d) Faster process execution (e) All of these
15. Which of the following is a thread creation and management library?
(a) POSIX (b) Win32
(c) Java Thread Library (d) All of these
16. Which of the following is the POSIX standard library for thread creation and management
(a) Pthreads (b) Threads (c) Jthreads (d) None of these
17. What happens when a thread object’s wait() method is invoked in Java?
(a) Causes the thread object to wait
(b) The thread will remain in the ‘Wait’ state until another thread invokes the notify() or notifyAll() method
of the thread object which is waiting
(c) Both of these
(d) None of these
18. Which of the following is true about user level threads?
(a) Even if a process contains multiple user level threads, the OS treats it as a single thread
(b) The user level threads are executed non-preemptively in relation to each other
(c) User level threads follow co-operative execution model
(d) All of these
19. Which of the following are the valid thread binding models for user level to kernel level thread binding?
(a) One to Many (b) Many to One (c) One to One (d) Many to Many
(e) All of these (f) only (b), (c) and (d)
20. If a thread expires, the stack memory allocated to it is reclaimed by the process to which the thread belongs.
State ‘True’ or ‘False’
(a) True (b) False
 Real-Time Opera ng System (RTOS) based Embedded System Design 493

Multiprocessing and Multitasking

1. Multitasking and multiprocessing refers to the same entity in the operating system context. State ‘True’ or
‘False’
(a) True (b) False
2. Multiprocessor systems contain
(a) Single CPU (b) Multiple CPUs (c) No CPU
3. The ability of the operating system to have multiple programs in memory, which are ready for execution, is
referred as
(a) Multitasking (b) Multiprocessing (c) Multiprogramming
4. In a multiprocessing system
(a) Only a single process can run at a time
(b) Multiple processes can run simultaneously
(c) Multiple processes run in pseudo parallelism
5. In a multitasking system
(a) Only a single process can run at a time
(b) Multiple processes can run simultaneously
(c) Multiple processes run in pseudo parallelism
(d) Only (a) and (c)
6. Multitasking involves
(a) CPU execution switching of processes (b) CPU halting (c) No CPU operation
7. Multitasking involves
(a) Context switching (b) Context saving (c) Context retrieval
(d) All of these (e) None of these
8. What are the different types of multitasking present in operating systems?
(a) Co-operative (b) Preemptive (c) Non-preemptive (d) All of these
9. In Co-operative multitasking, a process/task gets the CPU time when
(a) The currently executing task terminates its execution
(b) The currently executing task enters ‘Wait’ state
(c) The currently executing task relinquishes the CPU before terminating
(d) Never get a chance to execute (e) Either (a) or (c)
10. In Preemptive multitasking
(a) Each process gets an equal chance for execution
(b) The execution of a process is preempted based on the scheduling policy
(c) Both of these (d) None of these
11. In Non-preemptive multitasking, a process/task gets the CPU time when
(a) The currently executing task terminates its execution
(b) The currently executing task enters ‘Wait’ state
(c) The currently executing task relinquishes the CPU before terminating
(d) All of these (e) None of these
12. MSDOS Operating System supports
(a) Single user process with single thread
(b) Single user process with multiple threads
(c) Multiple user process with single thread per process
(d) Multiple user process with multiple threads per process
494 Introduc on to Embedded Systems

Task Scheduling
1. Who determines which task/process is to be executed at a given point of time?
(a) Process manager (b) Context manager
(c) Scheduler (d) None of these
2. Task scheduling is an essential part of multitasking.
(a) True (b) False
3. The process scheduling decision may take place when a process switches its state from
(a) ‘Running’ to ‘Ready’ (b) ‘Running’ to ‘Blocked’
(c) ‘Blocked’ to ‘Ready’ (d) ‘Running’ to ‘Completed’
(e) All of these
(f) Any one among (a) to (d) depending on the type of multitasking supported by OS
4. A process switched its state from ‘Running’ to ‘Ready’ due to scheduling act. What is the type of multitasking
supported by the OS?
(a) Co-operative (b) Preemptive (c) Non-preemptive (d) None of these
5. A process switched its state from ‘Running’ to ‘Wait’ due to scheduling act. What is the type of multitasking
supported by the OS?
(a) Co-operative (b) Preemptive (c) Non-preemptive (d) (b) or (c)
6. Which one of the following criteria plays an important role in the selection of a scheduling algorithm?
(a) CPU utilisation (b) Throughput (c) Turnaround time (d) Waiting time
(e) Response time (f) All of these
7. For a good scheduling algorithm, the CPU utilisation is
(a) High (b) Medium (c) Non-defined
8. Under the process scheduling context, ‘Throughput’ is
(a) The number of processes executed per unit of time
(b) The time taken by a process to complete its execution
(c) None of these
9. Under the process scheduling context, ‘Turnaround Time’ for a process is
(a) The time taken to complete its execution (b) The time spent in the ‘Ready’ queue
(c) The time spent on waiting on I/O (d) None of these
10. Turnaround Time (TAT) for a process includes
(a) The time spent for waiting for the main memory
(b) The time spent in the ready queue
(c) The time spent on completing the I/O operations
(d) The time spent in execution
(e) All of these
11. For a good scheduling algorithm, the Turn Around Time (TAT) for a process should be
(a) Minimum (b) Maximum (c) Average (d) Varying
12. Under the process scheduling context, ‘Waiting time’ for a process is
(a) The time spent in the ‘Ready queue’
(b) The time spent on I/O operation (time spent in wait state)
(c) Sum of (a) and (b) (d) None of these
13. For a good scheduling algorithm, the waiting time for a process should be
(a) Minimum (b) Maximum (c) Average (d) Varying
14. Under the process scheduling context, ‘Response time’ for a process is
(a) The time spent in ‘Ready queue’
(b) The time between the submission of a process and the first response
 Real-Time Opera ng System (RTOS) based Embedded System Design 495

(c) The time spent on I/O operation (time spent in wait state)
(d) None of these
15. For a good scheduling algorithm, the response time for a process should be
(a) Maximum (b) Average (c) Least (d) Varying
16. What are the different queues associated with process scheduling?
(a) Ready Queue (b) Process Queue (c) Job Queue (d) Device Queue
(e) All of the Above (f ) (a), (c) and (d)
17. The ‘Ready Queue’ contains
(a) All the processes present in the system (b) All the processes which are ‘Ready’ for execution
(c) The currently running processes (d) Processes which are waiting for I/O
18. Which among the following scheduling is (are) Non-preemptive scheduling
(a) First In First Out (FIFO/FCFS) (b) Last In First Out (LIFO/LCFS)
(c) Shortest Job First (SJF) (d) All of these
(e) None of these
19. Which of the following is true about FCFS scheduling
(a) Favours CPU bound processes (b) The device utilisation is poor
(c) Both of these (d) None of these
20. The average waiting time for a given set of process is ______ in SJF scheduling compared to FIFO
scheduling
(a) Minimal (b) Maximum (c) Average
21. Which among the following scheduling is (are) preemptive scheduling
(a) Shortest Remaining Time First (SRT) (b) Preemptive Priority based
(c) Round Robin (RR) (d) All of these
(e) None of these
22. The Shortest Job First (SJF) algorithm is a priority based scheduling. State ‘True’ or ‘False’
(a) True (b) False
23. Which among the following is true about preemptive scheduling
(a) A process is moved to the ‘Ready’ state from ‘Running’ state (preempted) without getting an explicit
request from the process
(b) A process is moved to the ‘Ready’ state from ‘Running’ state (preempted) on receiving an explicit
request from the process
(c) A process is moved to the ‘Wait’ state from the ‘Running’ state without getting an explicit request from
the process
(d) None of these
24. Which of the following scheduling technique(s) possess the drawback of ‘Starvation’
(a) Round Robin (b) Priority based preemptive
(c) Shortest Job First (SJF) (d) (b) and (c)
(e) None of these
25. Starvation describes the condition in which
(a) A process is ready to execute and is waiting in the ‘Ready’ queue for a long time and is unable to get the
CPU time due to various reasons
(b) A process is waiting for a shared resource for a long time, and is unable to get it for various reasons.
(c) Both of the above
(d) None of these
26. Which of the scheduling policy offers equal opportunity for execution for all processes?
(a) Priority based scheduling (b) Round Robin (RR) scheduling
496 Introduc on to Embedded Systems

(c) Shortest Job First (SJF) (d) All of these

(e) None of these
27. Round Robin (RR) scheduling commonly uses which one of the following policies for sorting the ‘Ready’
queue?
(a) Priority (b) FCFS (FIFO) (c) LIFO (d) SRT
(e) SJF
28. Which among the following is used for avoiding ‘Starvation’ of processes in priority based scheduling?
(a) Priority Inversion (b) Aging
(c) Priority Ceiling (d) All of these
29. Which of the following is true about ‘Aging’
(a) Changes the priority of a process at run time
(b) Raises the priority of a process temporarily
(c) It is a technique used for avoiding ‘Starvation’ of processes
(d) All of these (e) None of these
30. Which is the most commonly used scheduling policy in Real-Time Operating Systems?
(a) Round Robin (RR) (b) Priority based preemptive
(c) Priority based non-preemptive (d) Shortest Job First (SJF)
31. In the process scheduling context, the IDLE TASK is executed for
(a) To handle system interrupts
(b) To keep the CPU always engaged or to keep the CPU in idle mode depending on the system design
(c) To keep track of the resource usage by a process
(d) All of these
Task Communication and Synchronisation
1. Processes use IPC mechanisms for
(a) Communicating between process (b) Synchronising the access of shared resource
(c) Both of these (d) None of these
2. Which of the following techniques is used by operating systems for inter process communication?
(a) Shared memory (b) Messaging (c) Signalling (d) All of these
3. Under Windows Operating system, the input and output buffer memory for a named pipe is allocated in
(a) Non-paged system memory (b) Paged system memory
(c) Virtual memory (d) None of the above
4. Which among the following techniques is used for sharing data between processes?
(a) Semaphores (b) Shared memory (c) Messages d) (b) and (c)
5. Which among the following is a shared memory technique for IPC?
(a) Pipes (b) Memory mapped Object
(c) Message blocks (d) Events
(e) (a) and (b)
6. Which of the following is best advised for sharing a memory mapped object between processes under
windows kernel?
(a) Passing the handle of the shared memory object
(b) Passing the name of the memory mapped object
(c) None of these
7. Why is message passing relatively fast compared to shared memory based IPC?
(a) Message passing is relatively free from synchronisation overheads
(b) Message passing does not involve any OS intervention
(c) All of these (d) None of these
 Real-Time Opera ng System (RTOS) based Embedded System Design 497

8. In asynchronous messaging, the message posting thread just posts the message to the queue and will not wait
for an acceptance (return) from the thread to which the message is posted. State ‘True’ or ‘False’
(a) True (b) False
9. Which of the following is a blocking message passing call in Windows?
(a) PostMessage (b) PostThreadMessage
(c) SendMessage (d) All of these
(e) None of these
10. Under Windows operating system, the message is passed through _____ for Inter Process Communication
(IPC) between processes?
(a) Message structure (b) Memory mapped object
(c) Semaphore (d) All of these
11. Which of the following is true about ‘Signals’ for Inter Process Communication?
(a) Signals are used for asynchronous notifications
(b) Signals are not queued
(c) Signals do not carry any data
(d) All of these
12. Which of the following is true about Racing or Race condition?
(a) It is the condition in which multiple processes compete (race) each other to access and manipulate shared
data concurrently
(b) In a race condition the final value of the shared data depends on the process which acted on the data
finally
(c) Racing will not occur if the shared data access is atomic
(d) All of these
13. Which of the following is true about deadlock?
(a) Deadlock is the condition in which a process is waiting for a resource held by another process which is
waiting for a resource held by the first process
(b) Is the situation in which none of the competing process will be able to access the resources held by other
processes since they are locked by the respective processes
(c) Is a result of chain of circular wait
(d) All of these
14. What are the conditions favouring deadlock in multitasking?
(a) Mutual Exclusion (b) Hold and Wait
(c) No kernel resource preemption at kernel level
(d) Chain of circular waits (e) All of these
15. Livelock describes the situation where
(a) A process waits on a resource is not blocked on it and it makes frequent attempts to acquire the resource.
But unable to acquire it since it is held by other process
(b) A process waiting in the ‘Ready’ queue is unable to get the CPU time for execution
(c) Both of these (d) None of these
16. Priority inversion is
(a) The condition in which a high priority task needs to wait for a low priority task to release a resource
which is shared between the high priority task and the low priority task
(b) The act of increasing the priority of a process dynamically
(c) The act of decreasing the priority of a process dynamically
(d) All of these
498 Introduc on to Embedded Systems

17. Which of the following is true about Priority inheritance?

(a) A low priority task which currently holds a shared resource requested by a high priority task temporarily
inherits the priority of the high priority task
(b) The priority of the low priority task which is temporarily boosted to high is brought to the original value
when it releases the shared resource
(c) All of these (d) None of these
18. Which of the following is true about Priority Ceiling based Priority inversion handling?
(a) A priority is associated with each shared resource
(b) The priority associated to each resource is the priority of the highest priority task which uses this shared
resource
(c) Whenever a task accesses a shared resource, the scheduler elevates the priority of the task to that of the
ceiling priority of the resource
(d) The priority of the task is brought back to the original level once the task completes the accessing of the
shared resource
(e) All of these
19. Process/Task synchronisation is essential for?
(a) Avoiding conflicts in resource access in multitasking environment
(b) Ensuring proper sequence of operation across processes.
(c) Communicating between processes
(d) All of these (e) None of these
20. Which of the following is true about Critical Section?
(a) It is the code memory area which holds the program instructions (piece of code) for accessing a shared
resource
(b) The access to the critical section should be exclusive
(c) All of these (d) None of these
21. Which of the following is true about mutual exclusion?
(a) Mutual exclusion enforces mutually exclusive access of resources by processes
(b) Mutual exclusion may lead to deadlock
(c) Both of these (d) None of these
22. Which of the following is an example of mutual exclusion enforcing policy?
(a) Busy Waiting (Spin lock) (b) Sleep & Wake up
(c) Both of these (d) None of these
23. Which of the following is true about lock based synchronisation mechanism?
(a) It is CPU intensive
(b) Locks are useful in handling situations where the processes is likely to be blocked for a shorter period of
time on waiting the lock
(c) If the lock is being held for a long time by a process and if it is preempted by the OS, the other threads
waiting for this lock may have to spin a longer time for getting
(d) All of these (e) None of these
24. Which of the following synchronisation techniques follow the ‘Sleep & Wakeup’ mechanism for mutual
exclusion?
(a) Mutex (b) Semaphore (c) Critical Section (d) Spin lock
(e) (a), (b) and (c)
25. Which of the following is true about mutex objects for IPC synchronisation under Windows OS?
(a) Only one process/thread can own the ‘mutex object’ at a time
(b) The state of a mutex object is set to non-signalled when it is not owned by any process/thread, and set to
signalled when it is owned by any process/thread
 Real-Time Opera ng System (RTOS) based Embedded System Design 499

(c) The state of a mutex object is set to signalled when it is not owned by any process/thread, and set to non-
signalled when it is owned by any process/thread
(d) Both (a) & (b) (e) Both (a) & (c)
26. Which of the following is (are) the wait functions provided by windows for synchronisation purpose?
(a) WaitForSingleObject (b) WaitForMultipleObjects
(c) Sleep (d) Both (a) and (b)
27. Which of the following is true about Critical Section object?
(a) It can only be used by the threads of a single process (Intra process)
(b) The ‘Critical Section’ must be initialised before the threads of a process can use it
(c) Accessing Critical Section blocks the execution of the caller thread if the critical section is already in use
by other threads
(d) Threads which are blocked by the Critical Section access call, waiting on a critical section, are added to
a wait queue and are woken when the Critical Section is available to the requested thread
(e) All of these
28. Which of the following is a non-blocking Critical Section accessing call under windows?
(a) EnterCriticalSection (b) TryEnterCriticalSection
(c) Both of these (d) None of these
29. The Critical Section object makes the piece of code residing inside it ____?
(a) Non-reentrant (b) Re-entrant (c) Thread safe (d) Both (a) and (c)
30. Which of the following synchronisation techniques is exclusively used for synchronising the access of shared
resources by the threads of a process (Intra Process Synchronisation) under Windows kernel?
(a) Mutex object (b) Critical Section object
(c) Interlocked functions (d) Both (c) and (d)

Review Ques ons

Operating System Basics
1. What is an Operating System? Where is it used and what are its primary functions? [LO 1]
2. What is kernel? What are the different functions handled by a general purpose kernel? [LO 1]
3. What is kernel space and user space? How is kernel space and user space interfaced? [LO 1]
4. What is monolithic and microkernel? Which one is widely used in real-time operating systems? [LO 1]
5. What is the difference between a General Purpose kernel and a Real-Time kernel? Give an example for both.
[LO 2]
Real-Time Operating System (RTOS)
1. Explain the basic functions of a real-time kernel? [LO 2]
2. What is task control block (TCB)? Explain the structure of TCB. [LO 3]
3. Explain the difference between the memory management of general purpose kernel and real-time kernel.
[LO 2]
4. What is virtual memory? What are the advantages and disadvantages of virtual memory? [LO 2]
5. Explain how ‘accurate time management’ is achieved in real-time kernel [LO 2]
6. What is the difference between ‘Hard’ and ‘Soft’ real-time systems? Give an example for ‘Hard’ and ‘Soft’
Real-Time kernels. [LO 2]
554 Introduc on to Embedded Systems

Objec ve Ques ons

1. Which of the following is true about VxWorks OS
(a) Hard real-time (b) Soft real-time (c) Multitasking (d) (a) and (c)
(e) (b) and (c)
2. A task is waiting for a semaphore for its operation. Under VxWorks task state terminology, the task is said
to be in _______ state
(a) READY (b) RUNNING (c) PEND (d) SUSPEND
(e) None of these
3. Under VxWorks kernel the state of a task which is currently executing is changed to SUSPEND. Which of
the following system call might have occurred?
(a) taskSpawn() (b) taskActivate() (c) taskSuspend() (d) msgQSend()
(e) None of these
4. Under VxWorks kernel the state of a task is SUSPEND. Which of the following statement is true?
(a) It is a new task created with system call taskInit() and not yet activated
(b) It is a new task created with system call taskSpawn() and not yet activated
(c) The task is suspended by the system call taskSuspend()
(d) Execution of the task created some exception
(e) All of the above (f) Only (a), (c) and (d)
(g) Only (b), (c) and (d)
5. Which of the following is not part of a task’s context under standard VxWorks kernel?
(a) Program counter (b) CPU Registers
(c) Memory address space (d) Signal Handlers
(e) None of these
6. Under VxWorks kernel, executing the system call kernelTimeSlice (0) produces the impact
(a) The scheduling becomes pre-emptive priority based with Round Robin for Priority resolution
(b) The scheduling becomes pre-emptive priority based with no priority resolution
(c) The scheduling becomes Round Robin
(d) None of these
7. What is the priority level supported by VxWorks for tasks?
(a) 10 (b) 255 (c) 256 (d) Unlimited
8. Which of the following is(are) true about the system call taskDelete()
(a) Terminates a specified task (b) Frees the task memory occupied by stack
(c) Frees the memory occupied by the task control block
(d) Frees the memory allocated by the task during its execution
(e) All of these (f) Only (a), (b) and (c)
9. Which is the first task executed by VxWorks kernel on a system boot-up?
(a) tNetTask (b) tUsrRoot (c) tRlogind (d) tWdbTask
10. Which of the following is not an IPC mechanism supported by VxWorks
(a) Shared memory (b) Message queue (c) mailslot (d) Sockets
11. While executing a task under VxWorks kernel, an address error exception occurred. Which of the following
actions are performed by the default exception handler service?
(a) The task caused the error is suspended
(b) The state of the task at the point of exception is saved (c) Initiates a system reset
(d) All of these (e) Only (a) and (b)
 An Introduc on to Embedded System Design with VxWorks and MicroC/OS-II RTOS 555

12. Which of the following is not a mechanism supported by VxWorks for Inter Task Synchronisation?
(a) Binary semaphore (b) Test and set (c) Counting semaphore
(d) Mutual exclusion semaphore
13. Which of the following is true about the scheduler locking based synchronisation under VxWorks kernel?
(a) May lead to unacceptable real-time response
(b) May increase interrupt latency
(c) Both of these
(d) None of these
14. The mutual exclusion semaphore under VxWorks kernel is a type of
(a) Counting semaphore (b) Binary semaphore
15. The mutual exclusion semaphore prevents priority inversion by
(a) Priority ceiling (b) Priority inheritance
16. Which of the following is true about Interrupt Service Routine under VxWorks kernel
(a) It runs in a separate context
(b) It runs on the same context as that of the interrupted task
(c) It depends on the processor architecture in which the VxWorks kernel is running
(d) None of these
17. Which of the following is true about the stack implementation for ISR under VxWorks?
(a) All ISRs share a common stack
(b) The ISR uses the stack of the interrupted task
(c) It depends on the processor architecture in which the kernel is running
(d) None of these
18. What is the priority levels supported by MicroC/OS-II kernel
(a) 64 (b) 56 (c) 256 (d) Unlimited
19. Which of the following is true about task scheduling under MicroC/OS-II kernel
(a) Priority based pre-emptive scheduling
(b) Priority based non-preemptive scheduling
(c) Round Robin
(d) Pre-emptive priority based with Round Robin for priority resolution
20. Which of the following is not true about tasks under MicroC/OS-II kernel
(a) Supports multiple tasks with same priority
(b) ISRs are allowed to create tasks
(c) The stack can be specified as either upward growing or downward growing
(d) All of these (e) Only (a) and (b) (f) Only (a) and (c) (g) Only (b) and (c)
21. Under MicroC/OS-II kernel changes its state from ‘RUNNING’ to ‘WAITING’, which of the following
conditions might have invoked this?
(a) The task attempted to acquire a shared resource which is currently in use by another task
(b) The task involves some I/O operation and is waiting for I/O
(c) The task undergoes sleeping
(d) The task is suspended by itself or by another task
(e) Any one of these (f) None of these
22. Which is the MicroC function responsible for initialising the different OS kernel data structure
(a) OSInit() (b) OSStart() (c) OSIdle() (d) None of these
23. Which of the following is not an IPC mechanism under MicroC/OS-II kernel
(a) Message queue (b) Mailbox (c) Pipes (d) None of these
556 Introduc on to Embedded Systems

24. Which is the function call used by an ISR to indicate the occurrence of an interrupt to the MicroC/OS-II
kernel
(a) Interrupt (b) OSIntEnter (c) OSIntExit (d) OSIntNesting
25. Under the MicroC/OS-II kernel, the ISR for normal processor architecture makes use of which stack?
(a) Stack of the Interrupted Task
(b) Separate stack
(c) A mix of a separate stack and stack of interrupted task
(d) ISR doesn’t use any stack

Review Ques ons

1. Explain ‘task’ in ‘VxWorks’ context? Explain the different possible states of a task under VxWorks kernel.
[LO 1]
2. Explain the state transition under VxWorks kernel with a state transition diagram. Give an example for the
scenarios for each state transitions. [LO 1]
3. Explain the task creation and management under VxWorks kernel. [LO 1]
4. Explain the difference between taskInit() and taskSpawn() system calls for task creation under VxWorks
kernel. [LO 1]
5. Explain the task scheduling supported by VxWorks kernel. [LO 1]
6. Explain the priority based pre-emptive scheduling with Round Robin scheduling for priority resolution
under VxWorks, with execution diagram for the following: [LO 1]
(a) There are 3 tasks T1, T2 and T3 with priority 15 READY to run and the execution time for the tasks are
20, 15 and 20 Timer Tick respectively
(b) The Time slice for Round Robin scheduling is 5 timer ticks
(c) The scheduler selects the tasks in the order T1,T3,T2 for Round Robin execution
(d) After 7 timer ticks, task 4 with priority 14 and execution completion time 10 becomes ‘READY’
7. Explain the exception handling mechanisms for tasks and interrupts under VxWorks kernel. [LO 1]
8. Explain how a task can be made safe from unwanted deletion under VxWorks kernel, when it is holding a
system resource. [LO 1]
9. Explain the kernel services of VxWorks. [LO 1]
10. Explain the different types of Inter Process Communication Mechanisms supported by VxWorks. [LO 1]
11. Explain the implementation of a two-way message queue between two tasks under VxWorks kernel, with a
block diagram. [LO 1]
12. Explain the different mutual exclusion mechanisms supported by VxWorks. State the relative merits and
limitations of each. [LO 1]
13. What is semaphore? Explain the different types of semaphores supported by VxWorks. [LO 1]
14. Explain how a mutual exclusion semaphore prevents priority inversion in task execution under VxWorks
kernel. [LO 1]
15. Explain the different system calls for wind message queue creation and management under VxWorks kernel.
[LO 1]
16. Explain the different system calls for POSIX standard message queue creation and management under
VxWorks kernel. [LO 1]
 The Embedded System Development Environment 621

In Circuit Emulator (ICE): A hardware device for emula ng the target CPU for debug purpose [LO 4]
Debug Board Module (DBM): ICE device which contains the emula on control logic and emula on chip in a
single hardware unit and is designed for a par cular family of device [LO 4]
Background Debug Mode (BDM): A proprietary serial interface from Motorola for On Chip Debugging
[LO 4]
JTAG: A serial interface for target board diagnos cs and debugging [LO 4]
Boundary Scan: A target hardware debug method for checking the interconnec ons among the various chips
of a complex board [LO 6]
Boundary Scan Descrip on Language (BSDL): A language similar to VHDL, which describes the boundary scan
implementa on of a JTAG supported device [LO 6]

Objec ve Ques ons

1. Which of the following intermediate file, generated during cross-compilation of an Embedded C file holds
the assembly code generated corresponding to the c source code.
(a) List File (b) Preprocessor output file (c) Object file (d) Map file
2. Which of the following detail(s) is(are) kept in an object file generated during the process of cross-compiling
an Embedded C file.
(a) Variable and function names (b) Variable and function reference
(c) Reserved memory for global variables (d) All of these
(e) None of these
3. Which of the following intermediate file, generated during the cross-compilation of an Embedded C files
holds the information about the link/locate process for the multiple object modules of the project?
(a) List file (b) Preprocessor output file (c) Object file (d) Map file
4. Which of the following file generated during the cross-compilation process of an Embedded C project holds
the machine code corresponding to the target processor?
(a) List file (b) Preprocessor output file (c) Object file (d) Map file
5. Examine the following Intel HEX Record
:03000000020C1FD0
This record is ?
(a) a Data Record (b) an End of File Record (c) a Segment Address Record
(d) an Extended Linear Address record
6. Examine the following Intel HEX record
:03000000020C1FD0
What is the number of data bytes in this record?
(a) 0 (b) 3 (c) 2 (d) 20
7. Examine the following Intel HEX record
:03000000020C1FD0
What is the start address of the data bytes in this record?
(a) 0x0000 (b) 0x3000 (c) 0x1FD0 (d) 0x20C1
8. Examine the following Intel HEX Record
:03000000020C1FD0
622 Introduc on to Embedded Systems

Which all are the data bytes present in this record?

(a) 03, 00, 00 (b) 02, 0C, 1F (c) 0C, 1F, D0 (d) 00, 00, 20
9. The program that converts machine codes into target processor specific Assembly code is known as
(a) Disassembler (b) Assembler (c) Cross-compiler (d) Decompiler
10. Which of the following is true about a simulator used in embedded software debugging?
(a) It is a software tool
(b) It requires target hardware for simulation
(c) It doesn’t require target hardware for simulation
(d) (a ) and (b) (e) (a) and (c)
11. Which of the following is an example for on chip firmware debugging?
(a) OnCE (b) BDM (c) All of these

Review Ques ons

1. Explain the various elements of an embedded system development environment. [LO 1]
2. Explain the role of Integrated Development Environment (IDE) for Embedded Software Development.
[LO 1, LO 2]
3. What are the different files generated during the cross-compilation of an Embedded C file? Explain them in
detail. [LO 1, LO 2]
4. Explain the various details held by a List file generated during the process of cross-compiling an Embedded
C project. [LO 1, LO 2]
5. Explain the various details held by a Map file generated during the process of cross-compiling an Embedded
C project. [LO 1, LO 2]
6. Explain the various details stored in an Object file generated during the cross-compilation of an Embedded
C file. [LO 1, LO 2]
7. Explain the difference between Intel Hex and Motorola Hex file format. [LO 1, LO 2]
8. Explain the format of Hex records in an Intel Hex File. [LO 1, LO 2]
9. Explain the format of Hex records in a Motorola Hex File. [LO 1, LO 2]
10. What is the difference between an assembler and a disassembler? State their use in Embedded Application
development. [LO 2, LO 3]
11. What is a decompiler? [LO 3]
12. What is the difference between a simulator and an emulator? [LO 4]
13. Explain the advantages and limitations of simulator based debugging. [LO 4]
14. What are the different techniques available for embedded firmware debugging? Explain them in detail.
[LO 5]
15. What is a Monitor program? Explain its role in embedded firmware debugging? [LO 5]
16. What is ROM emulation? Explain In Circuit Emulator (ICE) based debugging in detail. [LO 5]
17. Explain On Chip Debugging (OCD). [LO 5]
18. Explain the different tools used for hardware debugging. [LO 5]
19. Explain the Boundary Scan based hardware debugging in detail. [LO 6]
 The Embedded Product Development Life Cycle (EDLC) 653

Tes ng Phase: Phase which deals with the execu on of various tests like Integra on tes ng, System tes ng,
User acceptance tes ng. etc. [LO 4]
Unit Tes ng: Tests carried out to verify the func oning of the individual modules of the firmware and hardware
[LO 4]
Upgrade Phase: Product Life Cycle stage which deals with the development of upgrades (new versions) for
the product which is already present in the market [LO 4]
User Acceptance Tes ng (UAT): Tests performed by the user (customer) against the acceptance values for
each requirement [LO 4]
Itera ve or Fountain Model: EDLC Model which follows the sequence—Do some analysis, follow some design,
then some implementa on [LO 5]
Linear or Waterfall Model: EDLC Model which executes all phases of the EDLC in sequence, one a er another
[LO 5]
Prototyping Model: EDLC Model which is the varia on of the itera ve model in which a more refined prototype
is produced at the end of each itera on [LO 5]
Spiral Model: EDLC model combining linear and prototyping model to give the best possible risk minimisa on
in product development [LO 5]

Objec ve Ques ons

1. Which of the following is not in the scope of EDLC
(a) Maximise Return on Investment (RoI)
(b) Minimise the risks involved in the product development
(c) Advertise the product
(d) Defect prevention in Product development
2. The term ‘model’ in EDLC represents
(a) The various phases in the life cycle of the product
(b) The various analysis of the product
(c) The various designs of the product
(d) The various architecture of the product
3. Which of the following is(are) a driving factor(s) for ‘Product Re-engineering’?
(a) Change in business requirement (b) User interface enhancements
(c) Technology upgrades (d) All of these
(e) (a) and (b) (f) (a) and (c)
4. An embedded product requires interfacing with another subsystem of an enterprise for data logging and
information exchange. The interface for this is defined during?
(a) Conceptualisation phase (b) Requirement analysis phase
(c) Design phase (d) Development phase
(e) Deployment phase
5. An embedded product requires a TCP/IP interface and it is decided that the TCP/IP interface can be
implemented using Commercial of the Shelf (COTS) component. The COTS module for the TCP/IP Module
is finalised and selected during?
(a) Conceptualisation phase (b) Requirement analysis phase
(c) Design phase (d) Development phase
(e) Deployment phase
654 Introduc on to Embedded Systems

6. An embedded product contains LCD interfacing and a developer is assigned to work on this module. The
developer coded the module and tested its functioning using a simulator. The test performed by the developer
falls under?
(a) Integration Testing (b) Unit Testing
(c) System Testing (d) Acceptance Testing
7. For an Embedded product, the requirements are well defined and are within the scope and no change requests
are expected till the completion of the life cycle. Which is the best-suited life cycle model for developing this
product?
(a) Linear (b) Iterative (c) Prototyping (d) Spiral
8. Which of the following is(are) not a feature of prototyping model
(a) Requirements refinement (b) Documentation intensive
(c) Intensive Project Management (d) Controlled risk
9. An embedded product under consideration is very complex in nature and there is a possibility for change
in requirements of the product. Also the risk associated with the development of this product is very high.
Which is the best-suited life cycle method to handle this product development?
(a) Linear (b) Iterative (c) Prototyping (d) Spiral

Review Ques ons

1. What is EDLC? Why EDLC is essential in embedded product development? [LO 1]
2. What are the objectives of EDLC? [LO 1, LO 2]
3. Explain the significance of Productivity in embedded product development. Explain the techniques for
productivity improvements. [LO 3]
4. Explain the different phases of Embedded Product Development Life Cycle (EDLC). [LO 4]
5. Explain the term ‘model’ in relation to EDLC. [LO 5]
6. Explain the different types of Product Development needs. [LO 4]
7. Explain the Product Re-engineering need in detail. [LO 4]
8. Explain the various activities performed during the Conceptualisation phase of an Embedded product
development. [LO 4]
9. Explain the various activities performed during the Requirement Analysis phase of an embedded product
development. [LO 4]
10. Explain the various activities performed during the Design phase of an embedded product development.
[LO 4]
11. Explain the various activities performed during the Development phase of an embedded product development.
[LO 4]
12. Explain the various types of tests performed in the development of an embedded product. [LO 4]
13. Explain the various activities performed during the Deployment phase of an embedded product. [LO 4]
14. Explain the various activities performed during the Support phase of an embedded product. [LO 4]
15. Explain the need for Product upgrades in the Embedded Product development. Explain the different types
of product upgrades. [LO 4]
16. Explain the various factors leading to the Retirement/Disposal of an embedded product. [LO 4]
734 Index

Register Transfer Level 250 SPI 47, 563

Relational Operations 327 Spin Lock 463
Relay 40 Spiral Model 650
Remote Method Invocation 445 SRT 419
Remote Procedure Call 445 Stack 397
Requirements Analysis 638 Starvation 416, 454
Reset Circuit 61 State Machine Model 213
Response Time 410 static 325, 326, 341, 372
RET 125 Static Memory 372
Retirement 646 Static RAM 30
return 322 Stepper Motor 38
RISC 7, 22, 210, 659 Bipolar 38
RMI 445 Half Step 39
ROM 29 Unipolar 38
Room Temperature Vulcanised 627 Wave Stepping 39
Round Robin Scheduling 421 Stereolithography 626
Routes 276 Storage Class 326
RPC 445 strcat 337
RS-232 51, 146 strcmp 338
RS-422 53 strcpy 338
RS-485 51 stricmp 338
RSoC 7, 659 String 338
RTC 62 strlen 338
RTL 250 struct 325, 346
RTOS 392 structure 346
Structure padding 351
scanf 337 Super Loop 309
Schematic Design 255 switch 325
Schmitt Trigger 131 switch case 329
Selective Laser Sintering 626 System C 211
Semaphore 469 System on Chip 657
Sensors 10, 16, 35 System Testing 640
Sequential Circuits 243
Sequential Programming Model 216 Task 393
Serial Peripheral Interface Bus 47 Task Communication 449
Shared Memory 433 Task Synchronisation 449, 462
Sharks Cove 665 TCON 128
Sheet Metal 627 Test and Set Lock 464
short 326 Testing Bits 365
Shortest Job First Scheduling 414 Integrated Development Environment 570
Shortest Remaining Time 419 Thread 399
Signalling 444 Binding 407
Silk Screen 296 Many-to-One 407
SIMD 210 One-to-One 407
Simulator 578, 607 Thread Pre-emption 407
Single Instruction Multiple Data 210 Threads 399
sizeof 325 Thread Standard 400
SJF 414 Throughput 410
Sleep 360 Time Management 395
Sleep & Wakeup 468 Timer 134
Small-Scale Integration 249 Timer tick 395
SoC 657 Time to Market 78, 209
Sockets 445 Time to Prototype 78
Soft Real-Time 396 Toggling Bits 363
Solder Mask 296 Tooling 626
 Index 735

Tri-State 236 volatile 325, 359

Truth Table 237 volatile pointer 360
TSL 464 Von-Neumann 100
TTL Logic 108 VxWorks 473, 508
Turnaround Time 410 Binary Semaphore 518
typedef 325, 343, 351 Counting Semaphore 518
Interrupt Handling 520
UART 48 Interrupt Locking 522
ULN2803 117 Inter Task Communication 512
UML 215, 220 Kernel Service 512
Activity diagram 223 Message Queue 515
Collaboration 220 Mutual Exclusion 517
Sequence diagram 223 Mutual exclusion Semaphore 518
State Chart diagram 223 Pipes 434
Use Case diagram 223 Signals 516
Unified Modelling Language 220 Task Creation 524
union 346 Task Locking 517
Unit Testing 640, 643 Task Scheduling 531
Universal Asynchronous Receiver Transmitter 48 Task Synchronisation 538
Universal Serial Bus 53
unsigned 322 Waiting Time 410
Upgrades 635 Watchdog Timer 63
USB 53 Waterfall Model 646
User Acceptance Testing 640 while 326, 330
User Level Thread 407 while continue 330
User Space 391 Wi-Fi 57
Win32 Thread 402
Verilog 211 wind 511
Very Large-Scale Integration 249
Very Long Instruction Word 211 XIP 34
VHDL 211, 250
Via 273 ZigBee 58
Virtual Memory 394 ZigBee Coordinator 58
VLIW 210 ZigBee End Device 58
VLSI 249 ZigBee Router 58
void 325