DIGITAL CIRCUITS AND

SYSTEMS

Electronic & Communication Engineering

Danang University of Technology
 Binary switch
Logic circuits perform operations on digital signals, usually
implemented as electronic circuits where the signal values
are restricted to a few discrete values
S
x = 0 x = 1
x
(a) Two states of a switch (b) Symbol for a switch

S
Battery x Light

Application: A light controlled by a switch.

Input that changes the circuit behavior is the switch control x

Output is state of the light (L=1 if light ON)
Simple logic expression: L(x) = x
 Consider the use of 2 switches to control the light state
(a) Series connection
S S
Power
supply x1 x2 Light L(x1, x2) = x1 . x2

The “.” symbol is called AND operator. The circuit implements a

logical AND function

S (b) Parallel connection

x1

Power L(x1, x2) = x1 + x2

supply S Light

x2
The “ + ” symbol is called OR operator. The circuit implements a
logical OR function
- The output L(x1, x2) is a logic function with input variables
- The AND & OR functions are two important logical functions, can
be used together with other simple functions as building blocks for
the implementation of all logic circuits

X1
S
Power
supply S X3 Light

X2

L(x1, x2, x3)= (x1 + x2) . x3

 Truth Tables

The same operations can also be defined in the form of

what called Truth Table
Three-input AND and OR operations.
 Inversion
R

Power
supply x S Light

An inverting circuit.

L( x) = x = x' =! x =~ x
 x1
x2
x1
x1 ×x2
x2 x1 ×x2 ×… ×xn

xn
(a) AND gates x x

x1
(c) NOT gate
x2
x1
x2
x1 + x2 x1 + x2 + … + xn

xn
(b) OR gates

A logic gate has one or more inputs and one output that is a
function of its inputs.

The graphical symbols for the AND, OR, NOT gates are shown

How logic gates are built will be studied later on

 Logic Gates & Networks

x
1
x
2
f = ( x + x ) ×x
x 1 2 3
3

- A larger circuit is implemented by a network of gates

- The complexity of a given network has direct impact on its costs
- It is desirable to reduce the cost of any manufactured product
- A logic function can be implemented with a different networks
- Search for the solution with minimum cost
 Analysis and Synthesis
- Analysis process: Determine the function performed by a network
- Synthesis process: Design a new network that implements a
desired functional behavior
x x f (x , x ) A B
x1 0 → 0 →1 → 1 1 →1 →0 →0
1 2 1 2

0 0 1 1 0
A
1 →1 → 0 → 1 f 0 1 1 1 0
0 →0 →0→1 B 1 0 0 0 0
0 → 1 →0 → 1 1 1 1
x2 0 1

(a) f = x1 + x1.x2 (b) Truth table

- To determine functional behavior, need to consider all possible

inputs signals and their corresponding output states
- Truth table is a useful tool to demonstrate this.
- It is important to look for the changes in the signals at various
points in the network: known as timing diagram
- The changes in the A, B, f waveforms take place instantaneously
when the input signals: idealized waveforms are based on the
assumption of zero time respond of the logic gates
- Practical logic gates has a delay between a change in input &
corresponding change in the output (chapter 3,4)
- CAD tools generate such timing to show designer how a circuit
behaves before it is actually implemented electronically
x 1
1 0

x 1
2 0

1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram
 Functionally Equivalent Networks
x1 0 → 0 →1 → 1 1 →1 →0 →0
A
1 →1 → 0 → 1 f
0 →0 →0→1 B
0 → 1 →0 → 1
x2

(a) f = x1 + x1.x2

0→0→1→1 1→1→0→0
x
1
1 →1 → 0→ 1
0→1→0→1 g
x
2

(b) g = x1 + x2
- How to derive this simpler logic circuit with equivalent function ?
Boolean algebra put forth by George Boole 1854 Boolean Algebra
An Investigation into the Laws of Thought
Boolean algebra will be our algebra
In Boolean algebra will work with
Two valued variables – our set
Can easily extend to multiple valued logics
Binary relations – our relations
AND - •
OR - +

Now we need some axioms

We’ll work with the following axioms or postulates
Postulates presented by Huntington 1904
Formally
Let A be a set of elements
We define an algebraic system {A, •, +, 0, 1}
• and + are the operations of AND and OR
0 and 1 are distinguished elements of A
and an equivalence relation = on A such that
 Postulates
I. For elements a, b, and c in A the equivalence relation is
•Reflexive
a = a for all a in A
•Symmetric
if a = b then b = a for all a, b in A
•Transitive
if a = b and b = c then a = c for all a, b, and c in A
•Substitutive
if a = b then substituting a for b in any expression will result in
equivalent relation

II. Let operators • and + be defined such that if a and b are elements of A
Called the closure property
a • b is in A
a + b is in A
III. There exists elements 0 and 1 in A such that
a •1 = a
a+0=a
IV. The operators • and + are commutative for all a and b in A
a•b=b•a
a+b=b+a

V. The operators • and + are distributive for all a, b, and c in A

a + (b • c) = (a + b) • (a + c)
a • (b + c) = a • b + a • c

VI. For every element a in A there exists an element ~a such that

a • ~a = 0
a + ~a = 1

VII. There are at least 2 elements, a and b in A such that

a≠b
+ 0 1 • 0 1

Based upon these postulates

0 0 1 0 0 0
Simplest algebra consists of
The set of elements A = {0, 1} 1 1 1 1 0 1
Operations • and + defined as
For our proposed algebra
We will demonstrate that each of these postulates holds Discussions
Using the set A
I and II are satisfied
Based upon the members in set and {0,1}
Definitions of • and + given above
III is satisfied because the elements of the set are defined and
Definitions of the operators • and + are specified above
IV is satisfied from the definitions of the operators • and +
V is demonstrated using a truth table proof

LHS RHS
a b c b c a+b c a+b a+c (a + b) (a + c)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
VI given by exhaustive proof
a • ~a = 0
a + ~a = 1

Using the definitions for the operators • and +

Let a = 0
Then for the set A
~a must be 1 since 0 and 1 are the only elements in A
a • ~a = 0 • ~0 = 0 • 1 = 0 from definition of •
a + ~a = 0 + ~0 = 0 + 1 = 1 from the definition of +
Let a = 1
Then for the set A
~a must be 0 since 0 and 1 are the only elements in A
a • ~a = 1 • ~1 = 1 • 0 = 0 from definition of •
a + ~a = 1 + ~1 = 1 + 0 = 1 from the definition of +

VII proven similarly in text

From the basic axioms
Theorems
Following theorems can be derived
These are essential building blocks of all our future work

Th I The elements 0 and 1 are unique

Th II For every a in A
a•a=a
a+a=a
Th III For every a in A
a•0=0
a+1=1
Th IV The elements 0 and 1 are distinct and ~0 = 1
Th V For all a and b in A
a + a•b = a
a • (a + b) = a
Th VI For all a in A ~a is unique
Th VII For all a in A a = ~~a
Th VIII For all a, b, and c in A
a • [(a + b) + c] = a•(a + b) + a•c = a
Th IX For all a, b, and c in A
a + (b + c) = (a + b) + c
a•(b•c) = (a•b)•c
Th X For all a and b in A
a + ~a•b= a + b
(a + ~a) • (a + b)
a•(~a + b) = a•b
Can prove with a truth table
Th XI For all a and b in A De Morgan’s Law
~(a•b)= ~a + ~b
~(a + b) = ~a•~b

Note:
~(a•b) ≠ ~a•~b
De Morgan’s Law extends to any number of variables
For 3 variables we have
~(a•b•c)= ~a + ~b + ~c
~(a + b + c) = ~a•~b•~c
Proof of DeMorgan’s theorem by perfect induction
 Venn Diagram

(a) Constant 1 (b) Constant 0

x x x x x y

(c) Variable x (d) x (e) x ×y

x y
x y x y
z

(f) x + y (g) x ×y (h) x ×y + z

 x y x y

z z

(a) x (d) x ×y

x y x y

z z

(b) y + z (e) x ×z

x y x y

z z

(c) x ×( y + z) (f) x ×y + x ×z

Verification of the distributive property: x.(y+z) = x.y+x.z

 x y
x y x y
z
z z
x ×y
x ×y y ×z

x y
x y x y
z
z z
x ×z
x ×z x ×y + x ×z + y ×z

x y
x. y + x.z + y.z = x. y + x.z
z

x ×y + x ×z

Remark: the term y.z is fully covered by the terms x. y & x.z
 Getting Some Practice
Let’s now look at working with some of these axioms and theorems
When designing logic circuits several major goals
We trade these off in the process of design
One of major objectives is simplicity
Why
Cost
Lower failure rate
Easier to build
Easier to test
Can use above theorems to simplify logic expressions
Let’s try a few examples
Ex. 2.1

Ex. 2.2
Ex. 2.1

Ex. 2.2
 Complicated Example
Let’s look at more complex relationship
Consider serving tea from a vending machine
We have 3 items TLM Good Bad Tea
Tea ⇒ T 0 0 0 0 Tea 0 1
Lemon ⇒ L 1 0 0 1 0 1
Milk ⇒ M 2 0 1 0 0 1
3 0 1 1 0 1
How many variables ? 4 1 0 0 1 0
How many combinations ? 5 1 0 1 1 0
6 1 1 0 1 0
7 1 1 1 0 1
How to build logic expressions and circuit ?
 Synthesis
- Design a logic circuit consisting of 2 inputs x1 & x2 and a output
f(x1 , x2).
- Required functional behavior: The output must be “0” if the
switch x1 is closed and x2 is open; otherwise the output equals “1”

A function to be synthesized.
 x1
x2

(a) Canonical sum-of-products

f ( x1 , x2 ) = x1 x2 + x1 x2 + x1 x2
(b) Minimal-cost realization
f ( x1 , x2 ) = x1 x2 + x1 x2 + x1 x2
= x1 x2 + x1 x2 + x1 x2 + x1 x2
x1
= x1 x2 + x1 x2 + x1 x2 + x1 x2 x2
f

= ( x1 + x1 ) x2 + x1 ( x2 + x2 )
= x2 + x1
Two implementations of the desired functional behavior
 Minterm
n −1
2
f ( x1, x 2 ,..., x n ) = ∑ f(α1 , α 2 ,...., α n )x1 1 x 2 2 ...x n n
α α α

e=0

x i if α i = 1
where x i i = 
α

xi if α i = 0

Maxterm
n −1
∏ [f(α , α ,...., α ) + x1 1 + x 2 2 + ... + x n n ]
2
f ( x1, x 2 ,..., x n ) =
α α α
1 2 n
e =0

x i if α i = 0
where x i i = 
α

 xi if α i = 1
Three-variable minterms and maxterms.
 Vending Machine - Minterm
Two expressions written in what is called
Sum of products form TLM Good Bad Tea
Tea
Each product called minterm
0 0 0 0 0 1
Also known as implicant 1 0 0 1 0 1
These are also written as 2 0 1 0 0 1
GT = Σ 4, 5, 6 3 0 1 1 0 1
BT = Σ 0, 1, 2, 3, 7 4 1 0 0 1 0
or 5 1 0 1 1 0
GT = m4 + m5 + m6 6 1 1 0 1 0
BT = m0 + m1 + m2 + m3 + m7 7 1 1 1 0 1
Where 4, 5, and 6 etc. are binary equivalent of
Minterm variables
4 is 100 ⇒ T~L~M

We get these by identifying all terms

For which logical expression has truth value of 1
 TLM Good Bad Tea
Tea
0 0 0 0 0 1
1 0 0 1 0 1 M
T~M
2 0 1 0 0 1 T~M+T~L
3 0 1 1 0 1 T
4 1 0 0 1 0
5 1 0 1 1 0 T~L
L
6 1 1 0 1 0
7 1 1 1 0 1
Let’s now simplify the two expressions
GT = T~L~M + TL~M + T~LM A+A=A(= T~L~M)
= T ~M(~L + L) + T~L(M +~M) A + ~A = 1
= T~M + T~L A•1 = A
= T(~M + ~ L)
BT = ~T~L~M + ~T~LM + ~TL~M + ~TLM + TLM
= ~T~L(~M + M) + ~TL(~M + M) + TLM A + ~A = 1
= ~T~L + ~TL + TLM A•1 = A
= ~T(~L + L) + TLM
= ~T + TLM A + ~A = 1
= ~T + LM A + ~AB = A+B
 Vending Machine - Maxterm
Maxterm Mi = ~mi
We get a different form of expression if we cover 0’s
Terms for which value is False
We have now written the expressions in maxterm format
Also called product of sums
Can also be written as
GT = Π 0, 1, 2, 3, 7
BT = Π 4, 5, 6
or
GT = M0 • M1 • M2 • M3 • M7
BT = M4 • M5 • M6
These give a listing of the terms for which the
Logical expression is 0

Using De Morgan’s Law

GT = 0
= (T+L+M)(T+L+~M)(T+~L+M)(T+~L+~M)(~T+~L+~M)
BT = 0
= (~T+L+M)(~T+~L+M)(~T+L+~M)
 Example

f ( x1 , x2 , x3 ) = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3
A three-variable function.
 x2

f
x3
x1

f ( x1 , x2 , x3 ) = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3
(a) A minimal sum-of-products realization (minterm)

x1
x3
f

x2

f ( x1 , x2 , x3 ) = x2 x3 + x1 x3
(b) A minimal product-of-sums realization (maxterm)

Two realizations of the depicted function

Ex. 2.3
 x1

f
x2

x3

(a) SOP implementation

AND-OR realizations of the function in Example 2.3.

Ex. 2.4
 x1

x2 f

x3

(a) POS implementation

AND-OR & NOR-gate realizations of the function in Example 2.4.

Ex. 2.5
 NAND and NOR gates
x1
x2
x1
x1 ⋅ x2 x1 ⋅ x2 ⋅ … ⋅ xn
x2

xn

(a) NAND gates

x1
x2
x1
x1 + x2 x1 + x2 + … + xn
x2

xn

(b) NOR gates

 x1
x1 x1
x2 x2
x2

(a) x1 x2 = x1 + x2

x1
x1 x1
x2 x2
x2

(b) x1 + x2 = x1 x2

DeMorgan’s theorem in terms of logic gates.

 x1 x1
x2 x2
x3 x3
x4 x4
x5 x5

x1
x2
x3
x4
x5

Using NAND gates to implement a sum-of-products (instead of

using AND-OR networks)
 x1 x1
x2 x2

x3 x3
x4 x4
x5 x5

x1
x2

x3
x4
x5

Using NOR gates to implement a product-of sums (instead of using

OR-AND networks)
 x1

f
x2

x3

(a) SOP implementation

x1

f
x2

x3

(b) NAND implementation

AND-OR & NAND-gate realizations of the function in Example 2.3.

 x1

x2 f

x3

(a) POS implementation

x1

x2 f

x3

(b) NOR implementation

AND-OR & NOR-gate realizations of the function in Example 2.4.

 Design Example
- Light ON: 1 switch is closed; 3
switches are closed
- Light OFF: No switches or 2
switches are closed

- The canonical SOP form:

f = m1 + m2 + m4 + m7
= x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

- The POS form: Truth table for a three-way

f = M 0 .M 3 .M 5 .M 6 light control.
= ( x1 + x2 + x3 )( x1 + x2 + x3 )( x1 + x2 + x3 )( x1 + x2 + x3 )
 Implementation

x1
x2
x3

(a) Sum-of-products realization

x3
x2
x1

(b) Product-of-sums realization

 Design Multiplexer

From Truth Table, derive canonical SOP form

f ( s, x1 , x2 ) = sx1 x2 + sx1 x2 + s x1 x2 + sx1 x2
( ) ( )
= sx1 x2 + x2 + s x1 + x1 x2 = sx1 + sx2
Extension to larger circuits: A 4-to-1 & 8-to-1 multiplexers ?
- Design Entry
CAD Tools
- Schematic capture
- Hardware description languages
- IEEE Standards: Verilog HDL & VHDL
- Synthesis
- Compile Verilog code into a network of logic gates (part of synthesis)
- The output is a set of logic expressions
- Tools provide automatic manipulation on user’s design to generate an
equivalent but better circuit
- Functional Behavior Simulation
- For each valuation, simulator evaluates the outputs produced by expressions
- Assume perfect gates through which signals propagate instantaneously
- Physical Design
- Map a circuit in the logic expression forms into realization that makes use
of the available resources on target chips
- Timing Simulation
- Evaluate the expected delays of a designed logic circuit
- Chip Configuration
 Design conception

DESIGN ENTRY

Schematic capture Verilog

Synthesis

Functional simulation

No
Design correct?

Yes

Physical design

Timing simulation

No
Timing requirements met?