SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION

DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING

MALANDIGHI, DURGAPUR-712212

2. Combinational Logic
• Logic circuits for digital systems may be combinational or sequential.

• A combinational circuit consists of input variables, logic gates, and output variables.

2-1.a. Binary Adder

Half Adder:-

• A combinational circuit that performs the addition of two bits is called a half adder.
• The truth table for the half adder is listed below:

Final Equation :- Sum:- S = x’y + xy’ Carry:- C = xy

Full Adder:-

• One that performs the addition of three bits(two significant bits and a previous carry) is a full
adder.

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

• adder can also implemented with two half adders and one OR gate (Carry Look
Full-adder Look-Ahead
adder).

S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

2-2.b. Binary Parallel Adder

• This is also called Ripple Carry Adder ,because of the construction with full adders are connected
in cascade.

2-2.c.
2.c. Binary Adder Subtractor

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

2.2.d Binary Subtractor

2.2.e BCD Adder

Rules of BCD adder:

• When the binary sum is greater than 1001, we obtain a non-valid

non valid BCD representation.

• The addition of binary 6(0110) to the binary sum converts it to the correct BCD representation
and also produces an output carry as required.

• To distinguish them from binary 1000 and 1001, which also have a 1 in position Z8, we specify
further that either Z4 or Z2 must have a 1.

C = K + Z8Z4 + Z8Z2

Implementation of BCD adder

• A decimal parallel adder that adds n decimal digits needs n BCD adder stages.

• The output carry from one stage must be connected to the input carry of the next higher-order
higher
stage.

Magnitude comparator

• The equality relation of each pair of bits can be expressed logically with an exclusive-NOR
exclusive
function as:

A = A3A2A1A0 ; B = B3B2B1B0

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

xi=AiBi + Ai’Bi’ for i = 0, 1, 2, 3

(A = B) = x3x2x1x0
• We inspect the relative magnitudes of pairs of MSB. If equal, we compare the next lower
significant pair of digits until a pair of unequal digits is reached.
• If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B.
(A>B)= A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)= A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0

Decoders:-
• The decoder is called n-to to-m-line decoder, where m≤2n .
converters such as a BCD-to-seven
• the decoder is also used in conjunction with other code converters BCD
segment decoder.
• 3-to-8 8 line decoder: For each possible input combination, there are seven outputs that are equal
to 0 and only one that is equal to 1.

Demultiplexer:-
• A decoder with an enable input is referred to as a decoder/demultiplexer.
• The truth table of demultiplexer is the same with decoder.

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

Design 3-to-8
8 decoder with enable implement the 4-to-16
4 decoder

Implementation of a Full Adder with a Decoder

• From table 4-4,4, we obtain the functions for the combinational circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

Encoders
• An encoder is the inverse operation of a decoder.
• We can derive the Boolean functions by table 4-7
4
z = D1 + D3 + D5 + D7
y = D 2 + D 3 + D6 + D 7
x = D 4 + D 5 + D6 + D 7

Priority encoder
• If two inputs are active simultaneously, the output produces an undefined combination
combination. We can
establish an input priority to ensure that only one input is encoded.
• Another ambiguity in the octal binary encoder is that an output with all 0’s is generated
octal-to-binary
when all the inputs are 0; the output is the same as when D0 is equal to 1.
• The discrepancy
crepancy tables on Table 4-7
4 and Table 4-88 can resolve aforesaid condition by providing
one more output to indicate that at least one input is equal to 1.

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 SANAKA EDUCATIONAL TRUST’S GROUP OFF INSTITUTION
DEPT OF ELECTRONICS & COMMUNICATION ENGINEERING
MALANDIGHI, DURGAPUR-712212

Multiplexers

A more efficient method for implementing a Boolean function of n variables with a multiplexer that has
n-1 selection inputs.

F(x, y, z) = (1,2,6,7)

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