ISABELA STATE UNIVERSITY

CITY OF ILAGAN CAMPUS

COLLEGE OF ENGINEERING, ARCHITECTURE AND TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING

EE 312
MSI AND PLD COMPONENTS
SUBMITTED BY:
ABALOS, BRADLEY JAMES
BALTAZAR, MARK JUN
BAYUCAN, VENCE LOUIE
DAVELA, EDNALIE
SUBMITTED TO:
LALATA, JAN MARK
SANCHEZ, MIKE RYAN ENGR.PATRICIO M. MATIAS JR., MoM
Students
LEARNING OBJECTIVE
Understand the Basic Operations of Digital Systems
Learn the Functionality of Logic Components
Understand Multiplexing and Data Selection
Understand Memory and Logic Arrays
Learn the Design and Implementation of Logic Circuits
Application of Concepts in Digital System Design
 INTRODUCTION
There are several combinational circuits that are employed extensively in
the design of digital systems. These circuits are available in integrated
circuits and are classified as MSI(Medium-scale Integration)
components. MSI components performs specific digital functions
commonly needed in the design of digital systems

Now, we will discuss the most important combinational circuit-type MSI

components that are readily available in IC packages. These are adders,
subtractors, comparators, decoders, encoders and multiplexers.
The components of a digital system can be classified as being specific to
an application or as being standard circuits. Standard components are
taken from a set that has been used in other systems. MSI components
are standard circuits and their use results in a significant reduction in the
total cost as compared to the cost of using SSI circuits. In contrast,
specific components are particular to the system being implemented and
are not commonly found among the standard components. The
implementation of specific circuits with LSI chips can be done by means
of ICs that can be programmed to provide the required logic.
A programmable logic device (PLD) is an integrated circuit with internal logic
gates that are connected through electronic fuses. Programming the device
involves the blowing of fuses along the paths that must be disconnected so as to
obtain a particular configuration. The word “programming” here refers to a
hardware procedure that specifies the internal configuration of the device. The
gates in a PLD are divided into an AND array and an OR array that are
connected together to provide an AND-OR sum of product implementation.
The advantage of using PLDs in the design of digital systems is that they can be
programmed to incorporate complex logic functions within one LSI circuit. The
use of programmable logic devices is an alternative to another design technology
called VLSI design. VLSI design refers to the design of digital systems that
contains thousands of gates within a single integrated-circuit chip. The basic
component used in VLSI design is the gate array. A gate array consists of a pattern
of gates fabricated in an area of silicon that is repeated thousands of times until the
entire chip is covered with identical gates
 BINARY ADDER AND SUBTRACTOR
Binary Adder: A binary adder performs the addition of binary numbers. The
simplest form is a half-adder, which adds two single-bit numbers. A full-adder adds
three bits, including a carry input.
Half Adder: Adds two binary digits and provides a sum and carry output.
Full Adder: Adds three binary digits (two inputs and a carry input) and provides
a sum and carry output.
Binary Subtractor: A binary subtractor is used to perform the subtraction of binary
numbers. The simplest form is a half-subtractor, which subtracts one binary digit from
another, while the full-subtractor takes into account a borrow bit from a previous
subtraction.
Half Subtractor: Subtracts one bit from another and outputs the difference and
borrow.
Full Subtractor: Subtracts three bits (two input bits and a borrow input) and
provides the difference and borrow output.
K-map for half adder
Full Adder
Logic Diagram of Full adder
 DECIMAL ADDER
Computers or calculators that perform arithmetic operations directly in the
decimal number system represent decimal numbers in binary-coded form. An
adder for such a computer must employ arithmetic circuits that accept coded
decimal numbers and present results in the accepted code. For binary addition, it
was sufficient to consider a pair of significant bits at a time, together with a
previous carry. A decimal adder requires a minimum of nine inputs and five
outputs, since four bits are required to code each decimal digit and the circuit
must have an input carry and output carry. Of course, there is a wide variety of
possible decimal adder circuits, dependent upon the code used to represent the
decimal digits.
The BCD-Adder is used in the computers and the calculators that perform
arithmetic operation directly in the decimal number system. The BCD-Adder
accepts the binary-coded form of decimal numbers. The Decimal-Adder requires a
minimum of nine inputs and five outputs.
There is the following table used in designing of BCD-Adder.
From the given table,
it is clear that if
the produced sum is
between 1 to 9, the
Binary and the BCD
code is the same. But for
10 to 19 decimal
numbers, both the codes
are different. In the
above table, the binary
sum combinations from
10 to 19 give invalid
BCD. There are the
following points that
help the circuit to
identify the invalid
BCD.
1. We take a 4-bit Binary-Adder, which
takes addend and augend bits as an
input with an input carry 'Carry in'.
2. The Binary-Adder produces five
outputs, i.e., Z8, Z4, Z2, Z1, and an
output carry K.
3. With the help of the output carry K
and Z8, Z4, Z2, Z1 outputs, the logical
circuit is designed to identify the Cout
4. The Z8, Z4, Z2, and Z1 outputs of the
binary adder are passed into the 2nd 4-
bit binary adder as an Augend.
5. The addend bit of the 2nd 4-bit binary
adder is designed in such a way that
the 1st and the 4th bit of the addend
number are 0 and the 2nd and the 3rd
bit are the same as Cout. When the
value of Cout is 0, the addend number
will be 0000, which produce the same
result as the 1st 4-bit binary number.
But when the value of the Cout is 1,
the addend bit will be 0110, i.e., 6,
which adds with the augent to get the
valid BCD number.
 MAGNITUDE COMPARATOR
A magnitude digital Comparator is a combinational circuit that compares
two digital or binary numbers in order to find out whether one binary
number is equal, less than, or greater than the other binary number. We
logically design a circuit for which we will have two inputs one for A and the
other for B and have three output terminals, one for A > B condition, one for
A = B condition, and one for A < B condition.
Magnitude comparator is a type of Combinational circuit, It Basically compares
two binary numbers and determines their relative magnitude. It gives output
whether one number is greater than the other, or less than or equal. These
comparators are used in digital systems, such as for sorting networks, and
decision-making circuits to handle numerical comparisons perfectly without any
error.
The circuit works by comparing the bits of the two numbers starting from the most
significant bit (MSB) and moving toward the least significant bit (LSB). At each bit
position, the two corresponding bits of the numbers are compared. If the bit in the first
number is greater than the corresponding bit in the second number, the A>B output is
set to 1,and the circuit immediately determines that the first number is greater than the
second. Similarly, if the bit in the second number is greater than the corresponding bit
in the first number, the A<B output is set to 1, and the circuit immediately determines
that the first number is less than the second.
 1 Bit Magnitude Comparator
A comparator used to compare two bits is called a single-bit comparator. It
consists of two inputs each for two single-bit numbers and three outputs to
generate less than, equal to, and greater than between two binary numbers.
The truth table for a 1-bit comparator is given below.

From the above truth table

logical expressions for each
output can be expressed as follows.
By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below.
APPLICATION OF COMPARATORS
Comparators are used in central processing units (CPUs) and
microcontrollers(MCUs).
These are used in control applications in which the binary numbers representing
physical variables such as temperature, position, etc. are compared with a reference
value.
Comparators are also used as process controllers and for Servo motor control.
Used in password verification and biometric applications.
ADVANTAGES DISADVANTAGES
Comparators are simple and efficient for Comparators have limit of
comparison of binary values. bits for comparison.
Fast decision-making in Digital Circuits.
This comparator can be easily integrated
It requires more complex
in to complex systems like processors and circuit for large bits.
arithmetic units. Power consumption
Design of comparator are modular, which increase with increase in the
allow them to scale solutions for
comparing multi-bit numbers
complexity of the circuit.
 ENCODER AND DECODER
Encoders - An encoder is a combinational circuit that converts binary information in
the form of a input lines into N output lines, which represent N bit code for the input.
For simple encoders, it is assumed that only one input line is active at a time.

As an example, let’s consider Octal to Binary encoder. As shown in the figure below,
an octal-to-binary encoder takes 8 input lines and generates 3 output lines.
As seen from the truth table, the output is 000 when D0is active; 001 when D1 is
active, 010 when D2 is active. The output line Z is active when the input octal digit is
1, 3, 5 or 7. Similarly, Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input
octal digits 4, 5, 6 or 7.
The Boolean functions would be: Implementing the logic gates we get:

Priority Encoder
One limitation of this encoder is that only one input can be active at any given time. If
more than one inputs are active, then the output is undefined. For example, if D6 and
D3 are both active, then, our output would be 111 which is the output for D7. To
overcome this, we use Priority Encoders.
 Priority Encoder solves the problems mentioned above by allocating a priority
level to each input. The priority encoders output corresponds to the currently
active input which has the highest priority. So, when an input with a higher priority
is present, all other inputs with a lower priority will be ignored.
An example of an 8-input priority encoder along with its truth table shown below.

Where X equals “don’t care”, that is it can be 0 or 1.

Priority encoders output the highest order input first for example, if input lines
“D2“, “D3” and “D5” are applied simultaneously the output code would be for
input “D5” (101) as this has the highest order out of the 3 inputs. Once input “D5”
had been removed the next highest output code would be for input “D3” (011).
The Boolean expression for the encoder above with data inputs D0 to D7 and outputs
Q0, Q1, Q2 is given as: Implementing the logic gates we get:

Decoders
A decoder does the opposite job of an encoder. It is a combinational circuit that
converts N lines of input into lines of output.
An example of 3-to-8 line decoder
Implementation
D0 is high when X = 0, Y = 0 and Z = 0. Hence,
D0 = X’ Y’ Z’
Similarly,
D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z
Hence,
 MULTIPLEXERS (MUX)
Multiplexing means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit
that selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally, there are 2" input lines and n selection lines whose bit combinations
determine which input is selected.

Key Components:
Input Lines: Each input line carries a different signal. The number of input lines is
usually a power of two (2, 4, 8, 16, etc.).
Selector Lines: These lines determine which input signal is selected. The number of
selector lines is equal to the logarithm (base 2) of the number of input lines. For
example, with 4 input lines, you need 2 selector lines (log2(4) = 2).
Output Line: The multiplexer outputs only the selected input signal.
How it Works:
Input Signals: Each input line carries a different signal.
Selector Lines: The selector lines act as "address" for the input signals.
Selection: The combination of values on the selector lines determines which input
signal is selected.
Output: The selected input signal is routed to the output line.
Multiplexers are essential components in digital electronics, enabling efficient signal
selection and routing. They play a crucial role in various applications, from data
transmission to communication systems. Understanding their operation and
advantages/disadvantages is key to designing efficient and effective digital circuits.

Advantages:
· Reduced wiring
· Efficient Data Transmission
· Flexibility and Control
· Cost-Effective
Example:
2-input Multiplexer Design
The input A of this simple 2-1 line multiplexer circuit constructed from standard
NAND gates acts to control which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data select input, A is LOW at
logic 0, input I1 passes its data through the NAND gate multiplexer circuit to the
output, while input I0 is blocked. When the data select A is HIGH at logic 1, the
reverse happens and now input I0 passes data to the output Q while input I1 is
blocked.

So by the application of either a logic “0” or a logic “1” at A we can select the
appropriate input, I0 or I1 with the circuit acting a bit like a single pole double throw
(SPDT) switch.
As we only have one control line, (A) then we can only switch 21 inputs and in this
simple example, the 2-input multiplexer connects one of two 1-bit sources to a
common output, producing a 2-to-1-line multiplexer. We can confirm this in the
following Boolean expression.

Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1

and for our 2-input multiplexer circuit above, this can be simplified too:
Q = A.I1 + A.I0

We can increase the number of data inputs to be selected further simply by following
the same procedure and larger multiplexer circuits can be implemented using smaller
2-to-1 multiplexers as their basic building blocks. So for a 4-input multiplexer we
would therefore require two data select lines as 4-inputs represents 22 data control
lines give a circuit with four inputs, I0, I1, I2, I3 and two data select lines A and B as
shown.
 READ-ONLY MEMORY (ROM)
A ROM is essentially a memory (or storage) device in which permanent binary in-
formation is stored. The binary information must be specified by the designer and is
then embedded in the unit to form the required interconnection pattern. ROMs come
with special internal electronic fuses that can be "programmed" for a specific config-
uration. Once the pattern is established, it stays within the unit even when power is
turned off and on again.
A block diagram of a ROM is shown. It consists of n input
lines and m output lines.Each bit combination of the input
variables is called an address. Each bit combination that
comes out of the output lines is called a word. The number
of bits per word is equal to the number of output lines, m.
An address is essentially a binary num-ber that denotes one
of the minterms of a variables. The number of distinct
addresses possible with n input variables is 2". An output
word can be selected by a unique ad-dress,and since there
are 2" distinct addresses in a ROM, there are 2" distinct
words that are said to be stored in the unit. The word
available on the output lines at any given time depends on
the address value applied to the input lines.
 The number of addressed words in a ROM is determined from the fact that n input lines are
needed to specify 2" words. A ROM is sometimes specified by the total num-ber of bits it
contains, which is 2" X m.

Example:
A 2048-bit ROM may be organ-ized as 512 words of 4 bits each. This means that the unit has
four output lines and nine input lines to specify 2°=512 words. The total number of bits stored in
the unit is 512x4=2048.

Combinational Logic Implementation

From the logic diagram of the ROM4, it is clear that each output provides the sum of all the
minterms of the n input variables. Remember that any Boolean function can be cx-pressed in sum
of minterms form. By breaking the links of those minterms not in-cluded in the function, each
ROM output can be made to represent the Boolean func-tion of one of the output variables in the
combinational circuit. For an n-input,referred to as programming the ROM. The designer need
only specify a ROM program table that gives the information for the required paths in the ROM.
The actual pro-gramming is a hardware procedure that follows the specifications listed in the
program table.
Combinational-circuit inplementation with a 4 x 2 ROM

(b) ROM with AND-OR gates (c) ROM with AND-OR-INVERT gates (a) Truth table
The ROM that implements the combinational circuit must have two inputs and
two outputs; so its size must be 4 x.2. Figure 5-23(b) shows the internal construc-
tion of such a ROM. It is now necessary to determine which of the eight available
fuses must be blown and which should be left intact. This can be easily done from
the output func-tions listed in the truth table. Those minterms that specify an output
of 0 should not have a path to the output through the OR gate. Thus, for this
particular case, the truth table shows three O's, and their corresponding fuses to the
OR gates must be blown.It is obvious that we must assume here that an open input to
an OR gate behaves as a 0input.
The required paths in a ROM may be programmed in two different ways. The
first is called mask programming and is done by the manufacturer during the last
fabrication process of the unit. The procedure for fabricating a ROM requires
that the customer fill out the truth table the ROM is to satisfy.The truth table
may be submitted on a special form provided by the manufacturer. More often,
it is submitted in a computer
input medium in the format specified on the data sheet of the particular ROM.
The manufac-turer makes the corresponding mask for the paths to produce the
I's and O's according customer a special fee for custom masking a ROM. For this
reason, mask programming is economical only if large quantities of the same
ROM configuration are tobe manu-factured.
For small quantities, it is more ecomomical to use a second type of ROM called a
programmable read-only memory, or PROM. When ordered, PROM units contain all O's
(or all I's) in every bit of the stored words. The fuses in the PROM are blown by application
of current pulses through the output terminals. A blown fuse defines one bi.nary state and an
unbroken link represents the other state. This allows the user to pro-dresses and stored
words. Special units called PROM programmers are available commercially to facilitate this
procedure. In any case, all procedures for programming ROMs are hardware procedures
even though the word programming is used.
ROMs are widely used to implement complex combinational circuts directly from their truth
tables. They are useful for converting from one binary code to another (such as ASCII to
EBCDIC and vice versa), for arithmetic functions such as multipliers,for display of
characters in a cathode-ray tube, and in many other applications requiring a large number of
inputs and outputs. They are also employed in the design of control units of digital systems.
As such, they are used to store fixed bit patterns that represent the sequence of control
variables needed to enable the various operations in the system.A control unit that utilizes a
ROM to store binary control information is called a mi-croprogrammed control unit.
 PROGRAMMABLE LOGIC ARRAY
A Programmable Logic Array therefore, comprises of a PLA chip having a fixed
wiring structure of AND gates followed by OR gates that can be programmed.
PLA is a type of programmable logic device to construct a reconfigurable digital
circuit on its architecture. It includes memory as well as logical operation which
enable the user to instruct the device to perform certain operations of logic. As
indicated by many authors, PLAs themselves are not configured with a specific
function at the time of manufacturing and are configured before use.
A Programmable Logic Array (PLA) is the implementation of the combinational logic
circuits using a programmable type of a digital logic device. There is a programmable
AND gate array with a programmable OR gate inputted thereafter, a feature that
enables users to specify the required custom logic. PLAs tend to be more versatile due
to their capability of being programmed to operate multiple logic functions and hence
can be used in the designing of specific hardware solutions.
 Comparison with other Programmable Logic Devices
PLA has a programmable AND gate array and programmable OR gate array.
PAL has a programmable AND gate array but a fixed OR gate array.
ROM has a fixed AND gate array but programmable OR gate array.
Features of Programmable Logic Array
Programmable AND and OR Gates: PLA has two types of arrays, namely
programmable AND gate array and programmable OR gate array so that the logic
circuits can be designed in any way.
Reconfigurability: As compared with other logic devices, the operation of PLAs is
highly flexible and these devices may be easily programmed to perform any of the
numerous logical functions.
Partial Minterm Generation: It is also to be noted here that PLA does not provide the
full decoding of variables like ROM but it functions only the necessary minterms.
Combination of Memory and Logic: PLA has both the memory and the logic features
hence making it suitable for various applications.
 BASIC BLOCK DIAGRAM OF PLA

F1 = AB’C’ + ABC’ + ABC

on simplifying we get : F1 = AB+ AC’
F2 = A’BC + AB’C + ABC
on simplifying we get: F2 = BC + AC

For the realization of the above function

following circuit diagram will be used.
The Operation of a PLA can be Summarized in Three Steps
1. Programming: The user defines the logic function to be implemented by the
PLA by programming the input and output configurations into the device.
2. Product term generation: The inputs are applied to the AND gate array to
produce a set of product terms.
3. Sum term generation: The product terms are then applied to the OR gate
array to generate the final output.

PLAs are often used in digital systems as they are versatile and allow complex
functions to be implemented easily. They are particularly useful for
implementing Boolean expressions with many variables as the arrays of AND
gates and OR gates can be configured to handle large numbers of inputs.
 PROGRAMMABLE ARRAY LOGIC
Programmable Array Logic (PAL) is a commonly used programmable logic
device (PLD). It has programmable AND array and fixed OR array. Because
only the AND array is programmable, it is easier to use but not flexible as
compared to Programmable Logic Array (PLA). PAL’s only limitation is
number of AND gates.
The Programmable Array Logic (PAL) is a programmable logic device that
allows the implementation of the combinational logic circuits with the fixed
OR array and a programmable AND array. This architecture enables the
design of the specific logic functions by the configuring the connections in
the AND array while the OR array remains static. The PALs are commonly
used in digital systems for the creating custom logic circuits efficiently. PAL
consist of small programmable read only memory (PROM) and additional
output logic used to implement a particular desired logic function with
limited components.
Key Components of Programmable Array Logic (PAL)
Programmable AND Array
The AND array consists of the multiple AND gates whose connections can be
programmed by the designer. This allows for the creation of the various logic functions by
the combining different input signals.
Fixed OR Array
The OR array is a set of fixed OR gates that combine the outputs from programmable
AND gates. The outputs from the AND gates feed into the OR gates allowing for the final
logic outputs.
Inputs and Outputs
The PAL devices have a number of inputs that feed into the AND array and a defined
number of the outputs that represent the result of the logic operations.
Programming Mechanism
The PALs are programmed using the hardware description language (HDL) or through
the special programming tools. This programming defines how the inputs are connected to
the AND gates.
Example: Realize the given function by using PAL: Any form from sum of
product (SOP) form or product of sum (POS) can be used for realization of a
Boolean function.

There are three inputs A, B, C and three functions X, Y, Z. Using sum of product
(SOP) terms to express the given function as follows:
X ( A,B,C) = ∑(2,3,5,7)
Y ( A,B,C) = ∑(0,1,5)
Z (A,B,C) = ∑(0,2,3,5)
Following Truth table will be helpful in
understanding function on number of
inputs:
Here ,place 1 as we take in part of the
question( for example there is given that
X=2,3,5,7 place 1 in the column of X for
this values)
Finding X, Y, Z: Look for
high minterms (function
value is equal to 1 in case
of SOP) in each function
output:
X = A’B + AC
Y = A’B’ + B’C
Z = A’B + A’C + AB’C

AND array has been programmed

but have to work with fixed OR array
as per requirement. Desired lines will
be connected in PLDs.
Advantages of PAL
Highly efficient
Low production cost as compared to PLA
Highly secure
High Reliability
Low power required for working.
More flexible to design.
Disadvantages of PAL
Limited Flexibility: Once programmed, the configuration of the AND array cannot be
altered limiting the flexibility of design compared to the more advanced programmable
devices like Field Programmable Gate Arrays (FPGA).
Size Constraints: The PAL devices may have a limited number of logic gates and
inputs which can restrict the complexity of the logic circuits that can be implemented.
Propagation Delay: The fixed structure of the OR array may introduce propagation
delays that can affect the performance of the high-speed applications.
MCQ ( Multiple Choice Questions)
1. Circuit that converts n input to 2^n outputs is called
A. Encoder
B. Decoder
C. Comparator
D. Carry look ahead
2. All the comparison made by comparator is done using
A. 1 circuit
B. 2 circuits
C. 3 circuits
D. 4 circuits
3. A binary Coded Decimal (BCD) adder is a circuit that adds two BCD digits
in parallel and produces a result in
A. Hexadecimal code
B. Binary Code
C. BCD code
D. Decimal code
4. Encoder are made by three
A. AND gate
B. OR gate
C. NAND gate
D. XOR gate
5. Small scale integrated (SSI) circuits has several independent gates about
A. 12 or 14 pins
B. 13 or 14 pins
C. 14 or 16 pins
D. 15 or 16 pins
6. PROM stands for
A. Permanent Read Only Memory
B. Portable Read Only Memory
C. Programmable Read Only Memory
D. Plugin Read Only Memory
7.PLD stands for
A. Portable Large Device
B. Portable logic Device
C. Programmable large Device
D. Programmable Logic Device
8. A binary parallel adder produces the arithmetic sum in
A. Serial
B. parallel
C. Sequence
D. Both a and b
9. Decoder is a
A. Combinational circuit
B. Sequential circuit
C. Complex circuit
D. Gate
10. Read Only Memory (ROM) is a
A. Non volatile memory
B. Secondary memory
C. Volatile memory
D. Small memory
Answer keys:
1. B 2. A 3. B 4. B 5. C 6. C 7. D 8. B 9. A 10. A