Introduction Motivation

IDDQ testing (Static Current Testing) is a method used to detect ◼ Zero defects or six sigma, and is considered mandatory for
defects in integrated circuits (ICs) by measuring the quiescent semiconductor companies to be competitive in the U.S. and
supply current (IDDQ) when the circuit is in a non-switching, international markets. Conventional approaches to meeting
idle state. this goal involve:
▪ Increasing test fault coverage
The basic principle behind IDDQ testing is that under normal
▪ Increasing burn-in coverage
conditions, a fault-free CMOS circuit draws a predictable and
▪ Increase electro-static damage awareness
low amount of current when it is not actively switching.
IDDQ current testing has been effective in achieving low defect
If there are defects, such as short circuits, leakage, or open levels.
circuits, the current will deviate from the expected value, IDDQ testing can significantly improve quality, decrease chip
indicating a potential fault. production cost, and is very useful for failure effect analysis
(FEA.)

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Basic Principle of IDDQ Testing Basic Principle of IDDQ Testing

Figure shows a CMOS inverter, with a * indicating a defect in the pFET Figure shows the input and output voltages, and the drain current that flows
that causes its input impedance to drop from infinity to a finite value. through the transistors. After switching completes, this current is referred to
Now, the DC current flows in steady state along the path indicated by the as the quiescent current and called IDDQ
arrow, and this elevates the steady state current, since current can still
flow through the defective pFET In the good circuit IDDQ falls to a negligible value, whereas in the defective
circuit IDDQ, remains elevated long after switching is over. We detect such
faults by measuring at the time instant shown by the arrow.

Measure IDDQ current through Vss bus

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Key Principles

◼ ATE can measure the IDDQ current at the VSS pin of the circuit, or, Idle State Behavior:
alternatively, we can build in a current measurement device into the ✓ In CMOS circuits, when the transistors are not switching (i.e., in a steady
VSS bus on the chip. state), they ideally should not consume significant power.
◼ IDDQ tests were used for functional tests, for testing delay ✓ The circuit should only draw a minimal amount of current—this is the
faults, and to detect pattern sensitive memory failures. quiescent current (IDDQ).
Defect-Induced Current Changes:
◼ IDDQ testing measures a current, which is inherently much
slower than measuring a voltage, as in stuck-fault testing. A defect in the circuit, such as a short circuit, leakage path, or a stuck-at
fault, will cause the circuit to draw more current than expected.
◼ The sub-threshold conduction current of MOSFETs increases, and
For instance:
the increased density of chips with 50 to 100 million
– A short circuit could cause a direct current path between the power
transistors makes it difficult to distinguish the defective current
supply and ground, leading to abnormal current.
from normal devices with somewhat elevated leakage currents
– A stuck-at fault could leave a node at a constant voltage, causing the
circuit to behave abnormally, which can manifest as an increase in
IDDQ.

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Key Principles Key Principles

IDDQ Measurement: Static Testing:

The IDDQ test involves powering the chip and measuring the IDDQ testing does not require dynamic or functional testing (i.e.,
supply current (IDDQ) while the chip is in a non-switching it doesn't require applying test vectors to the circuit). It simply
involves measuring the current while the circuit is powered
state. This measurement is compared to a known threshold
and idle, making it a static test.
value.
Nature of CMOS Circuits:
If the measured current exceeds this threshold, a defect is
CMOS technology (Complementary Metal-Oxide-
suspected. Semiconductor) is particularly suited to IDDQ testing. In
Threshold Current: CMOS circuits, there are two types of transistors (n-channel
A threshold IDDQ value is set based on typical circuit behavior. and p-channel) that ideally should not conduct current when
If the measured IDDQ is too high, it indicates that the circuit is they are not switching, contributing to low power
likely defective. consumption.
The threshold depends on the circuit’s complexity and
technology, and it is determined during the design phase.
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Faults Detected by IDDQ Tests Faults Detected by IDDQ Tests

◼ IDDQ testing can sometimes detect: ◼ A defect is a physical occurrence in a semiconductor device,
▪ transistors stuck-open, and a fault is a defect manifestation.
▪ transistors stuck-closed, ◼ One defect causes more than one fault, often of different
types.
▪ transistor gate oxide shorts (exhibiting a diode behavior),
◼ A pinhole short through the gate oxide of a pFET in a digital
▪ interconnect bridging shorts,
NOR gate can cause an input-to-output bridging fault, a
▪ unpowered interconnect opens.
slow-to-rise delay fault, and an excessive IDDQ current fault.
◼ A gate oxide short has resistive behavior if both shorted
terminals are doped the same type (n or p), but has diode
behavior otherwise.

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Faults Detected by IDDQ Tests

Bridging Defects with Stuck-at Fault Behavior
▪ Stuck-at Faults Levi noticed that an IDDQ test detected the Bridging of a
▪ Bridging Defects with stuck-at fault behavior logic node to VDD or VSS – which is a true stuck-at fault.
▪ Floating Gate Defects These are a small percentage of the real defects.
▪ Bridging Faults • Transistor gate oxide short of 1 to 5 Kohm to source also
▪ CMOS Stuck-Open Faults causes a stuck-at fault.
▪ Delay Faults ◼ IDDQ test vectors must drive all logic gate input/output nodes
to logic 0 and 1 for detecting all such faults.
▪ Leakage Faults
◼ Defects causing both n and pFET transistors in a gate to be
▪ Weak Faults
on are almost always detected by IDDQ tests.
▪ Transistor Stuck-Closed Faults
▪ Gate Oxide Short Failures

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Floating Gate Defects Floating Gate Defects
In Figure shows the open leaves at a voltage that is a function of the circuit
◼ Many defects causing open circuits elevate IDDQ current.
parasitics. The output then may behave as a stuck-at fault, and may have
◼ These defects in transistor gates usually do not fully turn off either a weak or strong logic voltage because of the logic gate analog voltage
the transistor. gain.

◼ Small break in logic gate inputs (100 – 200 Angstroms)still

allows signal coupling between two wire fragments by
electron tunneling .
◼ This cause Delay fault and elevation of IDDQ current which
can be tested with an IDDQ test.
◼ A large open results in stuck-at fault which some times
can be tested by an IDDQ test . ◼ Weak output voltage happens when Vtn < Vfn < VDD - |Vtp | then detectable
by IDDQ test.
◼When large line breaks occur, tunneling effects are
negligible.
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Floating Gate Defects Multiple IDDQ Fault Example

◼ The floating gate voltage is determined by capacitive

coupling of the broken polysilicon path to the metal lines
crossing it.
◼ For certain floating gate defects, the transistor conducts, and
for others it remains stuck-open.
◼ Floating gate voltage depends on these capacitances and node
voltages.
◼ If the nFET gets enough voltage at its gate to turn it on, then
a path from VDD to ground exists if the pFET is on, so
the abnormal current can be sensed.
◼ The floating gate voltage is sufficient to activate the faulty
transistor over many conditions. Figure shows the circuit schematic modeling the severed
transistor gate with the capacitance from poly to bulk, and the overlapped metal wire
to floating poly capacitance

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Capacitive Coupling of Floating Gates Bridging Faults S1 – S5

◼ Cpb–capacitance from poly to bulk

◼ Cmp–overlapped metal wire to poly
◼ Floating gate voltage depends on
capacitances and node voltages
◼ If nFET and pFET get enough gate
voltage to turn them on, then IDDQ test
detects this defect

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Bridging Faults CMOS Transistor Stuck-Open Faults
◼ A logic gate bridging fault may be an absolute short or a ◼ CMOS transistors stuck-open cause high impedance states
higher resistance short between two logic gates. at a logic gate output, and under certain situations, is
◼ For voltage testing, the fault is activated with a test vector elevated and the fault can be detected.
that places opposite logic values across the fault (at the two ◼ IDDQ testing does not guarantee detection, but works in
different logic gates), and then sensitizes two paths from the practice, because the floating output node is capacitively
logic gate outputs to two primary outputs. coupled into the substrate, as well.
◼ A deviant voltage at one of the POs reveals the fault. ◼ The coupling often results in an intermediate voltage on the
◼ With IDDQ testing, propagation is not required. node.

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Delay Faults Leakage Faults

◼ Most random CMOS defects cause a timing delay fault, not ◼ No leakage in a healthy MOSFET, except between source
catastrophic failure. and bulk and also between drain and bulk.
◼ Many of these defects elevate IDDQ current, which also ◼ Must be less than a specified value.
changes the signal rise and fall times test ◼ Gate oxide shorts can cause leakage between gate and source
◼ Many delay faults are detected with few IDDQ test or between gate and drain.
vectors ◼ Proposed six leakage faults for each MOSFET:
◼ Delay faults not detected by IDDQ test: ▪ Leakage path flags: fGS, fGD, fSD, fBS, fBD, and fBG
▪ Resistive via fault in interconnect G = gate, S = source, D = drain, B = bulk
▪ Increased transistor threshold voltage fault
◼ In the above proposal they Assume that leakage faults do not
IDDQ testing may be an inexpensive way to detect some change circuit logic values, which is true for gate oxide shorts
delay fault during production test.

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Weak Faults Paths in Circuit

◼ nFET passes logic 1 as 5 V – Vtn

◼ pFET passes logic 0 as 0 V + |Vtp|

◼ A weak fault causes one of the devices to fail to turn on, so the
signal passed from the source to the drain of the C-switch
is degraded (has a weak voltage), which increases
propagation delays and increases noise.
◼ Weak fault – one device in C-switch does not turn on
▪ Causes logic value degradation in C-switch

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Weak Faults Transistor Stuck-Closed Faults

◼ Two conditions to have a weak-0 (1) fault are: ◼ In CMOS, gate oxide short (GOS) failures Gate Oxide Short
1. At least one normal-0 (1) conducting path between ni and VSS happen frequently, resulting in an undesirable
(VDD) in good circuit, and all normal-0 (1) conducting paths current path through the MOSFET gate
should be blocked in the bad circuit. oxide.
2. At least one weak-0 (1) conducting path between node ni and ◼ The gate is no longer isolated from the
VSS (VDD) in the bad circuit. channel.
◼ A node may have multiple weak-0 (1) faults, must be ◼ Figure show an nFET with a gate oxide short.
considered separately because detection of one does not ◼ The transistor is split into two transistors,
imply detection of the others. separated by a rectifying barrier between the
◼ Assume that a weak-0 (1) fault at a node is caused by channel and the gate.
blocking of all normal-0 (1) conducting paths due to a single ◼ Parameter k is the location of the defect in the
defective transistor channel, and RS is the short resistance.

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IDDQ Testing Methods

IDDQ Fault Coverage Metrics
Malaiya and Su were the first to propose a new conductance fault The great significance of their work was a proof that a stuck-fault
model , in which current monitoring is used to detect all of the test set can be used to generate the minimum complete leakage
leakage faults in transistors during application of conventional fault test set.
single stuck-at fault test vectors.
A conventional logic fault simulator is modified to simulate these
Their model handled open wires, open/shorted transistors, and
leakage faults. effects, by requiring each stuck-at fault to propagate through a
single logic gate, rather than to a primary output.
An on transistor was modeled with a high conductance, and an
off transistor was modeled with a leakage conductance. The pseudo-stuck-at fault coverage is a voltage stuck-at coverage
A leaky transistor has a minimum conductance greater than the that represents the internal transistor shorts coverage and hard
maximum allowable conductance, and a normal transistor has stuck-at faults
a maximum conductance less than the allowable maximum
conductance.

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Vector Selection with Full Scan

IDDQ Test Vector Selection from Stuck- Fault Vector Sets

◼ Vector Selection with Full Scan ◼ Perry used voltage testing vectors and full-scan for testing.
◼ He measured current whenever the voltage test vector set hit an
◼ Vector Selection from Complete Stuck-Fault Tests internal scan chain boundary, so all internal nodes, chip inputs, and
◼ Hierarchical Test Vector Selection outputs were in a known state and made the test repeatable.
◼ He used only the first 10 scan ring boundaries for making
measurements, by applying a vector that minimized current.
◼ This vector sets all chip inputs with pull-up resistors to high,
disables all clocks, and sets all tristate outputs into high-impedance
mode.
◼ Stopping the clock holds the internal chip state constant.
◼ The minimum test vector also set all bidirectional inputs to a known
state, if they were in an output mode when the measurement was to
be made. The remaining inputs were held in their present state for
the measurement.

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 Leakage Fault Detection
Vector Selection from Complete Stuck-Fault Tests
◼ Mao and Gulati developed leakage and weak fault models to test for gate
◼ Leakage fault detection depends on the circuit’s logic state.
oxide shorts and opens. They select a subset of a complete logic-level test
vector set for fault tests. ◼ In Figure transistor N2 has a gate to source leakage fault fGS,
which is detected only if node Vb is at logic 1 and input VIN
is at logic 1.
◼ This creates the IDDQ leakage current through the fault.
◼ Detection requires that two transistor terminals with leakage
must have opposite logic values, and be at driving strengths.
◼ Non-driving or high-impedance states are insufficient since a
current path cannot be made through them.

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Weak Fault Detection – P1 (N1) Open Hierarchical Vector Selection

◼ Weak fault in Figure is detected if logic 1 (0) is applied when ◼ Generate complete stuck-fault tests
◼ Characterize each logic component to relate input/output logic
transistor P1 (N1) is open.
values and internal states to detection of :
◼ This degrades the input voltage at the load inverter, so both ▪ leakage fault
inverter transistors remain partially turned on. ▪ weak fault sensitization/propagation
◼ Elevates IDDQ from 0 to 56 A. This step involves switch-level simulation but is done only once
for each component type to characterize it.
◼ Store information in leakage and weak fault tables
◼ After that, a logic simulator captures input/output and internal state
values of each component instance due to the current test vector.
◼ The previously-generated fault tables indicate which leakage/weak
faults are detected by each vector, without the need for more switch-
level simulation

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Weak Fault Tables Weak Fault Tables

◼ The sensitization of a weak fault with an internal fault node The weak fault sensitization table contains all sensitized
depends only on I/O states of the faulty component. weak faults, associated boundary nodes, and sensitized
◼ Weak faults on component boundaries are sensitized by the but undetected weak faults associated with internal
I/O states of the component, but their propagation is boundary nodes for each component I/O state.
determined by either the I/O states of the component with the The weak fault propagation table shows the inputs that
weak fault or the I/O states of components driven by the node propagate a sensitized weak fault at the component
with the weak fault. input.
◼ After characterization, a weak fault detection table is
generated containing all detected weak faults associated with
internal nodes or nodes with weak faults.

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IDDQ Test Vector Selection IDDQ Test Vector Selection

◼ The circuit undergoes gate-level simulation using ◼ Component boundaries influence test vector selection.
the production stuck-fault test patterns. ◼ A node can have a weak fault due to a normal conducting
◼ Logic levels at inputs/outputs of all components path in one component, and a weak conducting path in
are compared with the entries of the leakage and another.
weak fault tables to determine which leakage and weak ◼ The two components must be analyzed together in order to

faults are tested. obtain correct results.

◼ All normal and weak conducting paths associated with a
◼ If a vector tests even one new leakage/weak fault,
it is selected for measurement. weak fault must exist in a single component.
◼ This is guaranteed when all inputs of a component type only
drive gates of transistors in the component, and outputs of
different components do not simultaneously drive the same
node.

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Current Limit Setting IDDQ Built-In Current Testing

◼ Production IDDQ current testing needs a pass/fail value for ◼ Built-in current testing (BIC) alleviates need for special
the current limit, and it is difficult to pick a correct value. purpose testing hardware and increases testing rate.
◼ One should evaluate test data from representative circuits ◼ BIC uses current sensors to monitor the quiescent current in
and characterize IDDQ current using every vector from a the power lines of the device under-test.
functional vector set and a slow, precision measurement ◼ In Figure BIC sensor has a voltage drop device and a
unit on a tester. voltage comparator.
◼ At the end of each clock, device compares
the virtual ground voltage with the Vref,
chosen so that Vgnd < Vref for good circuits
and Vgnd > Vref for bad ones.

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IDDQ Built-In Current Testing Delta IDDQ Testing

◼ Voltage drops across the voltage drop device must be small, ◼ Uses the derivative IDDQ of at test vector i as a current
even in defective circuits with shorts. signature
◼ During probe or package testing, BIC can detect permanent
defects, regardless of whether vectors are generated on or
off-chip.
◼ IC must be partitioned into functional units, each with a
◼ Excellent for diagnosis, and can greatly improve
single BIC sensor.
the resolution of IDDQ testing.
◼ If functional units are too large, the combined leakage
◼ Eliminates chip-to-chip and wafer-to-wafer variations
currents may erroneously trigger the BIC sensor.
in current measurements, which may be larger than
◼ Minimize the number of BIC sensors in the IC, to minimize variations in vector-to-vector measurements.
test circuit area.

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Limitations of IDDQTesting Summary

◼ IDDQ testing has been highly useful in detecting bridging ◼ IDDQ tests improve reliability, find defects causing:
faults, which are hard to detect using voltage testing.
▪ Delay, bridging, weak faults
◼ Sub-micron technologies have increased leakage currents:
▪ Chips damaged by electro-static discharge
▪ Transistor sub-threshold conduction
▪ Harder to find IDDQ threshold separating good and bad chips ◼ No natural breakpoint for current threshold
◼ IDDQ testing detects passive defects (involving non-switching ▪ Get continuous distribution – bimodal would be better
circuit nodes) and active defects (involving switching nodes). ◼ Conclusion: now need stuck-fault, IDDQ, and delay fault
◼ IDDQ tests work: testing combined.
▪ When average defect-induced current greater than average
good IC current
◼ Still uncertain whether IDDQ tests will remain useful as chip
▪ Small variation in IDDQ over test sequence and between chips feature sizes shrink further.
◼ IC technology scaling makes these two conditions less likely.

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956