Arab Academy for Science and Technology & Maritime Transport College of Engineering & Technology

Electronics and Communication Engineering Department

7 th term Electronics and Communications Engineering
Lecturer: Head of Department Electronics and Communications: Dr. Hesham Hamdy
TA: Eng. Mayar Magdy EC432 MICROELECTRONIC CIRCUITS

Design Single Stage Operational Amplifier

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Contents
Objective.......................................................................................................................................................2
1. MOSFET’s Charactersitics.......................................................................................................................2
1.1 Why?...............................................................................................................................................2
1.2 N-MOS test bench circuit................................................................................................................2
2. Single Stage Operational Amplifier........................................................................................................13
2.1 Introduction to Single Stage Operational Amplifier.....................................................................13
2.2 What is a Single Stage Amplifier...................................................................................................13
2.3 What are the aspects that we have?............................................................................................13
2.4.......................................................................Design Methodology we will use
13
3.4.1 Performance metrics of interest....................................................................................................13
3.4.2Why gm/Id Methodology?.............................................................................................................14
2.5 Start with the main steps to design Single Stage Amplifier.........................................................14
2.6 Calculate the following.................................................................................................................16
3.6.1 Create a Symbol for the Differential Amplifier..............................................................................16
3.6.2 Create testbench schematic..........................................................................................................16
3.6.3 OP simulation.................................................................................................................................17
3.6.4 Diff small signal ccs........................................................................................................................17

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Objective
The primary goals in designing a Single Stage Operational Amplifier include
optimizing parameters such as voltage gain and bandwidth, matching input and
output impedances, minimizing power consumption, enhancing slew rate for faster
response, reducing noise, ensuring a high Common-Mode Rejection Ratio
(CMRR), maintaining temperature stability, and addressing the impact of process
variations. The robustness of the design to different conditions is crucial, and
achieving precision and linearity is essential for accurate signal processing. In
designing a Current Mirror, precision and linearity are key objectives to accurately
replicate current across connected branches.
1. MOSFET’s Charactersitics
1.1 Why?
Utilizing MOSFETs as the active devices, the single-stage operational amplifier exhibits unique
characteristics. The MOSFETs, configured in common-source or common-gate arrangements, play a
pivotal role in achieving voltage gain and overall signal amplification. Careful consideration of biasing,
load resistance, and feedback networks is essential to tailor the amplifier's performance to specific
requirements. Single Stage Operational Amplifiers find applications in scenarios where moderate
gain and simplified design are sufficient. These amplifiers are commonly employed in audio
amplification, sensor interfaces, and other circuits where a compact and energy-efficient solution is
desirable.

1.2 N-MOS test bench circuit

Figure 1: Schematic of N-MOS

i. We have Variables (length, voltage between gate and source [VGS], voltage
between drain and source [VDS] and width of mosfet test bench) and add
these variables in Design Variables of ADE Explorer window.

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 ii. Select dc analysis with save dc operating points and sweep VGS from 0 to
0.5

iii. Run dc analysis without selectting any outputs.

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iv. click on tools >> result browser << Calculator

v. In Calculator << there are 3 windows :-

- first window type of the signal which I need to be selected in schematic
to be plotted
 OS (Select Mosfet parameters) [ gm, id, gds, vsat, vgs,
vth]
 Var (Select width of Mosfet) [W]

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vi. In Calculator << Second window << Stack that record function<< to record
press enter after selection.

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vii. third window << Function Panel << Selected Wavevswave

viii. create your needed final expression to form curves below:-

[Curve 1 (gm/gds vs gm/id)
Curve 2 (id/w vs gm/id)
Curve 3 (vgs vs gm/id)
Curve 4 (vth vs gm/id)
Curve 5 (vdsat vs gm/id)]

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ix. Select your required expression on x &y -axis

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  Run and record your curves
 Record your output steps and results in
assignment template.

x. Using same steps for other curves then record your results on
template assignment.
xi. Repeat same for P-MOS device with this test bench circuit.

Figure 2: Schematic of P-MOS

 Record your output steps and results in assignment

template.

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2. Single Stage Operational Amplifier
3.1 Introduction to Single Stage Operational Amplifier
Operational amplifiers, or op-amps, stand as fundamental building blocks in
electronic circuits, facilitating signal amplification, filtering, and a myriad of
analog signal processing tasks. Among the diverse designs of operational
amplifiers, the Single Stage Operational Amplifier using MOSFETs represents a
concise and efficient solution for certain applications. The Single Stage
Operational Amplifier serves as a crucial component in analog circuitry, offering
amplification within a single amplifying stage. Unlike more complex multi-stage
designs, the single-stage variant provides simplicity while maintaining essential
amplification capabilities. This design is particularly advantageous in applications
where a compact, low- power, and cost-effective solution is paramount.
3.2 What is a Single Stage Amplifier
An electronic circuit is said to be a single-stage amplifier if it consists of a single
transistor with proper bias and additional components based on the requirement
that will provide an output, which is then an amplified version of any input
quantity like the voltage, current, and power. That means Transistor is the main
component in single-stage Amplifiers.

𝑉𝐷𝐷
3.3 What are the aspects that we have?
1.2 V

(𝑉𝑂𝐶𝑀 )
CM output Level 0.5 V

Differential gain (𝐴𝑣) 5

Bias Current (𝐼𝐷)
𝜇𝐴
20

3.4 Design Methodology we will use

Traditional analog design methodologies generally require iteration, the "Square
Law" design equations are inaccurate for submicron devices and difficult to get an
optimum power. But this methodology "gm/Id technique" is intended for low-
power analog circuits where the weak as well as moderate inversion regions are
often used because they provide a good compromise between speed and power
consumption. The gm/ID ratio indeed is a universal characteristic of all transistors
formed by the same process. MOS transistors are either in strong inversion or in
weak inversion. Mainstream methods generally assume strong inversion and use
the transistor gate voltage overdrive (VOV) as the key parameter.
3.4.1 Performance metrics of interest
1. Transconductance efficiency (Gm/Id).
2. Transit frequency (ft = gm/cgg).

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 3. Intrinsic gain (gm/gds).
3.4.2 Why gm/Id Methodology?
1. Available for low power designs.
2. Gm, id, L, and w of input MOSFET pair can be found more
systematically at specified power and speed performance.
3. Use gm/id because it is difficult to model with Vov when using
MOSFET in a weak inversion area.
3.5 Start with the main steps to design Single Stage Amplifier
 We want to design a differential amplifier with the specifications below.
Note that the bias current is split between two transistors; each transistor
gets ID=20µA.
By using UMC 65nm process, design an amplifier given in Fig. 1 for take the
supply voltage VDD=1.2 V.
 Using values that output from previous curves of P-MOS characteristics
start with below steps before design.
IBias=40µA.
VoCM=0.5V.

= 5.64927, 𝑊 = 3.54µm
ID=20µA.
𝑖𝑑
𝑊
0.5
20µ
assume ro=6RD, gds=1/ ro, assume RD>> ro RD=
𝐴𝑉 ≈ 𝑔𝑚(𝑟𝑜‖𝑅𝐷) 𝐴𝑉 ≈ 𝑔𝑚𝑅𝐷 5 ≈ 𝑔𝑚25𝐾𝑔𝑚 = 200µA/V
=25KΩ

𝑔𝑚
≥ 10
𝐼𝐷
𝑔𝑑 = 6.67µA/V , ≥ 30, L=280nm
𝑔𝑚
𝑠
𝑔𝑑𝑠
CMMR=33dB, 𝐴𝑣𝑑 = 14𝑑𝐵
CMMR = 𝐴𝑣𝑑 - 𝐴𝑣𝑐𝑚
CMMR = 2𝑔𝑚𝑅𝑆𝑆

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 Figure 5: Single Stage amplifier circuit.

Figure 6: The Schematic for a Single Stage Amplifier.

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3.6 Calculate the following

3.6.1 Create a Symbol for the Differential Amplifier

Figure 7: The Symbol for a Single Stage Amplifier.

3.6.2 Create testbench schematic

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 Figure 8: The Testbench for a Single Stage Amplifier.

3.6.3 OP simulation
 The schematic of the diff Amp with DC Operating points is clearly
annotated: id, vgs, vds, vth, vdsat, gm, gds, gmb, region.
 Check that all transistors operate in saturation.

 Record your output steps and results in assignment

template.

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 Use AC magnitude = 1 for the 𝑉1 source (and AC magnitude = 0 for the
3.6.4 Diff small signal ccs

𝑉2 source).
 Run AC analysis (1Hz:2GHz, logarithmic, 10 points/decade).

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 Record your output steps and results in assignment
template.

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