UNIT – IV

F E T effect Transistor (FET)

A field effect transistor is a uni – Polar device. The current conduction

is due to majority carriers only. FET is a voltage controlled device i.e. the
output current is controlled by the electric field applied at the control
terminal (Gate). Hence the name FET. FET is a three terminal device.
They are Gate, source and drain.
Based on the construction, the FET can be classified into two types.
1. Junction FET (JFET) 2.Insulated gate FET (IFET) or Metal
oxide semiconductor FET(MOSFET).
Depending upon the majority carriers, JFET can be classified into
two types. 1. N-channel JFET 2.P-channel JFET.
N-channel JFET construction:

S D
p

(a) JFET
It consists of an N – type silicon semiconductor bar. Two ohmic
contracts are attracted at the two ends of the bar. One acts as a source and
other acts as a Drain. Two heavily doped P – type silicon regions are
diffused on both sides of the N – type bar by which PN Junctions are
formed. These layers are joined together and called Gate “G”. The region
(sourceto Drain) of the N – type bar between the depletion regions is called
the channel. The majority carriers move from source to drain through this
channel when voltage is applied between source and drain.
Symbol:

N – Channel JFET P – Channel JFET

D D
G G

S S

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 Operation of N – Channel JFET:
In the operation of JFET, Gate – Source Junction should be reverse biased
and + ve voltageshould be applied to the Drain terminal as shown in below
figure (a).
VGG VGG
+ - + -

P p
D S +1V +3 D
S
+2V
p

-+ - +
VDD 6V
Figure (a) figure (b)

When Vgs = 0 and VDS is increased from zero:

When no voltage is applied to the Gate, if we apply the positive

voltage to the Drain w.r.t source, the electrons flow through the channel
from source to Drain. Hence current ID flows from drain to source. The
current ID depends on the following factors.

(1) The number of electrons available in the channel i.e., the

conductivity of thechannel.
(2) The length of the channel.
(3) The cross – sectional area A of the channel.
(4) The applied voltages VDS & Vgs
VDS V L
ID =  A DS ( R )
R L A

When R → resistance of the channel.

A → area of the cross – section.
L → length of channel.
VDS → Drain to source voltage.

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 Whenever we apply the voltage between Source to Drain of the FET,
the channel acts as a resistor and the potential distribution is a gradual increase of
+ve voltage along the channel from source to drain as shown above figure (b).
Hence the reverse voltage across the PN Junctions increases and hence the
thickness of the depletion regions also increases. Thus the channel is wedge shaped
as in figure (b).
Pinch – off region
Break down region

ID
Ohmic region
Vgs = 0
Vgs =- 1v
Vgs = -2v
IDSS Vgs =- 3v

VP VBO VDS
(C) Drain characteristics.

As VDS is increased from zero, the cross – sectional area of the channel will
be reduced. At a certain value VP of VDS, the cross – sectional area will minimum.
At this voltage, the channel is said to be pinched off and the drain voltage VP is
called the pinch – off voltage.

Drain characteristics:
It is the plot of source to drain voltage ‘VDS’ to the Drain current ID for a
constant gate to source voltage ‘Vgs’.
As VDS is increased from zero, ID increases. The region from VDS = 0 to
VDS =VP, the current ID increases with V DS. This region is called ohmic region.
During this region FET is used as a voltage variable resistor (VVR) or voltage
dependent resistor (VDR).
When VDS = VP, the channel width will minimum. Thus the channel is
pinched off. Hence the drain current ‘ID’ reaches maximum. When VDS is
increased beyond V P, the pinch – off (saturation0 region increases). Hence there is
no further increase of ID. When VDS = VBO (Breakdown voltage) avalanche
Breakdown take place in the channel. Then ID increases sharply. This region is
called Breakdown region. In this region FET is used as a constant voltage
amplifier.

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 If we apply the – ve voltage to the gate, the depletion layer increases in the
channel. Hence the Drain current ID decreases i.e., the curve ID verses VDS shifted
downward and also pinch off and Breakdown voltages (VP & VBO) are decreases as
shown in figure (c).
Transfer Characteristics:

It is the plot of “vgs” to “ID” for constant ‘VDS’.

ID

IDSS

VDS =4v IDSS

VDS = 2v
VSS(off)

- Vgs Vp VP
0
Fig (d)
If we maintained the constant VDS, the drain current IDSS flows through
channel from Drain to source. The gate voltage Vgs is decreased from zero, the
drain ID reduces. At certain voltage of Vgs the drain current ID reduced to zero. This
voltage is called “Vgs” (off) or pinch – off voltage “VP”. In these characteristics the
shape of the curve is a parabola.
So, the Drain current ID is given as
 V 2
I D  IDSS 1 gs
 ................ (1)

 VP 

Where 
IDSS = Saturated Drain current when Vgs = 0 and VP = Pinch off voltage.

V gs 
2

ID = IDSS 1   When VP = Vgs (off).
 V off 
 gs 

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Transconductance (gm):
I
gm  VD , VDS constant.
gs

From equation ........... (1)

 Vgs 
1    - ----------------- (2)
 VP 

Differentiate equation (1) w.r.t Vgs we get

ID 2IDSS  Vgs 

  1 V  , then
Vgs VP P 

2IDSS  Vgs 
gm   1  V  ---------------------- (3) ( ∂ ID / ∂ Vgs = gm)
V
P  P 

Put equation (2) in (3) we get

2IDSS  ID
gm  
VP

ID IDSS
gm
VP

If Vgs = 0, from equation ----------(3)

2IDSS
gm    gmo , then
VP
 V 
 g m  g mo 1  


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Advantages of FET over BJT:
1) FET is a unipolar device; conduction is due to majority carriers
only. So it is easy toOperate.
2) If offers high input impedance because input Junction is always reverse
bias.
3) It is less noise than BJT
4) Simpler to fabricate
5) It occupies less space. So it is used in IC‘s design.

Disadvantages:
1) Small gain – Breakdown product.
2) Low voltage gain.
3) High cost.

Insulated Gate FET (or) Metal oxide semiconductor FET (MOS FET)
In this FET, Gate is insulated by insulating material Si O2. That’s why it’s
named as IGFET. It is also called as MOSFET because in this FET Gate is Metal
type and it is insulatedby Si O2 material.
Depends on the construction “MOSFET” can be classified into two types.
They are
1) Enhancement MOSFET.
2) Depletion MOSFET.
Depends upon the majority carriers Enhancement MOSFET can be divided into
two.
They are
(a) N – type Enhancement MOSFET
(b) P – type Enhancement MOSFET

N –type Enhancement MOSFET:

Construction:

N – Channel Enhancement MOSFET consists of a lightly doped P – type

substrate in which two heavily doped N – regions are diffused. One acts as a source
and second acts a drain and separated by 1 mm distance. A Si O2 layer of thickness
10-6m is deposited on surface of the substrate. This layer (Si O2) acts as a insulating
layer. An aluminum (Al) is deposited over the surface of Silicon diode layer (Si
O2) and it acts as a Gate. In this, Gate (Al), SiO 2 layer and substrate acts a parallel
plate capacitor.

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 G
S D Symbol
Al D
Si O2
N+ N+ G

P – type Substrate.
S

(a) (b)

Working & Characteristics:

If no voltage applied to the gate (i.e., Vgs = open) and if we apply the voltage
between source and drain ‘VDS’, no current (ID) flows through the FET because
there is no channel between source and Drain. Hence this FET acts as a OFF
switch. If voltage is applied to the gate, gate, SiO2 layer, Substrate acts as a parallel
plate capacitor. Hence +ve charges are inducedin the “Al” material. These charges
will induce the “- ve” charges in the near end of the Si O2 layer and these “-ve”
charges will induces the “+ve “charges in the far end of the Si O2 layer as shown in
fig (c). Hence these +ve charges attracts.
The minority carrier in the P – pe Substrate. So, inversion layer will form between source
and Drain.
This layer acts as a channel between Source and drain. Hence current ID flows through the
FET.
If gate voltage is increased, the current flows through the FET will enhanced.
i.e., The gate Voltage enhances the current flows through FET. That’s why it’s named as
Enhanced MOSFET. - +
G
S D
++++ Al +++

++++++++
N+ - - - - -- -- - - - N+

Induced channel

P – Type Substrate.

- +
VDS
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Drain characteristics:
ID

It is the plot of drain to source voltage

+ 5v “VDS” to drain current “ID” and gate
Voltage “Vgs” is constant.
+4v
+3v
Vgs =+ 2v
Vgs = +1v

VDS

When Vgs = 0, and the Drain D at a position w.r.t to the source, the drain
current “ID” will be zero because there is no continuous channel between source
and Drain. If the gate voltage is made positive, negative change consisting of
electrons is induced in the channel through Si O2 of gate – channel capacitor. The
induction of the negative charge causes Enhancement of mobile electrons in the
channel. Thus a inversion layer is produced between source and drain. Hence Drain
current increases. When VDS is increased ID increases and it becomes constant at a
certain value of VDS, called the pinch off voltage. The drain current “ID” gets
saturated beyond the pinch – off voltage.

The curve of “ID” verses Vgs for constant VDS is called the transfer characteristics
As shown in fig (b)

ID
-

VDSS
VDS = 2v

Vgs Vgs (off)

fig (b)

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Depletion MOSFET:

Diffused channel

S G D S G(-) D(+)

Si O2
Al _ _Al _ _ _ _
+ +++++++++++

n+ n+ n+ n +++++++++ n+

P (Substrate) P (Substrate)

(a) (b)
The construction of an N – Channel depletion MOSFET is shown in fig (a) in which
an N – Channel is diffused between the source and Drain. So, the drain current ID
flows fro zero gate – to – source voltage Vgs = 0.
The circuit symbols for an N – Channel MOSFET as shown in below figure (a) , (b) and (c)

D D D

Substrate.
G1 G2 G1 G2 G1 G2

S S S

2. (a) (b) (c)

If Vgs = 0, drain D at a positive voltage w.r.t the Source, the electrons flow through the N-
Channel from source to Drain. Thus, the current ID flows through the channel from Drain
to source. If the gate voltage is made negative, the holes are induced in the channel
through Si O2 layer as shown above (b).
The induction of the holes causes depletion of mobile electrons in the channel.
Thus, shape of the channel depends on V gs and VDS.

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 Hence the channel will be wedge shaped. When VDS is increased, ID
becomes constant at a certain value of VDS, called the pinch – off voltage. If Vgs is
increased, the induced holes in the channel increase, hence the drain current ID will
decrease.
The characteristics of depletion MOSFET as shown in below figure (1) & (2)

ID ID

+2v

+1v VDSS
Vgs =0
1v

2v - Vgs Vgs (off) Vgs

(1) Drain characteristics (2) Transfer characteristics.

The depletion MOSFET can be operated with both +ve and –ve gate voltages.
So, it is also called as dual mode MOSFET.

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