Journal of King Saud University – Computer and Information Sciences 34 (2022) 5578–5586

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Journal of King Saud University –

Computer and Information Sciences
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Ultra low power design of multi-valued logic circuit for binary interfaces
Mansi Jhamb, Ratnesh Mohan ⇑
USIC&T, GGSIPU, New Delhi, India

a r t i c l e i n f o a b s t r a c t

Article history: From the dawn of the computer age, man has mass produced binary components for computers, due to
Received 10 July 2020 which ternary or higher radix computers are not yet commercially used. It has been proved that ternary
Revised 17 January 2021 logic can be more efficient than binary logic and there are many devices in development that operate on
Accepted 17 January 2021
more than two internal states. Therefore an efficient method to produce multi-valued logic on the basis of
Available online 4 February 2021
binary input provided is needed. In this article, an effective, simple, flexible, and low power consumption
implementation has been proposed that can convert any binary number to a number of chosen radix. The
Keywords:
proposed design is implemented in 32 nm TSMC CMOS. The proposed design is then evaluated in power/
Multi-valued logic
Complementary meta-oxide-semiconductor
delay space and its performances are compared with the latest state of art designs. The proposed circuit
Dynamic voltage supply exhibits power saving up to 92% over previous models.
Binary to multi-valued converter Ó 2021 The Authors. Published by Elsevier B.V. on behalf of King Saud University. This is an open access
article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction image processing (Abiri et al., 2018), and microelectronics (Gaudet,

2016; Jhamb et al., 2017), data compression, and potential in cache
The primary constraint in binary logic is the existence of only design (Jhamb et al., 2017). Ternary logic systems themselves have
two states (0,1) which leads to introducing more input bits in order vast applications, the effectiveness of ternary storage elements
to implement complicated functions which leads to enormous chip (Dhande et al., 2014) is unparalleled. Ternary logic is also used in
size and power consumption. Multi-valued logic (MVL), which top EDA tools to minimize binary operations and can also be
operates on degree of truth rather than simple true and false applied in artificial intelligence and robotics. Ternary logic is also
(Miller and Thornton, 2007), provides us NNx possible logic func- implemented in molecular electronics (Tirgar Fakheri et al.,
tions (N is the radix and x give input bit(s)) over the traditional 2020), all of this reduces circuit size and complexity. Many tech-
binary system which provides us only 22x possible logic functions niques have been developed for the synthesis of MVL circuits
(x gives the input bit(s)). Researchers are working on MVL from a (Current, 1994), particularly in ternary logic (Balla and Antoniou,
long time as its introduction to our circuits would change the very 1984). Some of these ways involve changing transistors structure
essence of technology (Hurst, 1984; Smith, 1981). It has been com- to vary threshold at different gates (Raghavan and Bhaaskaran,
pared with binary IC designs (Etiemble and Israel, 1988), and its 2017). Other techniques involve quantum dot (Karmakar, 2019),
benefits are incredible. It has been proved that natural base etc. There has been great development in quaternary circuit design
(e = 2.718) should be the most efficient radix for operation, making (Freitas and Current, 1983; Yasuda et al., 1986), combinational cir-
a huge demand for ternary logic, as it is the closest feasible base cuits for radix 4 have also been made already (Patel and
near natural base. MVL has many developing applications like in Gurumurthy, 2009). A binary to quaternary converter operating
nano scale devices that operate at base five (Fresch et al., 2018), on low power will thus be very useful. In this paper a flexible, sim-
quantum computation (Muthukrishnan and Stroud, 2000), reliabil- ple, ultra power saving implementation built on 32 nm MOSFET
ity analysis of multi-state system (Zaitseva and Levashenko, 2017), technology, has been proposed. The proposed design, termed as
Uma circuit, is used to build the proposed converter design which
can effectively convert multi digit binary number into number of
⇑ Corresponding author. chosen radix (greater than 2). With this converter design, binary
E-mail address: [email protected] (R. Mohan). input can be used to operate MVL circuits.
Peer review under responsibility of King Saud University. Section 2 presents some introduced terms that are used in the
paper. Section 3 presents the working of the proposed Uma circuit.
Section 4 proposes a theorem for analysis of the proposed design.
Section 5 focuses on constructing binary to MVL converter using
Production and hosting by Elsevier Uma circuit. Section 6 suggests alternative approaches for

https://doi.org/10.1016/j.jksuci.2021.01.010
1319-1578/Ó 2021 The Authors. Published by Elsevier B.V. on behalf of King Saud University.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
M. Jhamb and R. Mohan Journal of King Saud University – Computer and Information Sciences 34 (2022) 5578–5586

Table 1 Table 3
List of abbreviations used. URF and RF form of MVL.

Serial Number Abbreviation Full Form Original MVL form RF URF

1. MVL Multi-valued logic 0 0 0
2. DPL Double pass-transistor logic 1 1 0
3. URF Unit reduced form 2 1 1
4. RF Reduced form 3 1 2
5. DSR Dynamic supply route 4 1 3
6. BTT Binary to ternary
7. BTQ Binary to quaternary
9. LSB Least significant bit
10. MSB Most significant bit ply to that logic gate is fluctuated in a predetermined pattern to
obtain the desired output, this way the gate would carry out binary
operation at that instant but collective output would be MVL, as
implementing binary to MVL conversion. In Section 7 results are magnitude of true value of output is equal to the supply given to
discussed and compared with the state of the art design, for binary that logic gate at that moment.
to ternary conversion (Saha and Pal, 2018; Jaber et al., 2019; The proposed Uma Circuit, Fig. 1, harnesses the same idea but
Shahangian et al., 2019) and Section 8 concludes the article. Table 1 with configurations to make things smoother and to achieve more
and Table 2 summarize list of abbreviation and notations respec- complex operations. The function of the different sections in the
tively, that are used through out the article. Uma circuit is explained below, and shall be explained with refer-
ence to the proposed 2 bits BTT (binary to ternary) converter in
Fig. 2.
2. Overview of introduced MVL terms
3.1. Mainframe
2.1. Reduced form (RF) of MVL
The mainframe provides input to the activated gate. It operates
Denoting different degree of truth values as ‘1’. This form basi-
on binary logic and has a Boolean expression. In other words, it
cally determines if the output is true or not, hence all degree of
provides a basic ‘frame’ of the output Nth wave, that tells us at what
true values is treated the same. Table 3 gives example of RF values
point, a true value has to be produced in the needed Nth wave and
of some MVL terms. As shown in the table, RF of logic ‘‘1”, ‘‘2”, ‘‘3”,
where zero is produced. As shown in Fig. 2, XOR gate serves as
etc. is the same, i.e., ‘‘1”.
mainframe.

2.2. Unit reduced form (URF) of MVL 3.2. Dynamic supply route (DSR)

Reducing ‘1’ from different degree of true values we acquire URF The dynamic supply route as the name suggests is the part of
of MVL. URF will be used to configure the power supply. Table 3 Uma circuit that provides the dynamic supply ‘Vds’ to the activated
gives example of URF values of some MVL terms. It is to be noted
that URF of logic ‘‘0” and ‘‘1” is taken as ‘‘0”.

2.3. Nth wave

A wave fluctuating between ‘N’ discrete voltage levels in time

domain. For example, output from a DC source will be termed as
1st wave. Output from a simple OR gate will be termed as 2nd wave.
Output from a Ternary NAND gate will be termed as 3rd wave.

3. Working of the proposed Uma circuit

Fig. 1. Fundamental layout of proposed design, i.e. Uma circuit.
The ideology used to produce higher logic is that certain binary
input is provided to a desired logic gate and at the same time, sup-

Table 2
List of notations used

Serial Notation Meaning

Number
1. Vds Dynamic supply provided to activated gate
2. ai ith input to Nth wave generator
3. Ai ith input to Uma circuit or BTMVL converter
4. Yi ith output bit
5. D Don’t care condition (K-map)
6. k Total number of input bits
7. x Total number of Uma circuit(s) in converter
8. z Total number of output bit(s)
9. y Maximum logic (state) of output MSB
10. fm Boolean functional definition of mainframe
11. fN Functional definition of Nth wave generator
12. fr Function definition of rth input to Nth wave
generator
Fig. 2. Schematic diagram for proposed 2 bits binary to ternary converter.

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gate. The dynamic supply is configured in such a way that at spec-

ified input, Vds is increased or decreased. This part of Uma circuit
consists of a pattern control which determines how Vds will vary
for the given input and magnitude control (a DC source) which
increases the output from pattern control and is always placed
directly after the pattern control. The Nth wave coming out of the
a DC source is Vds. As shown in Fig. 2, AND gate and a Dc source
(0.45 V) form DSR.

3.3. Activated gate

The last gate of the Uma Circuit which takes input from the
mainframe and the supply from the DSR. This is the place where
the varying supply generates the MVL terms. As shown in Fig. 2
the activated gate is a modified buffer.

3.4. Nth wave generator Fig. 4. Schematic diagram for proposed 3rd wave generator.

The proposed design forms a crucial part of binary to MVL con-

verters, when the output base is greater than 3, it forms a part of
Table 4
DSR. Although it uses an Uma circuit design, it is a mere generator Value of MVL terms in 3rd wave generator.
of Nth wave; it is not be confused with the converter itself as the
decimal value of input binary string is not equal to that of the out- Output value of MVL term (V)

put bit generated. The design is used for generating radix more 0 0
than ‘2’. The inverters in the mainframe are for impedance match- 1 a
2 a + value of logic ‘1’ of input a2
ing, they highly stabilize the circuit and ensure smooth output.
Figs. 3 and 4 are schematics of proposed Nth wave generator and
3rd wave generator, (which is the most basic form of Nth wave gen-
erator) respectively. Tables 4 and 5 provide voltage value of logic
Table 5
levels of 3rd wave generator and Nth wave generator and Table 6 Voltage value for MVL terms in Nth wave generator.
provides the truth table on the basis of which Nth wave generator
operates. From Table 6 it can be observed that for output of Nth
wave generator to be state ‘‘i”, a1,a2. . .ai
1 can be ‘‘1” or ‘‘0” (don’t
care), ai must be ‘‘1”, and ai+1, ai+2. . .aN
1 must be ‘‘0”. For example,
in Fig. 4 if input is (01)2 or (11)2, the output will be logic ‘‘2”.
Another example, assume an input of (10)2 in the BTT converter
in Fig. 2. Output of mainframe which is input of activated gate will
be ‘‘1” (0.45 V) and the output of DSR and supply to activated gate
will be ‘‘2” (0.9 V), so now the activated gate will increase the input
‘‘1” to higher logic, ‘‘2”(which is equal to binary input).

4. Proposed Uma’s MVL conversion theorem

4.1. Theorem

For any binary to MVL converter that employs Uma circuit(s),

the number of output bit(s) and the maximum number of Uma cir-
cuit(s) including the nested forms that are used to build the con-

Fig. 3. Schematic for proposed design of the Nth wave generator.

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Table 6 Number of Uma circuitðsÞ due to nesting ¼ ðz
1Þ  ðN
3Þ ð6Þ

Truth table for proposed Nth wave generator.
And at last, we must also analyze the most significant bit (MSB)
of the output string, as all the output bit(s) except the MSB show N
states whereas MSB may show N states or it may show states less
than N, affecting the total number of Uma circuits used for it. Let
total number of Uma circuits be ‘x’ and maximum state (maximum
logic level) of MSB be ‘y’ (where 16y6N).
Number of Uma circuitðsÞ for output MSB ¼ 1 þ ðy
2Þ ¼ y
1 ð7Þ
Therefore,
x ¼ ðz
1Þ þ ðz
1Þ  ðN
3Þ þ ðy
1Þ
¼ ðz
1Þ  ðN
2Þ þ ðy
1Þ ð8Þ
Now we must find the maximum state of the output MSB. For
MSB to exist in state y and base N its individual weight must be less
than or equal to the largest input term.

1  2k
1 þ . . . :: þ 1  21 þ 1  20
P y  Nz
1 þ 0  Nz
2 . . . :: þ 0  N 1 þ 0  N0 ð9Þ
Since the greatest integral value of y that satisfies the inequality
is desirable, simplification is done and then floor function (greatest
integer function) is used.

2k
1
y¼b c ð10Þ
verter, can be perfectly determined if the number of input bits and Nz
1
output radix is known. Through Eq. (4), (8) and (10) all the parameters can be deter-
mined as stated in the theorem. For example, Analysis for 4 bits
4.2. Proof binary to quaternary converter, using (4), output bits are 2. Using
(10) we can determine that MSB has 4 states (0,1,2 and 3) and with
To effectively represent all the input terms, represented by fixed (8) the number of Uma circuits are 4. All the details can be verified
number of bits, in radix ‘2’, as the output string in radix ‘N’, maxi- from Fig. 5.
mum possible value of output string must be greater or equal to
the maximum value of input term. If the number of input bits is 5. Proposed binary to MVL conversion
‘k’ and the output bit(s) ‘z’, then the following inequality in decimal
base has to hold: For Conversion of binary base to base N, for each output bit a
z
1 1 0 separate circuit must be configured. For some output bit Yi, let Vdsi,
ðN
1Þ  N þ . . . :: þ ðN
1Þ  N þ ðN
1Þ  N
RFi and URFi be its dynamic supply, RF and URF respectively. URF
k
1
P12 þ . . . :: þ 1  21 þ 1  20 ð1Þ and RF must be determined as per the output bit. A1, A2,. . .,Ak are
the input signals (k is the total number of input bits). The construc-
Summing up the geometric progressions and simplifying the tion can be carried out on the basis of characteristic functions and
terms on both sides: minimizing techniques like K-map, etc.
N z P 2k ð2Þ
5.1. Constructing mainframe
Taking logarithm and simplifying on both sides.
Mainframe implements a Boolean function of input signals that
z P k  log N 2 ð3Þ
produces RF of output.
Now, for an optimal solution z must be the least possible integer
f m ðA1 ; A2 ; . . . :; Ak Þ ¼ RF i of Y i ð11Þ
to satisfy the inequality, else we shall have output bit(s) that shall
always remain zero and thus be undesirable. Using ceiling function From Table 7 RF1 of Y1 is easily determined from definition of RF.
(also called least integer function) to determine the lowest integral Now we can easily acquire min-terms to implement K-map and
value of z that also satisfies the inequality in Eq. (3). design mainframe. Hence Boolean equation of mainframe for 2 bits
BTQ (binary to quaternary) converter is (‘m’ is collection of min-
z ¼ dk  log N 2e ð4Þ
terms);
Now in order to determine the total number of Uma circuit(s) X
f m ðA1 ; A2 Þ ¼ mð1; 2; 3Þ ¼ A1 þ A2 ð12Þ
used in a binary to MVL converter, we must analyze which parts
require Uma circuit(s). Analysis for most significant bit (MSB) of
output will be done separately. Firstly, each output bit uses one 5.2. Constructing DSR
Uma circuit unless the bit exists in binary state for any input term.

Number of Uma circuitðsÞ for indiv idual output bitðsÞ ¼ ðz
1Þ ð5Þ Construction of DSR will require an (N-1)th wave generator and
will involve configuring inputs to (N-1)th wave generator to produce
Secondly, in DSR Nth wave generator are used. For generation of URF.Leta1,a2. . .aN
2 betheinputsignalstothe(N-1)th wavegenerator.
radix N term, one (N-1)th wave generator is used. Each (N-1)th
wave generator uses ‘N-3’ Uma circuits, one is itself and the rest
f ðN
1Þth ða1 ; a2 ; . . . ; ar ; ::; aN
2 Þ ¼ URF i of Y i ð13Þ
are nested within.
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Fig. 5. Schematic diagram for proposed 4 bits binary to quaternary converter.

5.3. Constructing activated gate

Table 7
Truth table of proposed 2 bits BTQ converter.
An ordinary buffer is provided dynamic supply, Vds, from DSR
A1 A2 Y1 RF1 URF1 a1 a2
and input from Mainframe output. In order to save power Vds is
0 0 0 0 0 0 0 only provided in the second inverting part of the buffer and con-
0 1 1 1 0 0 0
stant supply is provided in the first inverting part, as in Fig. 2
1 0 2 1 1 1 0
1 1 3 1 2 D 1 and Fig. 5.

6. Alternate approaches
This function follows the truth table given in Table 6. As Eq. (13)
6.1. Special case of proposed Uma’s conversion theorem
is predefined we must configure inputs to Nth wave generator, i.e.,
ar where, ar is some input to the (N-1)th wave generator, where
In (3), sometimes left hand and right hand side become equal. In
16r6N-2, then
this case the right hand side is an integer, and hence ceiling func-
f r ðA1 ; A2 ; . . . :; Ak Þ ¼ ar ð14Þ tion used in (4) is not needed (though it would give the same
result). This equality condition in (3) exists only when conversions
From Table 7 URF1 of Y1 is easily determined from definition of are carried from base 2 to base which is a power of 2 (4, 8, 16, etc.).
URF and from Table 6 we can determine the corresponding a1 and Due to this equality, a 4 bits BTQ converter is made from two 2 bits
a2 values (‘d’ is collection of don’t care terms). BTQ converter, as in Fig. 5, a 6 bits binary to octonary converter
(base 8) is made from two 3 bits binary to octonary converter. This
f 3rd ða1 ; a2 Þ ¼ URF 1 of Y 1 ð15Þ
property reduces system complexity.
X X
f 1 ðA1 ; A2 Þ ¼ a1 ¼ mð2Þ þ dð3Þ ¼ A1 ð16Þ 6.2. Combining independent circuits

X
f 2 ðA1 ; A2 Þ ¼ a2 ¼ mð3Þ ¼ A1  A2 ð17Þ Each bit of the output (having MVL terms) has its own Uma cir-
cuit, these Uma circuits are not connected with each other, it has
The output from generator (URFi) when passed through the a been observed that very often they have same logic operations
DC source becomes Vdsi. (for example A + B can be present in two Uma circuits), hence
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one can perform the logic operation in one Uma circuit and share
the data with the other circuit as well. This greatly reduces transis-
tors used. This practice may lead to impedance mismatch; but with
buffer as the activated gate output is not affected.

6.3. Don’t care (D) for zero logic in URF

If the supply route gets complicated due to a large Boolean

expression one can use ‘don’t care’ condition for zero in the URF,
this technique will help in reducing the supply route size but will
provide unnecessary high supply to the final logic gate even when
it’s not needed.

6.4. Changing the structure of Nth wave generator

One can redesign the Nth wave generator rather than configur-
ing what input it receives, also the reason all inputs provided are
inverted is that the inverters helped in impedance matching and
inverted input make the overall truth table quite easy to generalize
and exploit, the inverters can be removed and a buffer can be intro-
duced as the activated gate similar to the converter circuits, this
will save transistors significantly if the conversion is to a high
radix.

6.5. Using the Nth wave generator as a converter

Just as we manipulated the 3rd wave generator to produce

desired output (Vds) in Fig. 5, similarly we can also manipulate
the input to the generator in such a way that the overall effect
mimics a converter. In some cases, this may save transistors.

6.6. Replacing the a DC source

The role of this DC source is that it adds a constant value to the

supply from the pattern control which gives URF as the output. URF
when added with the voltage from the a DC source becomes Vds. If
introducing multiple DC source causes inconvenience then one can Fig. 6. Input and output waveform for proposed 2 bits binary to ternary converter.
simply use a summing operational amplifier or any circuit setup
that adds two voltage values. If the a DC source or any similar
Table 8
replacement is not introduced then the activated gate will get no
Comparison between proposed binary to ternary converter and state of the art
supply when URF is ‘0’ which will distort the output when logic reference (Saha and Pal, 2018).
‘1’ has to be generated.
Saha and Pal (2018) Proposed design
Technology 180 nm CMOS 32 nm CMOS
7. Simulation and results Gate Logic DPL binary gates and Static combinational
ternary gates CMOS logic
The simulations have been carried out on 32 nm TSMC CMOS Power 270.42 lW 26.29 lW
using SPICE. Width and length ratio of CMOS was well tuned for Device Count 426 82
Delay 0.89 ns 0.13 ns
optimum performance. Detailed comparison has been carried out
Propagation delay from 25.43 ps 23 ps
with respect to state of art reference designs (Saha and Pal, ‘‘0” to ‘‘1”
2018; Jaber et al., 2019; Shahangian et al., 2019). Propagation delay from 31.20 ps 26 ps
‘‘1” to ‘‘2”
Propagation delay from 37.31 ps 48 ps
7.1. Case 1: binary to ternary converter
‘‘2” to ‘‘0”

The proposed circuit simulated is represented in Fig. 2. It was

constructed using the approach in Section 5. The output for this
circuit is presented in Fig. 6. The output was obtained at 25°C design uses 180 nm CMOS technology in its DPL (Double pass-
and at a bit rate of 0.2 billion bits per second with DC supply transistor logic) binary gates and uses ternary gates as well,
(Vdd) of 0.45 V. compared to 32 nm CMOS technology in basic binary gates (static
The proposed design is first compared to Saha and Pal (2018). combinational CMOS logic). In terms of power, device count and
Both circuits were simulated at temperature 25°C and input bit delay the proposed design clearly performs better by huge margin.
rate 0.33 billion bits per second, i.e., 0.33 GHz. In both designs logic The device count of proposed circuit includes 80 transistors and 2
symbols ‘‘0”, ‘‘1” and ‘‘2” are represented as 0 V, 0.9 V, 1.8 V. Both a DC sources. The delay (latency) in all the comparisons is calcu-
the circuit accept 3 bits binary string as input. The proposed design lated, as the difference of time at which input is 50% of its final
was powered by a DC supply (Vdd) of 0.9 V, with a DC source equal voltage and the time at which output reaches the same voltage.
to 0.9 V. The comparison is summarized in Table 8. The reference Time taken by circuit to reach required logic level after trigger from
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Table 9
Comparison between proposed binary to ternary converter and state of the art
reference (Jaber et al., 2019).

Jaber et al. (2019) Proposed design

Technology 180 nm CMOS 32 nm CMOS
Gate Logic Double pass- Static combinational
transistor logic CMOS logic
Power 349.9 lW 309.6 lW
Device Count 218 213
Propagation delay from 0.06 ns 0.028 ns
‘‘0” to ‘‘1”
Propagation delay from 0.07 ns 0.045 ns
‘‘1” to ‘‘2”
Propagation delay from 0.05 ns 0.055 ns
‘‘2” to ‘‘0”

input was also calculated and compared. This propagation delay in Fig. 7. Power consumption comparison of proposed 2 bits BTT converter and state
all three cases (from ‘‘0” to ‘‘1”, ‘‘1” to ‘‘2” and ‘‘2” to ‘‘0”) is nearly of the art reference (Shahangian et al., 2019) 2 bits BTT converter due to
temperature change.
the same for the reference and proposed circuits.
The proposed design is then compared to Jaber et al. (2019).
Both circuits are simulated at temperature 25°C and input bit rate
5 billion bits per second, i.e., 5 GHz. In both designs logic symbols
‘‘0”, ‘‘1” and ‘‘2” are represented as 0 V, 0.9 V, 1.8 V. Both the circuit
accept 4 bits binary string as input. The proposed design was pow-
ered by a DC supply (Vdd) of 0.9 V, with a DC source equal to 0.9 V.
The comparison is summarized in Table 9. Both reference design
(Saha and Pal, 2018; Jaber et al., 2019) employ the use of double
pass-transistor logic (DPL) to counter speed degradation, reduce
delay, and operate at high frequency under low supply. However,
DPL was not used in proposed design as due to the Dual rail system
of DPL, the interconnects are twice as much as a single rail system
which increases circuit complexity considerably for higher bits
input string (nearly twice as much as single rail system)
(Bernstein et al., 1999). Hence to operate at high frequency and
low supply 32 nm technology is used. The reference design
(Jaber et al., 2019), 4 bits BTT appears nearly the same as proposed Fig. 8. Power consumption comparison of proposed 2 bits BTT converter and state
design except in 2 distinct features, first as mentioned the type of of the art reference (Shahangian et al., 2019) 2 bits BTT converter due to load
technology and logic gate design. The second difference is based on capacitance change.

the design of overall circuit, the reference design has two circuits
for each bit of MVL output each computes one logic (‘‘1” or ‘‘2”)
et al. (2019). It can be observed that the proposed design provides
and then pass the bit to the output, whereas as the proposed
significant power saving in the commercial temperature range
design employs dynamic supply to a buffer which has two advan-
(0°C–70°C). Fig. 8 shows that power is nearly constant for load
tages, first is that the design can be easily extended to higher radix
capacitance change. The delay variation due to temperature is also
easily and second is that voltage loss is very low which doesn’t
reported in Fig. 9. It can be observed that delay reduces signifi-
appear is reference design (logic ‘‘2” is below 1.8 V).
cantly with increase in temperature (which is a known phe-
At last the proposed design is compared to Shahangian et al.
nomenon in low power supply circuits) but is still higher than
(2019), Both circuits are simulated at temperature 25°C and input
the reference design (See Fig. 10).
bit rate 0.2 billion bits per second, i.e., 0.2 GHz. In both designs
logic symbols ‘‘0”, ‘‘1” and ‘‘2” are represented as 0 V, 0.45 V,
0.9 V. The proposed circuit runs on supply of 0.45 V, with a DC 7.2. Case 2: binary to quaternary converter
source equal to 0.45 V. The reference design (Shahangian et al.,
2019) uses an entirely different technology, CNTFET. From the data As discussed in Section 3 and 5, a 2 bits BTQ converter was con-
in Table 10, proposed design is clearly better in power saving but structed and simulated at 25°C, bit rate 0.2 billion per second with
equally falls behind the reference design in delay. Power dissipa- supply of 0.3 V. As explained in Section 6.1, a 4 bit BTQ converter
tion due to change in temperature and load capacitance has been was made by using two 2 bits BTQ converter in parallel and the
reported in Figs. 7 and 8 and also compared with Shahangian waveform of the circuit is presented in Fig. 6. This design was

Table 10
Comparison between proposed binary to ternary converter and state of the art reference (Shahangian et al., 2019).

Shahangian et al. (2019) Proposed design Power compare

Technology CNTFET 32 nm CMOS
Parameters Power Delay Transistors Power Delay Transistors Saving
2 bits BTT 8.28 lW 10.02 ps 23 1.24 lW 408.1 ps 28 85.02%
3 bits BTT 37.16 lW 22.93 ps 80 2.93 lW 634.4 ps 80 92.1%
4 bits BTT 64.41 lW 46.95 ps 151 5.09 lW 965.1 ps 210 92.09%
6 bits BTT 172.09 lW 86.32 ps 392 25.61 lW 1382.2 ps 786 85.11%

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posed Uma circuit can effectively convert any binary number to a

number of desired base. The basic algorithm provided in the Sec-
tion 5 is very flexible and can be modified as needed or completely
altered by the techniques provided in the succeeding section. The
use of this implementation for binary to MVL conversion is shown
to be stable in commercial operating temperature range. Overall,
we can conclude that MVL string can be generated via supply fluc-
tuation and can be intelligently configured to work as a converter,
with power savings up to 92% over the state of art, hence ensuring
that the proposed converter using proposed Uma circuit is a poten-
tial candidate for ultra low power application and binary to MVL
conversion.

Declaration of Competing Interest

Fig. 9. Change in delay of proposed 2 bits BTT converter due to temperature change.
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared
to influence the work reported in this paper.

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