4 *******************************************************************************************************

** NCP/NCV1362 Inductor and Losses calculation for adapter

**
** ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// **
** Made by Yann Vaquette, email: [email protected] for reporting any issue
** Rev: 0.1 17/09/2020
** Modifications: Initial Version
** Rev 0.0: - Initial Release for NCP/NCV1362
** Rev 0.1: - DC input voltage version

*******************************************************************************************************
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HOW TO USE THE SPREADSHEET

This spreadsheet will calculate for you every parameters needed

to design a power supply using the NCP1362

Comment:
The zones underlined in pink need data from the user.
The zones underlined in yellow are calculation results
The zones underlined in red are controllers internal parameters and must not be changed !
------------------------------------------------------------------------------------------------

INPUT DATA

Minimum DC input voltage: VINmin  120V Maximum DC input voltage: VINmax  375V

Maximum output power: Pout  12W Output voltage: Vout  12V

Estimated efficiency: η  85% Output diode forward voltage: Vf  0.6V

Switching frequency at maximum output power, low line: Fsw  50kHz

External Capacitor between Drain & Source: CDS  0.100pF External Cap for valley adjust

MOSFET part number: FCU600N65S3R0

MOSFET breakdown voltage: BVdss  650V

Mosfet Coss @ VDS = Vo : COSS  10pF

Mosfet VDS = Vo @ which is measured Vo  400V

Mosfet Qg: Qg  11nC

MOSFET Rdson at Tj = 110 °C: Rdson110  1.0Ω (0.6 Ω max @ 25°C)

Output diode forward part number: ON Semiconductor NRVTSS5100E

Output diode forward voltage @ Tj = 125 °C: Vf0  0.2V
 Controller Parameters:
Note: For no clamp option please enters Fsw_max >>
Swiching Frequency Clamp: Fsw_max  500kHz
to the max freq of your design, otherwise enters 80
kHz, 110 kHz or 140 kHz value
Maximum peak current: VCSmax  0.8V

Frozen peak current in VCO mode: VCSmin  250mV

Frozen peak current in VCO mode: VCSmin2  65mV

Constant Current Voltage ref: Vref_CC  1.0V

Internal min dead time in VCO: DT_min  650ns

KcompCV  KcompCC  4

Minimal Fsw in VCO mode Fmin  1kHz Option 200 Hz or 1 kHz

Internal Comp Offset level VCompOffset  1.1V

Min Comp pin level at which VCompIPKmin  VCSmin KcompCV  VCompOffset  2.1 V
the peak current is frozen:
Min Comp pin level: VCompmin  0.2V

Max Comp pin level: VCompmax  VCSmax KcompCV  VCompOffset  4.3 V

Total Propagation delay time: tprop  150  ns

Internal Voltage reference Vref_CV1  2.5V

Vref_OVP  Vref_CV1  126 %  3.15 V

Vref_UVP  1.5V

μA
Transconductance gain: g m  200
V

Preliminary calculations:

Pout
Iout  Iout  1 A
Vout

Primary to secondary turn ratio calculation (Nps=Ns/Np)

MOSFET breakdown voltage: BVdss  650 V

Derating factor for the MOSFET breakdown voltage: α  90%

Leakage inductance ratio (k leak = Lleak / Lp ) k leak1  1.8% k leak2  2.0% k leak3  2.2%

Clamping diode recovery time overshoot: Vos  10V

VDSmax  BVdss α VDSmax  585 V

 2
4  1
Pout kc 
 
Pcond k c   Rdson110   
3 2
η  VINmin 
VINmin 
VDSmax  VINmax  Vos 
Pout k c
 
PRclp k c k leak  k leak 
η kc  1

k c_min  1.2 k c_max  4 nb_step  50

kc_max  kc_min
k c  k c_min k c_min   k c_max
nb_step

The losses caused by the clamping resistor are plotted below for different value
of kleak.

 
Pcond kc
2
PRclp  kc kleak1

PRclp  kc kleak2

PRclp  kc kleak3 1

0
1.2 1.5 1.8 2.1 2.4 2.7 3
kc

Clamping coefficient (k c = Vclamp / Vreflect): k c  1.9


k c Vout  Vf 
Npsmin  Npsmin  0.12
VDSmax  Vos  VINmax
Enter your value for Nps: Nps  0.124

New k c based on the turn ratio selection if different from the theoritical calulation:

VDSmax  Vos  VINmax

k c  Nps k c  1.968
Vout  Vf 
New VDS of the Power MOS based on the Nps turn ratio selection:

Vout  Vf  must be <

VDS   k c  Vos  VINmax VDS  585 V VDSmax  585 V
Nps

Vout  Vf 
Vclamp   kc Vclamp  200 V
Nps
Ipk and Lp calculation including the dead-time

Ipk 
2  Pout
 
1

Nps   π 2  Pout  COSS  CDS  Fsw
Vout  Vf  Ipk  0.525 A
η
 VINmin  η

2  Pout
Lp 
2 Lp  2.049  mH
Ipk  η Fsw

Enter your value for Lp: Lp  1.2 mH

Expected Leakage: k leak  1.8% Lleak  Lp  k leak Lleak  21.6 μH

New Ipk value based on Lp selection

2  Pout
Ipk  Ipk  0.686 A
Lp  η Fsw

VCSmax
RsenseCV  RsenseCV  1.166  Ω
Ipk

Lp  η Fsw Iout
Vref_CC_max  VCSmax 2  KcompCC Nps  1.157 V
VCSmax  0.8 V 2  Vout

2
KcompCC  4 Vref_CC  1.0V 2  Vout Vref_CC 1
Iout_min    0.747 A
2 Lp  η Fsw
 VCSmax 2  KcompCC Nps 

Rsense calculation for CC regulation:

Iout_CC  Iout  1 A
Maximum output current:
Iout_CC  Iout 1.10 Iout  10%

Vref_CC
Rsense_theo  Rsense_theo  0.916  Ω
2  KcompCC Nps Iout_CC

Enter the normalized value for Rsense: Rsense  Rsense_theo 99%  0.907 Ω

Rsense  0.907Ω

New Iout value based on the Rsense selection:

Vref_CC
Iout_new  Iout_new  1.111 A
2  KcompCC Nps Rsense
Auxiliary winding turn ratio

Desired value for VCC: VCC  8V

Forward Voltage of Aux diode Vf_aux  0.8V


Nps VCC  Vf_aux 
Naux  Naux  0.089
Vout  Vf0

Enter Naux value: Naux  0.089

ZCD resistor divider calculation:

Rupper Vs /
ZCD
Auxiliary

Rlower
CZCD

Naux
Max voltage on Aux winding 
Vaux  Vout  Vf0 
Nps
 Vaux  8.756 V

Constant time selection, must be

below 100 ns in order to keep a
τ  0.100μs
good accuracy on the CV
regualtion:

Arbitrary Selection of Rupper on Rupper  9.29kΩ

ZCD pin:

Vref_CV1
Rlower  Rupper Rlower  3.712  kΩ
 
Vaux  Vref_CV1

Rupper  Rlower
CZCD  τ CZCD  37.703 pF
Rupper  Rlower

Vref_CV1
M   0.4
Vaux  Vref_CV1

Rlower  4.3kΩ
Rlower components values selection:

Rupper  Rlower
CZCD   τ  34.02  pF
Rupper  Rlower

Czcd components values selection: CZCD  10pF

 Time constant verification

Rupper  Rlower
τ   CZCD τ  0.029  μs
Rupper  Rlower

Output votlage error based on the Rlower and Rupper selection:

Rlower
M   0.463
Rupper

M
Vref_CV1  Vaux
1M
Vout_Error  Vout_Error  10.825 %
Vref_CV1

Vout OVP & UVP protection level with resistor divider selection:

Vout_OVP 
Nps Rupper  Rlower


 Vref_OVP
 Vout_OVP  13.871 V
Naux Rlower

Vout_UVP 
Nps Rupper  Rlower


 Vref_UVP
 Vout_UVP  6.605 V
Naux Rlower

Primary and secondary rms current calculation

Ipk Lp
Tonmax  Tonmax  6.86 μs
VINmin

Dmax  Tonmax Fsw Dmax  34.3 %

1  Dmax
IpRMS  Ipk IpRMS  0.232 A
3
Ipk
Ips  Ips  5.532 A
Nps

1
IsRMS  Ips 
3

 1  Dmax  IsRMS  2.589 A

Dmax
IpriDC  Ipk IpriDC  0.118 A
2

2 2
IpriAC  IpRMS  IpriDC IpriAC  0.2 A

Output capacitor calculation

Vripple  Vout  1.5%

Vripple
RESR 
Ips RESR  0.033  Ω
 2 2
ICoutRMS  IsRMS  Iout
ICoutRMS  2.388 A

Enter Output capacitor selection:

Nichicon LF PLF1C471MDO1, 16 V, 470 µF Resr = 9 mOhm, Irms = 5.0 A
nbrCout  2 ICout  nbrCout 5 A  10 A

5 3 3
Cout  nbrCout 470  μF  940  μF RESR   10  Ω  2.5  10 Ω
nbrCout

Predicting the evolution of the switching frequency

Enter below the DC input voltage at which you want to see the frequency evolution (these
voltages will also be used for the losses calculations)

VINlow  120V VINhigh  375V

Fsw versus Pout at VINlow

5
1.3 10

110kHz
4
9.75 10

FswVLD
Fsw (Hz)

4
6.5 10
FswVLI

4
3.25 10

0
0 1 2 3 4 5 6 7 8 9 10 11 12
PoutVLD PoutVLI

Pout (W)

Valley versus Pout at VINLow

10

7
ValleyVLD
6
ValleyVLI 5

1
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI

Pout (W)
 Ipk versus Pout at VINlow

IpkVLD 0.4
Ipk (A)

IpkVLI
0.2

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI

Pout (W)

Comp versus Pout at VINlow

3
VComp (V)

V CompVLD

V CompVLI 2

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI

Pout (W)

Duty Ratio versus Pout at VINlow

5
tonVLD 1 10
Duty Ratio (%)

tdemagVLD

tonVLI 6
5 10
tdemagVLI

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLD PoutVLI PoutVLI

Pout (W)

RCD clamp calculation

Vclamp  200 V
 Leakage inductance considered for the RCD clamp k leak  1.8 %
calculation:

Lleak  Lp  k leak Lleak  21.6 μH


2  Vclamp Vclamp 
Vout  Vf 
Rclp 
 Nps  Rclp  77.434 kΩ
2
Ipk  Lleak Fsw

Enter Rclp selection: Rclp  136kΩ

Enter Voltage Ripple Percentage on Vclamp: Clamppkpk  50%

Vclamp
Cclp  Cclp  0.294  nF
Rclp Fsw Clamppkpk Vclamp

Peak Inverse Voltage of the clamp diode:

PIVDclp 
Vout  Vf   Vos PIVDclp  111.613 V
Nps

RCD clamp losses:

2
Vclamp
PClp  PClp  0.294 W
Rclp

Losses calculation: @ Low line input Voltage

Extracted max peak current @ low line from the curves


Ipk_low  max IpkVLD IpkVLI  Ipk_low  0.565 A

Extracted swiching frequency @ the max peak current point from the curves:

Fsw_low  FswVLD if Ipk_low = IpkVLD Fsw_low  82.004 kHz

0 0
FswVLI

last FswVLI  otherwise

Duty Ratio calculations:

Ipk_low Lp
DRlow   Fsw_low
VINmin DRlow  0.463

Transformer primary RMS current:

DRlow
IpRMS_low  Ipk_low IpRMS_low  0.222 A
3
Transformer secondary RMS current:

Ipk_low 1
IsRMS_low 
Nps

3

 1  DRlow  IsRMS_low  1.927 A

Output Capacitor RMS current:

2 2
ICoutRMS_low  IsRMS_low  Iout
ICoutRMS_low  1.647 A

Power loss in RCD clamp PClp  0.294 W

Power loss in sense resistor:

2
Psense  Rsense IpRMS_low Psense  0.045 W

Power loss in Cout

2
PCout  RESR ICoutRMS_low 3
PCout  6.783  10 W

* Power loss in MOSFET

Drain source resistance at Tj = 110°C: Rdson110  1 Ω

MOSFET COSS at Vds = V0 : COSS  10 pF

Condution losses:

 
PCOND IpRMS  IpRMS Rdson110
2

Switching losses
Switching losses due to the Power Mosfet only:
3
2
 Vout  Vf 
2
PSW1 VINDC Fsw    VINDC    COSS Vo Fsw
3  Nps 

Switching losses due to the extra capacitor that it could be placed in parallel with the Power
Mosfet:

2
 Vout  Vf 
1
PSW2 VINDC Fsw   CDS  VINDC    Fsw
2  Nps 
Switching total losses is the sum:

   
PSW VINDC Fsw  PSW1 VINDC Fsw  PSW2 VINDC Fsw  
 Due to the QR mode and thanks to the power mosfet losses graph it is possible to extract the
worst case conditions losses:

VINlow  120 V

MOSFET conduction and switching losses versus Pout at VINLow

3
0.05 1.5 10

3
0.04 1.2 10
Conduction losses (W)

Switching losses (W)

4
PcondVLD 0.03 9 10 PswVLD

PcondVLI PswVLI
4
0.02 6 10

4
0.01 3 10

0 0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI PoutVLD PoutVLI

Pout (W)

The following graph illustrates the sum of the switching losses and conduction losses versus the
output power and at different input voltages:

VINlow  120 V

Overall MOSFET losses versus Pout at VINLow

0.05

0.04
P Mos losses (W)

 PcondVLDPswVLD 0.03
 PcondVLIPswVLI 0.02

0.01

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI

Pout (W)

Thus worst case mosfet losses is extracted from the graphs above:

VINlow  120 V VINhigh  375 V

 
PMOS  max Pcond VLD  PswVLD Pcond VLI  PswVLI Pcond VHD  PswVHD Pcond VHI  PswVHI

PMOS  0.099 W

* Power loss in output diode

Peak inverse voltage :

PIVdiode  VINmax Nps  Vout  Vf PIVdiode  59.1 V

Output diode : NRVTSS5100E

Diode forward voltage at low current: Vf0  0.2 V @ 125°C

0.1V
Diode dynamic resistance: Rd   0.05 Ω
2A

2
PDiode  Vf0 Iout  Rd  IsRMS_low PDiode  0.386 W

* Power loss in Synchronous Rectification MOSFET if it is used instead of Schottky diode

Mosfet reference: NTMFS5C612NL from ONSEMI

Drain source resistance at Tj = 110°C: RSRdson110  0.00345Ω

MOSFET COSS at Vds = VSR_o : CSR_OSS  2953pF

VSR_o  25V

Maximum forward body diode: VSR_SD  0.66V

Estimated maximum duration of the body diode conduction: tBD_on  100ns

Condution losses:

Ipk  IpkVLD tdemag  tdemagVLD Fsw  FswVLD


 Ipk 1  2 
PSR_condVLD   

Nps 3
 
 tdemag Fsw  RSRdson110


Ipk  IpkVLI tdemag  tdemagVLI Fsw  FswVLI


 Ipk 1   2 
PSR_condVLI      tdemag Fsw  RSRdson110
 
Nps 3 
  

Ipk  IpkVHD tdemag  tdemagVHD Fsw  FswVHD


 Ipk 1  2 
PSR_condVHD   

Nps 3
 
 tdemag Fsw  RSRdson110

 Ipk  IpkVHI tdemag  tdemagVHI Fsw  FswVHI


 Ipk 1   2 
PSR_condVHI      tdemag Fsw  RSRdson110
 
Nps 3 
  

Switching losses

Thanks to the body diode of the sync power mosfet, the SR mosfet is turned on at almost
null voltage (Vf ~ 1.0 V) , thus the switching losses could be neglected.
However we could consider the losses due to the body diode conduction before the power
mosfet is turned on.

Body diode losses :

Ipk  IpkVLD Fsw  FswVLD

 

PSR_SDVLD   VSR_SD
Ipk
 tBD_on  Fsw
 Nps 
Ipk  IpkVLI Fsw  FswVLI
 

PSR_SDVLI   VSR_SD
Ipk
 tBD_on  Fsw
 Nps 
Ipk  IpkVHD Fsw  FswVHD
 

PSR_SDVHD   VSR_SD
Ipk
 tBD_on  Fsw
 Nps 
Ipk  IpkVHI Fsw  FswVHI
 

PSR_SDVHI   VSR_SD
Ipk
 tBD_on  Fsw
 Nps 

VINlow  120 V
 SR MOSFET losses versus Pout at VINLow
0.015 0.03

0.012 0.024
Conduction losses (W)

Switching losses (W)

3
P SR_condVLD 9 10 0.018 P SR_SDVLD

P SR_condVLI P SR_SDVLI
3
6 10 0.012

3 3
3 10 6 10

0 0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI PoutVLD PoutVLI

Pout (W)

The following graph illustrates the sum of the switching losses and conduction losses versus the
output power and at different input voltages:

VINlow  120 V

Overall SR MOSFET losses versus Pout at VINLow

0.04

0.032
P Mos losses (W)

 PSR_condVLDPSR_SDVLD 0.024

 PSR_condVLIPSR_SDVLI 0.016

3
8 10

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVLD PoutVLI

Pout (W)

Thus worst case SR mosfet losses is extracted from the graphs above:


PSR_MOS  max PSR_condVLD  PSR_SDVLD PSR_condVLI  PSR_SDVLI PSR_condVHD  PSR_SDVHD PSR_con

PSR_MOS  0.042 W

* Compensating the power supply

 Vout
Rload 
Iout

Rload

H0 VINDC    Vout 
H0 ( 120V)  5.104
2  KcompCV Nps Rsense  2   1
 Nps VINDC 
1
sz1 
RESR Cout

Rload 1

sz2 VINDC  2

Vout  Vout 
Nps  Lp 1  
Nps VINDC Nps VINDC
 

Vout
2 1
1 Nps VINDC

sp1 VINDC Rload Cout

Vout
1
Nps VINDC

Power stage without ZOH:

1  s  1  s 
 sz1   sz2 VINDC 
H1  s VINDC  H0  VINDC 
  
1  s 
 sp1 VINDC 
 
Transformer Gain:
Naux
KT0 
Nps
 0.718  
20 log KT0  2.881

Power stage on Aux winding without ZOH:

  
H2 s VINDC  H1 s VINDC  KT0 

Power Stage with ZOH:

End of Demagnetization Transfer function:

Rlower
KD0   0.31641
Rlower  Rupper
 Rlower  Rupper
τ1  C  29.394 ns
Rlower  Rupper ZCD

1
KD( s)  KD0
1  s 2  π τ1

Internal Sample & Hold (ZOH):

ZOH Transfer function:

 s T
1e
TZOH( s T) 
s T

Switching frequency @ full load versus min and max input voltage:

 FswVLD0 
TswZOH      81.922   kHz
 FswVHD   125.836 
 0

G3 Power Stage integrating internal transfer function (Demag detection & ZOH):

1

H3 s VINDC  T
TswZOH
if VINDC = VINmin
0
1
T otherwise
TswZOH
1

 
H2 s VINDC  KD( s)  TZOH( s T)

Tools for Bode Plot:

 Power Stage Gain @ VINminDC
20

 
MAG H 1 f VINmin  20

MAG H 3 f VINmin

 40

 60

 80
3 4 5
10 100 1 10 1 10 1 10
f f

Power Stage Phase @ VINminDC

0

 50


ARG H1 f VINmin 
ARG H3 f VINmin  100

 150

3 4 5
10 100 1 10 1 10 1 10
f f
Type 2 OTA with automated calculations
1
R0   5  kΩ
gm

Selected Crossover frequency (Fc) and the wanted Phase Margin (PM):

Fc  1kHz PM  70°

Power stage Gain and Phase at the selected crossover frequency (including end of demag
detection and ZOH):

 
GFc  20 log H3 i 2  π Fc VINmin  GFc  32.523

PFc  arg  H3  i 2  π Fc VINmin  PFc  91.055 °

Boost  PM  PFc  90° Boost  71.055 °

  GFc 
 
G0  10
20 
G0  42.281

k 1  tan  45°
Boost
k 1  5.993
 2 
Fc
Fz  Fz  166.85 Hz
k1

Fp  k 1  Fc Fp  5.993  kHz

G0
R2  R2  211.404  kΩ
gm

1
C2  C2  4.512  nF
2π R2 Fz

1
C1  C1  0.126  nF
2π R2 Fp

2  π Fz
R2  C2 1
s
G0  g m G1 ( s)  G0 
C1  C2 s
1
2  π Fp

 
PM1  arg G1 i 2  π Fc   PFc PM1  70 °
 1

Fp0 R0 C1 C2  
2  π R 0  C 1  C 2  
1

Fp1 R2 C1 C2   C1 C2
2  π R 2
C1  C2

1

Fz R2 C2  
2  π R 2  C 2


Fc R2 C1 C2    
Fz R2 C2  Fp1 R2 C1 C2  

Normalized value R2  220kΩ C2  4.7nF C1  120pF

   
3
Fp0 R0 C1 C2  6.604  10  Hz Fp1 R2 C1 C2  6.183  kHz

 
Fz R2 C2  153.922  Hz  
Fc R2 C1 C2  975.512  Hz

1

2  π Fz R2 C2 
R2  C2 s
G01  g m G11( s)  G01
C1  C2 s
1

2  π Fp1 R2 C1 C2 
Open loop with ZOH:
1

Lx0 s VINDC   T
TswZOH
if VINDC = VINmin
0
1
T otherwise
TswZOH
1

 
H2 s VINDC  G11( s)  KD( s)  TZOH( s T)

Open loop without ZOH:

  
Lx1 s VINDC  H2 s VINDC  G11( s)  KD( s) 
 Open Loop Gain @ VINminDC
50

25


MAG Lx0 f VINmin 
 25
MAG Lx1 f VINmin

 50

 75

 100
3 4 5
10 100 1 10 1 10 1 10
f f

Open Loop Phase @ VINminDC

180

90


ARG Lx0 f VINmin 
0
ARG Lx1 f VINmin 

 90

 180
3 4 5
10 100 1 10 1 10 1 10
f f

Stability Criteria:

crossover frequency: Frequency @ Phase = 0°

 
fc0  fc Lx0 VINmin  1.013  kHz  
fg0  fg Lx0 VINmin  11.98  kHz

Phase margin: Gain margin @ 180°:


PM0  PM Lx0 VINmin  70.957 °   
GM0  GM Lx0 VINmin  28.263

crossover frequency: Frequency @ Phase = 0°

 
fc1  fc Lx1 VINmin  1.013  kHz  
fg1  fg Lx1 VINmin  83.149 kHz
Phase margin: Gain margin @ 180°:

 
PM1  PM Lx1 VINmin  73.182 °  
GM1  GM Lx1 VINmin  53.167
 Fsw versus Pout at VINhigh
5
1.6 10

5
1.2 10
110kHz
FswVHD
Fsw (Hz)

4
8 10
FswVHI

4
4 10

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)

Valley versus Pout at VINhigh

10

7
ValleyVHD
6
ValleyVHI 5

1
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)
 Ipk versus Pout at VINhigh

0.4

IpkVHD0.3
Ipk (A)

IpkVHI 0.2

0.1

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)

Comp versus Pout at VINHigh

3
VComp (V)

V CompVHD

V CompVHI 2

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)

Duty Ratio versus Pout at VINHigh

6
6 10

tonVHD
6
Duty Ratio (%)

tdemagVHD 4 10

tonVHI
6
2 10
tdemagVHI

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHD PoutVHI PoutVHI

Pout (W)
 VINhigh  375 V

MOSFET conduction and switching losses versus Pout at VINHigh

0.015 0.1

0.012 0.08
Conduction losses (W)

Switching losses (W)

3
PcondVHD 9 10 0.06 Psw
VHD

PcondVHI PswVHI
3
6 10 0.04

3
3 10 0.02

0 0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI PoutVHD PoutVHI

Pout (W)

VINhigh  375 V

Overall MOSFET losses versus Pout at VINHigh

0.1

0.08
P Mos losses (W)

 PcondVHDPswVHD 0.06
 PcondVHIPswVHI 0.04

0.02

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)
VINhigh  375 V
 SR MOSFET losses versus Pout at VINHigh
0.015 0.04

0.012 0.032
Conduction losses (W)

Switching losses (W)

3
P SR_condVHD 9 10 0.024 PSR_SDVHD

P SR_condVHI PSR_SDVHI
3
6 10 0.016

3 3
3 10 8 10

0 0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI PoutVHD PoutVHI

Pout (W)

VINhigh  375 V

Overall SR MOSFET losses versus Pout at VINHigh

0.05

0.04
P Mos losses (W)

 PSR_condVHDPSR_SDVHD 0.03
 PSR_condVHIPSR_SDVHI 0.02

0.01

0
0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12
PoutVHD PoutVHI

Pout (W)

ndVHI  PSR_SDVHI 
 Power Stage Gain @ VINmaxDC
20

 
MAG H 1 f VINmin  20

MAG H 3 f VINmin

 40

 60

 80
3 4 5
10 100 1 10 1 10 1 10
f f

Power Stage Phase @ VINmaxDC

0

 50


ARG H1 f VINmin 
ARG H3 f VINmin  100

 150

3 4 5
10 100 1 10 1 10 1 10
f f
 Open Loop Gain @ VINminDC
50

25


MAG Lx0 f VINmin 
 25
MAG Lx1 f VINmin

 50

 75

 100
3 4 5
10 100 1 10 1 10 1 10
f f

Open Loop Phase @ VINminDC

180

90


ARG Lx0 f VINmin 
0
ARG Lx1 f VINmin 

 90

 180
3 4 5
10 100 1 10 1 10 1 10
f f