10 Marks Questions

1. What are combinational circuits? Explain and verify the truth-table of Full-
Adder with the help of half adders.

Hint and marks breakdown:

Write about combinational circuits (2 marks), What is half-adder, its circuit and truth
table (3 marks) and finally the full-adder, simplification and expression (either using K-
map or Boolean algebra simplification) and finally the circuit diagram and truth table (5-
marks)

Solution:
2. What are combinational circuits? Explain and verify the truth-table of Full-
Subtractor with the help of half-subtractor.

Hint and marks breakdown:

Write about combinational circuits (2 marks), What is half-adder, its circuit and truth
table (3 marks) and finally the full-adder, simplification and expression (either using K-
map or Boolean algebra simplification) and finally the circuit diagram and truth table (5-
marks)

Solution:
3. Design a combinational circuit with the help of truth table which compares two
1-bit variables?

Hint and marks breakdown:

Indirectly the evaluator is referring to Magnitude comparator circuit. Write about

what is comparator circuits (2-marks), its truth table (2-marks), expression using K-map
(3-marks) and final circuit (3 marks)

Solution:
4. Implement f ( A , B ,C )=∑ m ( 1 , 3 ,6 ,7 ) using 4:1 MUX using A and B as select line

Hint and marks breakdown:

This type of questions can be framed based on any functions w.r.t. two to three
variables. Find the logic using MUX mapping (truth-table/Tabular method) (4-marks),
Design the circuit based the logic output (4-marks) and verify the truthtable (2marks)

Solution:

A B C ∑ m ( 1 ,2 , 6 , 7 ) Logic
0 0 0 0 C
0 0 1 1
0 1 0 0 C
0 1 1 1
1 0 0 0 0 (GND)
1 0 1 0
1 1 0 1 1 (Vcc)
1 1 1 1
 5. Design 16:1 MUX using 4:1 MUX

Hint and marks breakdown:

Match the inputs using the smaller one total number of inputs required i.e. in this case
16/4 = 4, therefore four 4:1 MUX will be used at the input side. The four outputs of these
MUX will act as the inputs to the last 4:1 MUX. Make sure that two MSB’s will be the
select line for 2nd stage 4:1 MUX (Multiplexer at the output side). Circuit design (6
marks) and Truth-Table (4 marks)

Solution:

S3 S2 S1 S0 Output
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15

6. Implement all gates using MUX

Hint and marks breakdown:

There are total seven gates i.e. AND, OR, NOT, NAND, NOR, XOR and XNOR, and
majorly all except one has two input and one output, therefore 2:1 MUX will be used to
design the gates with one input as select line and other as the inputs to the MUX. (1.5
marks for each gates)

Solution:
7. Implement f ( A , B ,C )=∑ ( 2, 4 , 5 ,7 ) using 3:8 Decoder (5 marks)

Hint and marks breakdown:

Circuit design (3 marks) and Truth Table (2 marks)

Solution:
I2 I1 I0 Output
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
8. Design 4:16 Decoder using only 2:4 decoder

Hint and marks breakdown:

Match the outputs using the smaller decoder, total number of outputs required i.e. in
this case 8/4 = 2, therefore four 2:4 decoder will be used at the output side. Make sure
that the MSB will be the enable line for 1st stage and the LSB will be the enabler for the
last stage (Output side). Circuit design (6 marks) and Truth-Table (4 marks)

Solution:
I3 I2 I1 I0 Output
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15

9. Design a combinational circuit which converts Decimal number system to Binary

Coded Decimal number?

Hint and marks breakdown:

A decimal to BCD encoder has 10 input lines D0 to D9 and 4 output lines Y0 to Y3.
Truth-Table (3 Marks), Boolean Expression (2 marks), Circuit Diagram (4 Marks), Block
diagram.

Solution:

Expression

Y0 = D1 + D3 + D5 + D7 + D9

Y1 = D2 + D3 + D6 + D7

Y2 = D4 + D5 + D6 + D7

Y3 = D8 + D9
10. Design a combinational circuit which converts Octal numbers to Binary value

Hint and marks breakdown:

A Octal to Binary encoder has 8 input lines Y0 to D7 and 3 output lines A0 to A2.
Truth-Table (3 Marks), Boolean Expression (2 marks), Circuit Diagram (4 Marks), Block
diagram.

Solution:
Expression

A2 = Y7 + Y6 + Y5 + Y4

A1 = Y7 + Y6 + Y3 + Y2

A0 = Y7 + Y5 + Y3 + Y1

11. Design a combinational circuit which converts Hexa-Decimal numbers to Binary

numbers.
Hint and marks breakdown:

A Hexadecimal to Binary encoder has 16 input lines I0 to IF and 4 output lines Y0 to

Y3. Truth-Table (3 Marks), Boolean Expression (2 marks), Circuit Diagram (4 Marks),
Block diagram.

Solution:

Y0 = I8 + I9 + IA + IB + IC + ID + IE + IF
Y1 = I4 + I5 + I6 + I7 + IC + ID + IE + IF

Y1 = I2 + I3 + I6 + I7 + IA + IB + IE + IF

Y1 = I1 + I3 + I5 + I7 + I9 + IB + ID + IF

12. Design a combinational circuit which Priority In over. In-1

Hint and marks breakdown:

Evaluator is indirectly talking about Priority encoder. Truth-Table (2 Marks), Boolean

Expression using K-map (4 marks), Circuit Diagram (4 Marks), Block diagram.

Solution:

D0 D1 D2 D3 Q0 Q1
0 0 0 0 X X
 1 X X X 0 0
0 1 X X 0 1
0 0 1 X 1 0
0 0 0 1 1 1

Q0 Q1
D2 D3 D2 D3
00 01 11 10 00 01 11 10
D0 D1
D0 D1
X 1 1 1 X 1 1 0
00 00
01 0 1 1 1 01 1 1 1 1
11 0 1 1 1 11 0 1 1 0
10 0 1 1 1 10 0 1 1 0

Q0 = D3 + D2 Q1 = D3 + D0’D1

13. What is Parity Generator and Parity Checker? Design and explain in details Parity
Generator circuit discussing both even and odd parities with the help of truth table.
Hint and marks breakdown:

Parity Generator and Parity checker explanation (2 Marks) Truth-Table (2 Marks),

Boolean Expression using K-map (4 marks), Circuit Diagram (4 Marks), Block diagram.