TH E ANALOG M IN D

Behzad Razavi

The Design of a Millimeter-Wave Frequency Synthesizer

W
We have previously described the
design of a voltage-controlled oscilla-
tor (VCO) and a multimodulus divider
(MMD) for the 30-GHz range [1], [2].
In this article, we extend our work to
value. For a finer resolution, one
would need to resort to fractional-N
operation. Third, the circuit must
incorporate a feedback divide ratio,
N, of about 300. The synthesizer is
4N 2 S REF fBW . Doubling this amount to
account for the reference, we obtain
the rms jitter as

  DT j =
8N 2 S REF fBW
TVCO (1)
2r
develop a millimeter-wave integer-N designed in 28-nm CMOS technology
frequency synthesizer. The reader is with VDD = 0.95 V in the slow–slow w h e r e TVCO d e n o t e s t h e o u t p u t
referred to the vast body of knowl- corner at T = 75c C. period.
edge in this domain, e.g., [3], [4], [5]. Recall from [1] that our complete
We target the following specifications: PN Considerations VCO design is as shown in Figure 2(a)
■ ■ output frequency range: fout = The assumed reference PN of −170 and displays the PN profile shown
28 GHz-32 GHz dBc/Hz leads to a number of con- in Figure 2(b). Since N 2 S REF / -120
■■ output phase noise (PN): −100 dBc/Hz straints on the design. As the syn- dBc/Hz, we draw a horizontal line
at 1-MHz offset thesizer loop bandwidth, fBW, is at this intercept, reaching SVCO at
■■ output spur level: −50 dBc reduced, this contribution to jitter fBW . 6 MHz. Equation (1) then yields
■■ output jitter: < 200 fs rms falls, but that due to the VCO rises.
DT j . 35 fs rms.(2)
■■ reference frequency: fREF = 100 MHz As a rule of thumb, we select fBW to
■■ reference PN: S REF = - 170 dBc/Hz make the two contributions equal, This value is far below our 200-fs
■■ power budget: 10 mW. tacitly neglecting other sources of target, but our synthesizer design
These quantities merit a few noise. From another perspective, we will face other imperfections that
remarks. First, while related, PN and multiply S REF by N2 and set the band- raise the jitter considerably.
jitter specifications serve different width equal to the offset frequency The rigid condition fBW . 6 MHz
purposes. The former signifies how at which N 2 S REF intersects the VCO imposes certain restrictions on the
much a receiver can tolerate blockers free-running PN, SVCO (Figure 1). In loop parameters, creating tradeoffs
in the presence of reciprocal mixing, the ideal case, the phase-locked among the chip area, PN, and spur
whereas the latter represents the cor- system exhibits a PN profile that is level. This point becomes clear later.
ruption that the synthesizer imparts flat up to ! fBW and drops in propor- Another consequence of reduc-
to the signal constellation in both tion to f 2 beyond these points. One ing fBW is the long settling time.
the transmit path and the receive can show in such a scenario that the While typical phase-locked loops
path. The desired jitter is computed total integrated VCO PN is equal to (PLLs) settle in roughly 50–100 ref-
conservatively by integrating the PN erence cycles, we expect a substan-
from a 10-kHz offset to a 1-GHz off- tially greater amount in this case.
set, but this range must be carefully S φ (f ) The result may still satisfy the radio
Free−Running
chosen in conjunction with the mod- VCO PN standard’s requirement, but it will
ulation scheme and the symbol rate. pose serious issues in terms of the
N 2SREF
Second, with fREF = 100 MHz, the simulation time (see the “The Con-
Phase−Locked
synthesizer can provide a minimum VCO PN cept of Loop Scaling” section).
output frequency step of the same
–fBW 0 +fBW f Synthesizer Architecture
Digital Object Identifier 10.1109/MSSC.2023.3269456 As shown in Figure 3, the integer-N syn-
Date of current version: 22 June 2023 FIGURE 1: The choice of loop bandwidth. thesizer incorporates the previously

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 VDD = 0.95 V
–20
Mirror Ratio = 2.5
500 fF 53 pH 320 Ω 53 pH 500 fF –40
W and L Quadrupled

Phase Noise (dBc/Hz)

–60 IREF Halved

4 µm 4 µm –80
16 µm 30 nm 30 nm 16 µm
–100
200 nm M1 M2 200 nm
Mv 1 ISS 2 mA Mv 2
–120

Vcont –140
175 fF S0 175 fF –160
104 106 108
N 160 µm M
Offset Frequency (Hz)
S1 S2
(b)
120 nm 120 nm
Dcont
(a)

FIGURE 2: (a) The millimeter-wave VCO design and (b) its PN.

designed VCO and MMD along with Choice of Loop Parameters

a phase frequency detector (PFD), Our 30-GHz VCO provides a KVCO of IP KVCO
a charge pump (CP), and a loop fil- about 2.08 GHz/V / 13.1 grad/s/V. fREF PFD CP VCO fout
ter. The VCO gain is dented by KVCO, Such a high gain can translate the
R1
and the CP current is dented by ripple on the control voltage to large C2
C1
I P. Even though true single-phase spurs at the output. It is possible to
clocking offers a lower PN for the reduce KVCO by making the varactors N
PFD [6], we opt for a NOR-based smaller, but let us proceed with this MMD
static topology to ensure reliable value for now. With N . 300 in Fig-
operation at 100 MHz despite device ure 3, we must determine I P, R1, C1, FIGURE 3: The synthesizer architecture.
leakage. We expect that the input- and C2. We begin with I P = 0.5 mA,
referred PN arising from the PFD obtaining C 1 = 15.2 pF from (5) and
and/or the CP may be comparable to R 1 = 8.7 kΩ from (4). 20log|H |
S REF = -170 dBc/Hz. Thus, the loop The choice of C 2 in Figure 3
BW may need to decrease, leading to entails a tradeoff. To suppress the
a greater integrated jitter. CP activity and hence the ripple, we
The closed-loop 3-dB BW is wish to maximize C2 and can allow
ωp3
approximately given by a value as large as 0.2C 1 with neg- 0
1 ωu log ω
ligible effect on the loop settling
R1C1
2 2
(2rfBW) = [1 + 2g + (1 + 2g ) + 1 ] 2
~ n2 behavior. However, the pole intro-
(3) duced by C2 and given by H
log ω
where 1 0
~ p3 = (7)
R1 C 1 C2 –90°
R1 I P K VCO C 1 C1 + C2
g= (4)
2 2rN –180°
causes peaking in the input–out- PM
and put response and in the output PN
profile. Plotting the magnitude and FIGURE 4: The magnitude and phase of the
I P K VCO
~n = .(5) phase of the loop transmission, synthesizer’s loop transmission. PM: phase
2rC 1 N
margin.
For well-behaved settling, we select
H (s) = 2rI P c R 1 + 1 m VCO (8)
K
g = 1 and arrive at C 1 s Ns With R 1 = 8.7 kX , we have C 2 . 0.5 pF
if ~ p3 . 5~ u . Figure 5(a) summa-
fBW . 2.5~ n (6)
  in Figure 4, we observe that the phase rizes the results, and Figure 5(b)
2r
margin (PM) degrades if ~ p3 does not depicts the CP design. Note that a
which, according to our previous lie much farther than the unity-gain unity current-mirror ratio in the CP
estimates, should be set to about bandwidth, ~ u ^. 2rfBWh . Thus, we avoids excessive multiplication of
6 MHz. That is, ~ n . 2r (2.4 MHz). must select ~ p3 & 2rfBW = 2r (6 MHz). the diode-connected devices’ noise.

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 The large area occupied by C1 CP-induced PN (see “The Concept of steady-state (pss) simulation for lon-
motivates us to increase I P and Loop Scaling” section). ger than the lock time and follow it
decrease C1 in (4) while maintaining by a periodic noise (pnoise) simula-
g = 1. For example, I P = 1 mA yields The Need for Fast Simulations tion, including a sufficient number of
C 1 = 7.6 pF. However, this doubles The basic integer-N PLL can be con- sidebands. Specifically, a divide ratio
~ n and ~ 3dB. In other words, the structed and simulated fairly quickly. of N = 300 in our example demands
6-MHz loop bandwidth—imposed by However, optimization for loop about 5N = 1, 500 sidebands, lead-
N 2 S REF and SVCO —creates a rigid situ- dynamics and output jitter requires ing to extremely slow pnoise analy-
ation in terms of C1 and I P, requiring hundreds of simulations. Transient ses. With the addition of ancillary
that they scale in the same direc- analyses must use a time step much functions, e.g., voltage regulators,
tion. If both are reduced by a factor less than TVCO and run for a total time the task becomes nearly impossible.
of a, then so is g, which dictates much longer than TREF = 1/fREF . For We resolve these issues by introduc-
that R1 be increased by the same example, if the time step is 5 ps and ing the concept of “loop scaling.”
factor. Lowering C2 proportionally the loop locks in 50TREF = 500 ns,
as well, we note from (7) that ~ p3 the simulation must run for 500,000 The Concept of Loop Scaling
remains unchanged. We conclude points. This is necessary for evaluating To save simulation time, we wish to
that C 1 /a, I P /a, aR 1, and C 2 /a form the lock time and the output spur level. reduce the ratio fVCO /fREF = N. Illus-
a feasible solution (Figure 6). None- Similarly, to obtain the output PN trated conceptually in Figure 7, the
theless, a lower I P leads to greater profile, we must perform a periodic idea is to scale fREF up and the divide
ratio down by the same factor, K. We
envision that the loop settling time
VDD falls by K. More importantly, the
lower complexity of the divider also
Ip = 0.5 mA KVCO = 2.08 GHz/V 10 µm 10 µm
leads to significantly faster pss and
90 nm 90 nm
CP VCO fout pnoise simulations.
10 µm
0.5 mA Up For this concept to deliver consis-
8.7 kΩ 30 nm
0.5 pF tent results as K decreases toward
15.2 pF one, we must bea r in mind t wo
10 µm
Down
0.5 mA 90 nm points. First, in view of the design
effort necessary for the VCO, we pre-
5 µm 5 µm
300 90 nm fer not to alter it or its load. Alterna-
90 nm
tively, we can replace the VCO circuit
(a) (b) with a Verilog behavioral model and
include its noise by inserting a volt-
age source in series with its control
FIGURE 5: (a) Loop parameter values for fBW = 6 MHz and (b) CP design. [7]. In any case, KVCO is constant. Sec-
ond, we also wish to avoid changes to
the transistor-level design of the PFD
and CP so that their imperfections
IP
IP KVCO KVCO do appear in the synthesizer output
α
and exhibit a “scalable behavior” as a
CP VCO CP VCO function of K. That is, IP is constant.
R1 αR1 Third, we must keep g constant
C2
C2 as well so that the loop dynamics
C1 α
C1 are predictable.
α
Let us return to (4) and (5) and ask
how the loop parameters must scale.
FIGURE 6: The choice of loop parameter values for a constant g and bandwidth. If N " N/K , we opt for C 1 " C 1 /K
so that g does not change. As a
result, ~ n increases by a factor of K,
and so does fBW = 2.5~ n / (2r) . The
PLL PLL
key point here is that the settling
fREF fout KfREF fout dynamics retain their shape but
N N
K become K times faster. Figure 8 sum-
marizes our loop scaling principle.
This method should not be confused
FIGURE 7: An illustration of loop scaling. with that in Figure 6.

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The Effect of Loop Scaling on Jitter in unity steps. Popular MMD topolo- redesigned for different K values if
and Spurs gies include the pulse-swallow coun- its complexity must be minimized.
Our ultimate goal is to be able to ter and Vaucher’s structure [8]. Used
predict the performance of the for our millimeter-wave Simulation Procedure
unscaled loop from that of the design [1], the latter also Our ultimate We perform three sim-
scaled one. To this end, we construct lends itself to loop scaling goal is to be able ulations for each choice
the PN profiles of the free-running much more easily. This is to predict the of K so as to quantify the
or phase-locked VCO for K = 1 and due to its modular form. performance of synthesizer’s behavior.
K > 1, neglecting flicker noise upcon- As shown in Figure 11, the unscaled loop First, we run a transient
version for simplicity. As illustrated we can cascade two or from that of the simulation and examine
in Figure 9, the jitter falls for K > 1 more stages so as to scaled one. 1) the VCO control settling
and is expressed from (1) as scale N by a factor of time and 2) the reference
K. The pulse-swallow counter, on spurs in the output spectrum. We
4 c N m S REF (KfREF)
2

K the other hand, would need to be also consider the time alignment of
DT j = TVCO (9)
2r
4N 2 S 2REF fREF
    = 1 TVCO (10) IP KVCO IP KVCO
K 2r
fREF CP VCO fout KfREF CP VCO fout
where the factor of four accounts R1 R1
C2 C2
for only the VCO contribution. That C1 C1
K
K
is, the VCO-induced output jitter of
the scaled loop is lower by a factor N
N
of K . K
Additionally, the reference, the
PFD, and the CP also introduce PN, FIGURE 8: The scaling of the loop parameter values.
which dominates the “in-band” com-
ponents, i.e., those between - fREF
S φ (f )
and + fREF . Lumping these contri-
Free−Running
butions into S REF, we observe from VCO PN
Figure 10 that the corresponding
K=1
jitter (the square root of the area
2S
under the profile) falls by a factor of N REF
K regardless of the shape of the Phase−Locked
VCO PN
input–output transfer function. We
can then predict the output jitter as N 2
SREF
we begin with a heavily scaled loop K
K>1
and gradually decrease K.
The effect of loop scaling on the
output reference spurs is studied –KfBW –fBW 0 +fBW +KfBW f
as follows. Suppose a scaled PLL
exhibits a certain ripple amplitude, FIGURE 9: The effect of loop scaling on VCO PN.
Vr. The output spur level is given by
Vr K VCO / (4rfREF) if we approximate
the ripple by a sinusoid. We now PN Due to REF
and PFD/CP
increase C1 and C2 by a factor of K and
decrease the reference frequency by K=1
the same factor. For a fixed PFD/CP
design, the ripple amplitude falls N 2SREF
by K, yielding a spur level equal to
(Vr /K) K VCO / (4rfREF /K) = Vr K VCO / (4r
fREF). That is, the spur level remains N 2
SREF
constant. This point holds even if K
K>1
the ripple is not sinusoidal.

The Choice of MMD Topology –KfBW –fBW 0 +fBW +KfBW f

Frequency synthesis requires an
MMD whose divide ratio can change FIGURE 10: The effect of loop scaling on reference, PFD, and CP PN.

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the PFD and CP output pulses in the Third, we perform another set of the transformation depicted in Fig-
locked condition. pss and pnoise simulations with the ure 8, we have C 1 = 15.2 pF/K = 405 fF
Second, we carry out pss and noise of RD in Figure 12 set to zero, and C 2 = 13 fF, the latter becoming
pnoise simulations to determine the arriving at the output PN profile due comparable to the VCO varactors’
input–output frequency response. to the synthesizer itself. The integral capacitance and hence causing an
This is accomplished by modulating of this profile yields the rms jitter. error in the value of ~ p3 . We retain the
the supply of the reference buffer by original values of IP = 0.5 mA and
thermal noise so as to impart white First Scaled Loop R 1 = 8.7 kΩ, arriving at the design
PN to the waveform entering the PFD We wish to reduce N = 300 by a large shown in Figure 13.
(Figure 12) [7]. If this PN is tens of factor to allow fast simulations. But Figure 14 plots the oscillator con-
decibels greater than the synthesiz- we must also bear in mind that typi- trol voltage, suggesting a settling
er’s intrinsic noise, the output spec- cal static PFD designs do not operate time of about 15 ns. This waveform
trum reveals the transfer function, above 5 GHz in 28-nm technology. We also implies a peak-to-peak ripple of
specifically, the 3-dB bandwidth and then select N = 8, K = 300/8 = 37.5, about 100 mV, but much of this dis-
the amount of peaking. and fREF = 30 GHz/8 = 3.75 GHz. From turbance arises from the coupling of

Module 1 2/3 Module 2 2/3

Q2 Q4
L2 L2′ L2 L2′
Q2 Q4
Q1 CK1 Q3 CK2
CK
L1′ L1 L1′ L1
MC1 MC2
B1 B2

FIGURE 11: Vaucher’s modular MMD. CK: clock; MC: modulus control.

+
1,000 VX
– VX
0.9
+
– 0.8
Vcont (V)

0.7
PLL
fREF 0.6
f
0.5
fout f
0 5 10 15 20
Time (ns)

fREF f
FIGURE 14: Oscillator control voltage
FIGURE 12: Input phase modulation for obtaining the input–output response. settling.

IP = 0.5 mA KVCO = 2.08 GHz/V

Output Spectrum (dB)

–20
fREF = 3.75 GHz CP VCO fout
–40
8.7 kΩ
13 fF –60
405 fF
–80

–100
20 25 30 35 40
8 Frequency (GHz)

FIGURE 15: The first scaled loop output

FIGURE 13: A scaled loop with a divider ratio of eight. spectrum.

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 1 700 700
600 600
0.8
500 500

Current (µA)

Current (µA)
Voltage (V)

0.6 400 400

300 300
0.4
200 200
0.2 100 100
0 0
0 –100 –100
20.3 20.4 20.5 20.6 20.1 20.2 20.3 20.1 20.2 20.3 20.4
Time (ns) Time (ns) Time (ns)
(a) (b) (c)

Up Down

FIGURE 16: (a) PFD up and down pulses, (b) CP up and down currents, and (c) improved alignment between CP up and down currents.

the VCO’s internal swings through

the varactors. This phenomenon
Input-Output Response (dB)

proves benign. 0
To find the output reference spurs,
–5
we take the fast Fourier transform
–10
(FFT) of the VCO’s differential output
–15
from t = 15 ns to t = 20 ns, obtain-
ing the spectrum shown in Figure 15 –20
and observing a spur level of about –25
−48 dBc, a value greater than our
105 106 107 108 109
target. Let us delve into this issue by Frequency (Hz)
examining the up and down outputs
of the PFD [Figure 16(a)]. They appear
FIGURE 17: The input–output response of the first scaled loop.
well aligned. But more relevant are
the output current pulses generated
by the CP [Figure 16(b)]. Originat-
ing from the inverter skew in Figure –100
Output Phase Noise (dBc/Hz)

5(b), the 6-ps pulsewidth difference

–110
noted here is partially responsible
for the high spurs. We then insert a –120
transmission gate in the down path –130
and improve the situation to that
depicted in Figure 16(c). The spur –140
level falls to −51 dBc. –150
The next phase of our study
relates to the input–output trans- –160
fer function. We follow Figure 12 106 108
and reach the output spectrum Frequency (Hz)
shown in Figure 17. The 3-dB BW is
182 MHz, which is somewhat lower FIGURE 18: The output PN of the first scaled loop.
than our previous prediction of
KfBW = 37.5 # 6 MHz = 225 MHz. The The PN drops by 3 dB with respect Figure 1(b) and predict a value less
response suffers from a peaking of to the plateau value at f = 147 MHz. than −150 dBc/Hz at this offset. Why
2.6 dB at 80 MHz. We call this quantity the “noise- is there so much discrepancy? We
The last part of our investiga- shaping” bandwidth. suspect the CP noise. The in-band
tion deals with PN and jitter. Plotted Let us check the validity of the output PN due to the CP is given by
in Figure 18 is the output PN pro- −129-dBc/Hz PN in the plateau
file, displaying a plateau of about region. With a noise-shaping BW of 2
S z, CP (f ) = (4r 2 N 2) 2 I2n · res (11)
T
−129 dBc/Hz and 0.5 dB of peaking. 147 MHz, we return to the VCO PN of I P TREF

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 where I 2n denotes the white noise of
IP = 0.5 mA KVCO = 2.08 GHz/V each CP current source, and Tres denotes
the minimum pulsewidth of the up and
fREF = 1.875 GHz CP VCO fout
down pulses. Also, I 2n = 4kTcg m, where
k = 1.38 # 10 -23 J $ K and T is the
8.7 kΩ
26 fF temperature. Writing g m = (2I P ) /
810 fF (VGS - VTH), we have

16 kT T
· res .
S z, CP (f ) = (4r 2 N 2)
I P (VGS - VTH) TREF
16 (12)

From Figure 16(c), Tres . 25 ps. Since

FIGURE 19: A scaled loop with a divide ratio of 16. IP = 0.5 mA, VGS - VTH . 200 mV, N = 8,
and TREF = 1/ (3.75GHz), we obtain

–10 S z,CP (f) = - 128 dBc/Hz. (13)

Output Spectrum (dB)

0.9 –20
0.8 –30 This means that the CP thermal noise
Vcont (V)

–40 dominates the output, a trouble-

0.7
–50 some point to which we return later.
0.6 –60 We can also refer this amount to the
0.5 –70 input by subtracting 20 log 8 = 18 dB,
–80 obtaining −146 dBc/Hz.
0 10 20 30 40 25 30 35
We recognize from Figure 18 that
Time (ns) Frequency (GHz)
(a) (b) the PN falls at a rate of 10 dBc/Hz
from f = 10 kHz to f = 1 MHz. Such
FIGURE 20: (a) Oscillator control settling of the second scaled loop and (b) the output a signature stems from the flicker
spectrum. noise of the CP rather than from that
of the VCO.
To compute the jitter, we find the
Input-Output Response (dB)

0 area under the profile of Figure 18

–5 and double it to account for the PN
–10 on both sides of the carrier:
–15
–20
1 GHz
–25 2 8 10 kHzS z (f ) df
DT j = TVCO .(14)
–30 2r
–35
We have DT j = 41 fs rms. Note that this
105 106 107 108 109
Frequency (Hz) amount does not include the refer-
ence PN. According to our previous
FIGURE 21: The input–output response of the second scaled loop. projection, this value translates to a
jitter of K # 41 fs rms = 250 fs rms for
the unscaled synthesizer. It appears
–100 that the design fails to meet our tar-
Output Phase Noise (dBc/Hz)

–110 get even if the reference contribu-

tion is neglected.
–120

–130 Second Scaled Loop

–140 Despite missing our target speci-
fication, we continue our loop
–150
scaling efforts to see whether the
–160 parameters vary according to our
104 105 106 107 108 109 projections. We now select N = 16,
Frequency (Hz) K = 18.75, C 1 = 810 fF, C 2 = 27 fF,
and fREF = 1.875 GHz (Figure 19). A
FIGURE 22: The output PN of the second scaled loop. transient simulation produces the

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 0

Output Phase Noise (dBc/Hz)

Input-Output Response (dB)
–100
–10 –110

–20 –120
–130
–30
–140
–40 –150
N = 32 N = 64 N = 32 N = 64
–50 –160

106 107 108 109 104 105 106 107 108 109
Frequency (Hz) Frequency (Hz)
(a) (b)

FIGURE 23: (a) The input–output responses of third and fourth scaled loops and (b) corresponding PN profiles.

settling behavior of Figure 20(a) Plotted in Figure 23(a) are the in- The cost is a larger area occupied by
and the output spectrum of Figure put–output responses for the two the capacitors.
20(b). The spur level is −52 dB, fairly cases, yielding fBW = 54 MHz and
consistent with our conjecture that 26 MHz, respectively. We observe References
[1] B. Razavi, “The design of a millimeter-
it should remain constant. that t h e b a n d w i d t h wave VCO [The Analog Mind],” IEEE
Plotted in Figure 21 is We can return i s scaled w ith rea- Solid-State Circuits Mag., vol. 14, no. 3,
pp. 6–12, Summer 2022, doi: 10.1109/
the input–output response, to the original sonable accuracy. Fig- MSSC.2022.3184443.
displaying a BW of 103 loop bandwidth ure 23(b) depicts the [2] B. Razavi, “The design of a millimeter-
wave frequency divider [The Analog
MHz and suggesting that calculations; output PN profiles and Mind],” IEEE Solid-State Circuits Mag., vol.
it is not quite halved assume an SREF suggests a plateau value 14, no. 4, pp. 6–16, Fall 2022, doi: 10.1109/
with respect to the first dominated by the of −120 dBc/Hz for N = 32 MSSC.2022.3205805.
[3] D. Liao, Y. Zhang, F. F. Dai, Z. Chen, and
scaled loop. The peak- CP and reduce fBW and −113 dBc/Hz for N = Y. Wang, “An mm-wave synthesizer with
ing is about 2.1 dB. accordingly. 64. These results are fair­ robust locking reference-sampling PLL
and wide-range injection-locked VCO,”
F i g u r e 22 s h o w s ­ly aligned with S z, CP ? N 2 IEEE J. Solid-State Circuits, vol. 55, no. 3,
pp. 536–546, Mar. 2020, doi: 10.1109/
the output PN with a plateau value in (11). The integrated jitter values JSSC.2019.2959513.
of −125 d B c / H z . From (11), this amount to 60 fs rms and 90 fs rms , re- [4] D. Yang et al., “A harmonic-mixing PLL
architecture for millimeter-wave applica-
should be equal to −123 dBc/Hz be- spectively. The scaling of the jitter is tion,” IEEE J. Solid-State Circuits, vol. 57,
cause N is doubled. The 2-dB discrep- now somewhat close to the theoreti- no. 12, pp. 3552–3566, Dec. 2022, doi:
10.1109/JSSC.2022.3209614.
ancy may be avoided if the number cal factor of K . [5] T. Si r ib u r a n on et a l ., “A low -p owe r
of sidebands in the pnoise analysis Let us project the jitter of the low-noise mm-wave subsampling PLL
using dual-step-mixing ILFD and tail-
is increased. Integrating this profile unscaled loop from our last case: coupling quadrature injection-locked
yields a jitter of 47 fs, which is 15% DT j = 90 fs # 300/64 =195 fs rms. We oscillator for IEEE 802.11ad,” IEEE J.
Solid-State Circuits, vol. 51, no. 5, pp.
(rather than a factor of 2 ) greater may expect that the reference PN will 1246–1260, May 2016, doi: 10.1109/JSSC.
than that in the previous case. elevate this value considerably. How- 2016.2529004.
[6] A. Homayoun and B. Razavi, “Analysis
ever, recall from previous sections of phase noise in phase/frequency de-
Third and Fourth Scaled Loops that the input-referred CP contribution tectors,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 60, no. 3, pp. 529–539, Mar.
To form a clearer picture of the is around −146 dBc/Hz, far exceeding 2013, doi: 10.1109/TCSI.2012.2215792.
trends, we study two more cases our presumed S REF = - 170 dBc/Hz. [7] B. Razavi, Design of CMOS Phase-Locked
Loops. Cambridge, U.K.: Cambridge Univ.
with N = 32 and N = 64. For the former, Thus, the unscaled loop still exhibits Press, 2020.
we select C 1 = 1.62 pF, C 2 = 54 fF, a jitter of about 200 fs rms . [8] C. S. Vaucher et al., “A family of low-power
truly modular programmable dividers
and fREF = 937.5 MHz. For the latter, The jitter that we have obtained in standard 0.35-μm CMOS technology,”
we have C 1 = 3.24 pF, C 2 = 108 fF, is not minimum. We can return to IEEE J. Solid-State Circuits, vol. 35, no. 7,
pp. 1039–1045, Jul. 2000, doi: 10.1109/
and fREF = 468.75 MHz. According to the original loop bandwidth calcula- 4.848214.
transient simulations, the output tions; assume an S REF dominated by

spur level remains around −51 dB. the CP and reduce fBW accordingly.

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