INTRODUCTION TO VERILOG

HDL
 What is Verilog?

• V e rilo g is a H D L - h a rd w a re d e s c rip tio n la n g u a g e to

d e s ig n th e d ig ita l s ys te m .

• V H D L is o th e r h a rd w a re d e s c rip tio n la n g u a g e.
• V irtu a lly ev ery c h ip (F P G A , A S IC , e tc .) is d e s ig n e d in
p a rt u s in g o n e o f th es e tw o la n g u a g e s

• V e rilo g w a s in tro d u c ed in 1 9 8 5 b y G a tew a y D e s ig n

S ys te m C o rp o ra tio n
 Verilog

• IE E E 1 3 6 4 -2 0 0 1 is th e la te s t V e rilo g H D L
sta n d a rd

• V e rilo g is c a se s e n sitiv e (K e y w o rd s a re in
lo w e rc a se )

• T h e V e rilo g is b o th a b e h a v io ra l a n d a
stru c tu re la n g u a g e
 Difference between VERILOG and
VHDL
• V e rilo g is s im ila r to c - la n g u a g e .

• V H D L is s im ila r to A d a - (a d a is a s tru c tu re d ,
s ta tic a lly typ ed , im p era tiv e , w id e s p ec tru m
a n d o b je c t – o rie n te d h ig h lev el c o m p u te r
p ro g ra m m in g la n g u a g e, e xten d e d fro m
P a s c a l)

• M a n y fe e l th a t V e rilo g is e a s ie r to le a rn a n d
u s e th a n V H D L.
Elements of Verilog-logic values

■ 0 : ze ro , lo g ic lo w , fa lse , g ro u n d

■ 1 : o n e , lo g ic h ig h , p o w e r

• X: unknow n

• Z : h ig h im p e d a n c e , u n c o n n e c te d , tri-sta te
 Elements of Verilog- data type
• N e ts
– N e ts a re p hy sic a l c o n ne c tio ns b e tw e e n d e v ic e s
– M a n y typ e s o f n ets, b u t a ll w e c a re a b o ut is w ire .
• Declaring a net
wire [<range>] <net_name> ;
Range is specified as [MSb:LSb]. Default is one bit wide
• R e g is t ers
– Im p licit sto ra ge -h o ld s its v a lue until a ne w v a lue is a ss ig n ed to it.
– R e g is te r ty p e is d e no te d b y re g .
• Declaring a register
reg [<range>] <reg_name>;

• a re n o t v a ria b le s, th e y a re
c o n sta n ts.
 Verilog Primitives

• B a s ic lo g ic g a te s on ly
– and
– or
– n o ta
– buf
– xo r
– na nd
– nor
– xn o r
– b u fif1 , b u fif0
– n o tif1 , n o tif0
 Numbers in Verilog

< size > ’ < ra d ix > < va lu e >

– 8 ’ h a x = 10 1 0 xxxx
– 1 2 ’ o 3 zx7 = 0 1 1zzzxxx1 1 1
 Logical Operators

• &&  lo g ic a l A N D
• ||  lo g ic a l O R

• !  lo g ic a l N O T

• O p e ra n d s e v a lu a te d to O N E b it v a lu e : ,
or
• R e su lt is O N E b it v a lu e : , or
A = 1; A && B  1 && 0  0
B = 0; A || !B 1 || 1  1
C = x; C || B  x || 0  x
 Bitwise Operators (i)

• &  b itw ise A N D

• |  b itw ise O R
• ~  b itw ise N O T
• ^  b itw ise X O R
• ~ ^ o r ^~  b itw ise X N O R

• O p e ra tio n o n b it b y b it b a sis
 Bitwise Operators (ii)
c = ~a; c = a & b;

• a = 4’ b1010;
b = 4’ b1100;

c = a ^ b;

• a = 4’ b1010;
b = 2’ b11;
 Shift, Conditional Operator

• > >  sh ift rig h t

• < <  sh ift le ft
• a = 4’ b1010;
d = a > > 2 ;// d = 0 0 1 0 ,c = a < < 1 ;// c = 0 1 0 0
• c o n d _ e xp r ? tru e _e xp r : fa lse _e xp r
A
1
Y
Y = ( sel ) ? A : B;
B
0
sel
 Keywords
• N o te : A ll k e yw o rd s a re d e fin e d in lo w e r
case
• E xa m p le s :
• m o d u le , e n d m o d u le
• in p u t, o u tp u t, in o u t
• re g , in te g e r, re a l, tim e
• n o t, a n d , n a n d , o r, n o r, x o r
• p a ra m e te r
• b e g in , e n d
• fork , jo in
• sp e c ify , e n d sp e c ify
 Keywords

• m o d ule – fu nd am e n ta l b u ild in g b lo c k fo r V e rilo g

d e s ig ns
• U se d t o c o n st ru c t d e s ig n h ie ra rc h y

• C a nn o t b e n e s te d

• e n d m o d u le – e nd s a m o d u le – n o t a sta te m e n t

=> no “ ;”

• M o d ule D e c lara tio n

• m o d u le ( , , );

• E x a m p le : m o d u le full _a d d e r (A , B , c _ in, c _ o u t , S );
 Verilog keywords

• Inp u t D e c la ra tio n
• S c a la r

• in p u t ;

• E x a m p le : in p u t A , B , c _in ;

• V e c to r

• in p u t[ ] ;

• E x a m p le : in p u t[1 5 :0 ] A , B , d a ta ;

• O u tp ut D e c la ra t io n
• S c a la r E x a m p l e : o u tp u t c _o u t, O V , M IN U S ;

• V e c to r E x a m p le : o u tp u t[7 :0 ] A C C , R E G _IN , d a t a _o ut;

 Types verilog coding
• Behavioral

■ P ro c e d ura l c o d e , sim ila r to C p ro g r a m m in g

■ L ittl e st ruc tura l d e ta il (e x c e p t m o d u le inte rc o n ne c t)

• Dataflow

■ S p e c if ie s tra ns f e r o f d a ta b e tw e e n re g iste rs

■ S o m e s truc tur a l in f o rm a tio n is a v a ila b le ( R T L )

■ S o m e tim e s sim ila r to b e h a v io r

• Structural (gate,switch)

■ Inte rc o n ne c tio n o f sim p l e c o m p o n e n ts

■ P ure ly s tru c tu ra l
Hierarchical Design

E.g.
 Module

m o d u le m y _ m o d u le ( o u t1 , .., in N ) ;

in1 my_module out1 o u tp u t o u t1 , .., o u tM ;

in2 out2 in p u t in 1 , .., in N ;

f .. / / d e c l a ra tio n s

inN outM .. / / d e s c rip tio n o f f (m a y b e

.. / / s e q u e n tia l)

e n d m o d u le

E v eryth in g yo u w rite in Ve rilo g m u s t b e in s id e a m o d u le

ex c e p tio n : c o m p ile r d ire c tiv es
 VERILOG coding for all gate
m o d u le g a te s (a , b , y1 , y 2 , y 3 , y 4 , y 5 , y6 , y7 ) ;
in p u t [3 :0 ] a , b ;
o u tp u t [3 :0 ] y 1 , y 2 , y3 , y4 , y5 , y 6 , y 7 ;
/* S e v e n d iffe re n t lo g ic g a tes a c tin g o n fo u r b it
b u s s es */
a s s ig n y 1 = ~ a ; // N O T g a te
a s s ig n y 2 = a & b ; / / A N D g a te
a s s ig n y 3 = a | b ; / / O R g a te
a s s ig n y 4 = ~ (a & b ); / / N A N D g a te
a s s ig n y 5 = ~ (a | b ) ; / / N O R g a te
a s s ig n y 6 = a ^ b ; / / X O R g a te
a s s ig n y 7 = ~ (a ^ b ); / / X N O R g a te
e n d m o d u le
 Example: Half Adder

A
S

B
m o d ule h a lf_ a d d er(S , C , A , B );
C o u tp ut S , C ;
in p u t A , B ;
a s s ig n S = A ^ B ;
a s s ig n C = A & B ;
A S
en d m o d u le

B C
 Example: Full Adder
in1 A S I1 A S sum

in2 B C I2 B C I3
cout

cin

modul e f ul l _ adder ( s um, cout , i n1, i n2, ci n) ;

out put sum, cout ;
i nput i n1, i n2, ci n;

wi r e I 1, I 2, I 3;
Module Instance
name hal f _ adder ha1( I 1, I 2, i n1, i n2) ; name
hal f _ adder ha2( s um, I 3, I 1, ci n) ;

as si gn cout = I 2 | | I 3;

endmodul e
 Example
• 4 -b it a d d e r
m o d ule a d d 4 ( s,c 3,c i,a ,b)
in p ut [3 :0 ] a ,b ; // p o rt d e c la ra tio n s
in p ut c i ;
o utp ut [3 :0 ] s : // v ec to r Simpler than VHDL
o utp ut c 3 ; Only Syntactical
w ire [2 :0 ] c o ; Difference
f ul l _ adder a 0 (s [0 ], c o [0 ], a [0 ], b [0 ], c i) ;
f ul l _ adder a 1 (s [1 ], c o [1 ], a [1 ], b [1 ], c o [0 ]) ;
f ul l _ adder a 2 (s [2 ], c o [2 ], a [2 ], b [2 ], c o [1 ]) ;
f ul l _ adder a 3 (s [3 ], c 3 , a [3 ], b [3 ], c o [2 ]) ;
e nd m o d ule

c3 a3 a2 a1 a0 ci
 Assignments

• C o ntin uo us a ssig nm e nts a ss ig n va lu e s to n ets (v ec to r a nd sc a la r)

– Th e y a re trig g e re d w h e ne v er s im ula tio n c a u se s the v a lu e o f the
rig ht-ha nd s id e to c ha ng e

– K ey w o rd “ a s sig n ”

e .g . o ut = in1 & in2 ;

• P ro c e d ura l a s sig n m en ts d riv e v a lue s o nto re g iste rs (ve c to r a nd

sc a la r)

– T h e y O c c u r w ith in proc e d u re s su c h a s a nd

– T h e y a re trigg e re d w h e n th e flo w o f e x e cu tio n re a c h e s th e m (lik e in C )

– B lo c king a n d N on -B lo ck ing pro c e du ra l a s sig nm e nts

 Assignments (cont.)

• P ro c e d u ra l A ssig n m e n ts
– Blocking assignment s ta t em e n t ( = op e ra to r) a c t s m u c h
lik e in t ra d itio n a l p ro g ra m m in g la n g u a g e s . T h e w h o le

s ta tem e n t is d o n e b e fo re c o n t ro l p a s s e s o n t o t h e n e xt

s ta tem e n t

– Nonblocking a s s ig n m en t s t a te m e n t ( <= o p e ra t or)

e v a lu a tes a ll t h e rig h t -h a n d s id e s fo r th e c u rre n t tim e

u n it a n d a s s ig n s th e left-h a n d s id es a t t h e e n d o f th e

tim e u n it
 Delay based Timing Control

• Delay Control (#)

– E x p re ss io n s p e c if ie s th e tim e d ura tio n b e t w e e n i nitia lly e n c o u n te rin g
th e s ta t e m e nt a n d w h e n the sta te m e n t a c tu a lly e x e c u te s .

– D e la y in P r o c e d u ra l A s si g nm e n ts
• In te r-S ta te m e n t D e l a y
• In tra -S ta te m e n t D e la y

– F o r e x a m p le :
• In te r-S ta te m e n t D e l a y

#10 A = A + 1 ;
• In tra -S ta te m e n t D e la y

A = #1 0 A + 1 ;
 Example: Half Adder,
2nd Implementation

A
S
m o d ule ha lf_ a d d e r(S , C , A , B );
B
o utp ut S , C ;
C
in p ut A , B ;

x o r # 2 (S , A , B );

a n d # 1 ( C , A , B );
A ss um in g :
• X O R : 2 t.u. d e la y e nd m o d ule
• A N D : 1 t.u. de la y
 Combinational Circuit Design
• O u tp u ts a re fu n c tio n s o f in p u ts

c om b.
in p u ts c irc u its O u tp u ts

• E x a m p les
– M UX
– decoder
– p rio rity e n c o d e r
– add er
Procedural Statements: if
E .g . 4 -to-1 m ux :
m o d u le m u x4 _ 1( o u t, in , se l) ;
o u tp u t o u t;
if (e xp r1 ) in p u t [3 :0 ] in ;
tru e_s t m t1 ; in p u t [1 :0 ] s e l;

re g o u t;
e ls e if (ex p r2 ) w ire [3 : 0 ] in ;
w ire [1 : 0 ] s e l;
tru e_s t m t2 ;
.. a lw a y s @ ( in o r s e l)
if ( se l = = 0 )
e ls e o u t = in [0 ];
d e f_ s tm t ; e ls e if (s e l = = 1 )
o u t = in [1 ];
e ls e if (s e l = = 2 )
o u t = in [2 ];
e ls e
o u t = in [3 ];
e n d m o d u le
 Procedural Statements: case
E .g . 4 -to-1 m ux :
modul e mux 4_ 1( out , i n, s el ) ;
c a s e (e xp r) out put out ;
i nput [ 3: 0] i n;
i nput [ 1: 0] sel ;
ite m _1 , .., it em _n : s tm t 1 ;
r eg out ;
ite m _n + 1 , .., it em _m : s tm t 2 ; wi r e [ 3: 0] i n;
.. wi r e [ 1: 0] s el ;

d e fa u lt: d e f_ s tm t ; al way s @( i n or s el )
case ( s el )
0: out = i n[ 0] ;
e nd ca se 1: out = i n[ 1] ;
2: out = i n[ 2] ;
3: out = i n[ 3] ;
endcas e
endmodul e
2 BIT MAGNITUDE COMPARATOR

m o d ule m ag (a ,b ,x,y,z);

in p u t [1 :0 ]a ,b ;

o u tp ut x,y,z;

w ire [1 :0 ]w ;

a s s ig n w [1 ]= (~ a [1 ]& ~ b [1 ])|(a[ 1 ]& b [1 ]);

a s s ig n w [0 ]= (~ a [0 ]& ~ b [0 ])|(a[ 0 ]& b [0 ]);

a s s ig n x = w [1 ]& w [ 0 ];

a s s ig n y =(a [1 ] & ~ b [1 ])|(w [1 ]& a[ 0 ]& ~ b [0 ]);

a s s ig n z = (~ a [1 ] & b [1 ])|(w [1 ] & ~ a[ 0 ]& b [0 ]);

en d m o d u le
 2 BIT MAGNITUDE COMPARATOR

m o d ule c o m p a ra to r_ 2 bit ( a ,b ,e q ua l ,g re a te r ,lo w e r );

o utp ut e q ua l ;

o utp ut g rea te r ;
o utp ut low e r ;
in p ut [1 :0 ] a ;

in p ut [1 :0 ] b ;
a s sig n e q ua l = (a == b ) ? 1 : 0 ;

a s sig n g re a te r = (a >b ) ? 1 : 0 ;
a s sig n lo w e r = (a < b ) ? 1 : 0 ;
e nd m o d ule
 Simulation

• S im u la tio n is th e p ro c e s s o f v e rifyin g th e
fu n c tio n a l c h a ra c te ris tic s o f m o d e ls a t a n y
lev els o f m o d e lin g . W e u s e s im u la to rs to
s im u la te th e h a rd w a re m o d e ls .

• T o tes t if th e R T L c o d e m e ets th e fu n c tio n a l

re q u ire m e n ts o f th e s p e c ific a tio n , S e e if a ll th e
R T L B lo c k s a re fu n c tio n a lly c o rre c t.
 Synthesis

• Synthesis is a p ro c e ss in w h ic h a d e s ig n
b e h a v io r th a t is m o d e le d u s in g a H D L is

tra n s la te d in to an im p le m e n ta tio n

c o n sistin g of lo g ic g a te s. T h is is d o n e b y a

sy n th e sis to o l w h ic h is a n o th e r so ftw a re

p rog ra m .