STM32F777xx STM32F778Ax

STM32F779xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 2MB flash/
512+16+4KB RAM, crypto, USB OTG HS/FS, 28 com IF, LCD, DSI
Datasheet - production data

Features
• Includes ST state-of-the-art patented
technology
• Core: Arm® 32-bit Cortex®-M7 CPU with
LQFP100 (14 × 14 mm) UFBGA176 (10 x 10 mm) WLCSP180
DPFPU, ART Accelerator and L1-cache:
LQFP144 (20 × 20 mm) (0.4 mm pitch)
16 Kbytes I/D cache, allowing 0-wait state TFBGA216 (13 x 13 mm)
execution from embedded flash memory and LQFP176 (24 × 24 mm)
TFBGA100 (8 x 8 mm)
external memories, up to 216 MHz, MPU, LQFP208 (28 x 28 mm)
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions. – 32 kHz oscillator for RTC with calibration
• Memories – Internal 32 kHz RC with calibration
– Up to 2 Mbytes of flash memory, organized • Low-power
into two banks allowing read-while-write – Sleep, Stop and Standby modes
– SRAM: 512 Kbytes (including 128 Kbytes – VBAT supply for RTC, 32×32 bit backup
of data TCM RAM for critical real-time data) registers + 4 Kbytes backup SRAM
+ 16 Kbytes of instruction TCM RAM (for • 3×12-bit, 2.4 MSPS ADC: up to 24 channels
critical real-time routines) + 4 Kbytes of
backup • Digital filters for sigma delta modulator
(DFSDM), 8 channels / 4 filters
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM, • 2×12-bit D/A converters
SDRAM/LPSDR SDRAM, NOR/NAND • General-purpose DMA: 16-stream DMA
memories controller with FIFOs and burst support
• Dual mode Quad-SPI • Up to 18 timers: up to thirteen 16-bit (1x low-
• Graphics power 16-bit timer available in Stop mode) and
– Chrom-ART Accelerator (DMA2D), two 32-bit timers, each with up to four
graphical hardware accelerator enabling IC/OC/PWM or pulse counter and quadrature
enhanced graphical user interface (incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
– Hardware JPEG codec
timer
– LCD-TFT controller supporting up to XGA
resolution • Debug mode
– MIPI® DSI host controller supporting up to – SWD and JTAG interfaces
720p 30 Hz resolution – Cortex®-M7 Trace Macrocell™
• Clock, reset and supply management • Up to 168 I/O ports with interrupt capability
– 1.7 to 3.6 V application supply and I/Os – Up to 164 fast I/Os up to 108 MHz
– POR, PDR, PVD and BOR – Up to 166 5 V-tolerant I/Os
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)

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 STM32F777xx STM32F778Ax STM32F779xx

• Up to 28 communication interfaces • Advanced connectivity

– Up to four I2C interfaces (SMBus/PMBus) – USB 2.0 full-speed device/host/OTG
– Up to four USARTs/4 UARTs (12.5 Mbit/s, controller with on-chip PHY
ISO7816 interface, LIN, IrDA, modem – USB 2.0 high-speed/full-speed
control) device/host/OTG controller with dedicated
– Up to six SPIs (up to 54 Mbit/s), three with DMA, on-chip full-speed PHY and ULPI
muxed simplex I2S for audio – 10/100 Ethernet MAC with dedicated DMA:
– 2 x SAIs (serial audio interface) supports IEEE 1588v2 hardware, MII/RMII
– 3 × CANs (2.0B Active) and 2x SDMMCs • 8- to 14-bit camera interface, up to 54 Mbyte/s
– SPDIFRX interface • Cryptographic acceleration: hardware
– HDMI-CEC acceleration for AES 128, 192, 256, triple DES,
– MDIO slave interface HASH (MD5, SHA-1, SHA-2), and HMAC
• True random number generator (RNG).
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
• All packages are ECOPACK2 compliant

Table 1. Device summary

Reference Part number

STM32F777xx STM32F777BI, STM32F777II, STM32F777NI, STM32F777VI, STM32F777ZI

STM32F778Ax STM32F778AI
STM32F779xx STM32F779AI, STM32F779BI, STM32F779II, STM32F779NI

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Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 36
3.20 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 36
3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.23.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.23.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 43
3.26 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 44
3.27 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.29 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.30 Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.31 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 46
3.32 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 46
3.33 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 47
3.35 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 47
3.36 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 49
3.39 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.40 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.41 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.42 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.43 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 50
3.44 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.45 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.46 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.47 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.48 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 112
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . 112
6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 112
6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 143
6.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 155
6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

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6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.32 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 212
6.3.33 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 213
6.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 215
6.3.35 DFSDM timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 218

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.2 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.3 TFBGA100 package information (A08Q) . . . . . . . . . . . . . . . . . . . . . . . . 224
7.4 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.5 LQFP176 package information (1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.6 UFBGA(176+25) package information (A0E7) . . . . . . . . . . . . . . . . . . . . 235
7.7 WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
7.8 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
7.9 TFBGA216 package information (A0L2) . . . . . . . . . . . . . . . . . . . . . . . . 243
7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 250

A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts . . . . . 17
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 33
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 9. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and
ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 12. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 111
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 112
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 112
Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON),
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled),
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode), regulator ON . . . . . . . . . . . . . . . . . . . . . . 119
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode) on ITCM interface (ART disabled),
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode) on ITCM interface (ART disabled),
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 32. Typical and maximum current consumption in Run mode, code with data processing

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List of tables STM32F777xx STM32F778Ax STM32F779xx

running from flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 33. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 123
Table 34. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 124
Table 35. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 124
Table 36. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 125
Table 37. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 126
Table 38. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 39. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 43. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 45. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 47. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 48. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 49. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 50. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 51. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP
transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 53. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 54. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 55. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 56. Flash memory programming (single bank configuration
nDBANK=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 57. Flash memory programming (dual bank configuration
nDBANK=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 58. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 59. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 60. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 61. EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 1). . . . . . . . . . . . . . . 154
Table 62. EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 2). . . . . . . . . . . . . . . 154
Table 63. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 64. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 65. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 66. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 67. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 68. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 69. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 70. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 71. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 72. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 73. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 74. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 75. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 166
Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 167
Table 78. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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Table 80. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 81. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 82. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 83. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 84. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 85. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 86. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 87. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 88. Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 89. Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 90. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 91. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 92. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 93. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 94. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 95. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 96. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 97. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 98. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 99. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 100. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 192
Table 102. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 192
Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 193
Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 194
Table 105. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 106. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 195
Table 107. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 197
Table 109. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 110. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 111. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 112. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 113. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 114. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 115. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 116. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 118. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 119. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 120. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 121. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 122. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 123. DFSDM measured timing 1.71-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 124. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 219
Table 125. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 219
Table 126. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 127. TFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 128. TFBGA100 - Example of PCB design rules (0.8 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 226
Table 129. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 130. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 131. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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Table 132. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 236
Table 133. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 134. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules
(0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 135. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 136. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 137. TFBGA216 - Example of PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . 246
Table 138. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 139. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 140. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 250
Table 141. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

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List of figures

Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. STM32F777xx, STM32F778Ax and STM32F779xx block diagram . . . . . . . . . . . . . . . . . 20
Figure 3. STM32F777xx, STM32F778Ax and STM32F779xx AXI-AHB
bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 31
Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1,VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1,VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. STM32F77xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12. STM32F77xxx TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13. STM32F77xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. STM32F77xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 15. STM32F779xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. STM32F77xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 17. STM32F779Ax/STM32F778Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18. STM32F77xxx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 19. STM32F779xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 20. STM32F77xxx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 21. STM32F779xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 24. STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . 106
Figure 26. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 27. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 28. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 29. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 30. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 31. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 32. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 33. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 34. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 35. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 36. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 37. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 38. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 39. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 40. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 41. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 42. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 169
Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 169

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13
List of figures STM32F777xx STM32F778Ax STM32F779xx

Figure 45. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 46. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 47. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 48. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 49. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 50. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 51. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 52. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 53. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 54. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 55. USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 185
Figure 56. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 57. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 58. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 59. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 60. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 191
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 193
Figure 63. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 64. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 65. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 66. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 67. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 68. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 71. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 72. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 73. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 74. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 78. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 79. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 80. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 81. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 82. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 83. TFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 84. TFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 85. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 86. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 87. LQFP176 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 88. LQFP176 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 89. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 90. UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 91. WLCSP 180-bump, 5.5 x 6 mm, 1.27 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 92. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 93. WLCSP180 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 94. LQFP208 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

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Figure 95. LQFP208 - footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 96. TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 97. TFBGA216 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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13
Introduction STM32F777xx STM32F778Ax STM32F779xx

1 Introduction

This document provides information on STM32F777xx, STM32F778Ax and STM32F779xx

microcontrollers, such as description, functional overview, pin assignment and definition,
electrical characteristics, packaging, and ordering information.
This document must be read in conjunction with the reference manual (RM0410) and the
device errata sheet (ES0334), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32F777xx STM32F778Ax STM32F779xx Description

2 Description

The STM32F777xx, STM32F778Ax and STM32F779xx devices are based on the high-
performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The
Cortex®-M7 core features a floating point unit (FPU), which supports Arm® double-precision
and single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU), which enhances the
application security.
The STM32F777xx, STM32F778Ax and STM32F779xx devices incorporate high-speed
embedded memories with a flash up to 2 Mbytes, 512 Kbytes of SRAM (including
128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM
(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power
modes, and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses, a 32-bit multi-AHB bus matrix, and a multi layer AXI interconnect
supporting internal and external memories access.
The devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
a true random number generator (RNG), and a cryptographic acceleration cell. They also
feature standard and advanced communication interfaces.
• Up to four I2Cs.
• Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
• Four USARTs plus four UARTs.
• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI).
• Three CANs.
• Two SAI serial audio interfaces.
• Two SDMMC host interfaces.
• Ethernet and camera interfaces.
• LCD-TFT display controller.
• Chrom-ART Accelerator.
• SPDIFRX interface.
• HDMI-CEC.
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI flash memory interface, a camera interface for CMOS sensors and a
cryptographic acceleration cell.
The STM32F777xx, STM32F778Ax and STM32F779xx devices operate in the –40 to
+105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for
USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available
on all the packages except LQFP100 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.

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54
Description STM32F777xx STM32F778Ax STM32F779xx

The STM32F777xx, STM32F778Ax and STM32F779xx devices offer devices in 11

packages ranging from 100 pins to 216 pins. The set of included peripherals changes with
the device chosen.
These features make the STM32F777xx, STM32F778Ax and STM32F779xx
microcontrollers suitable for a wide range of applications.
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smartwatches
The following table lists the peripherals available on each part number.

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 STM32F777xx STM32F778Ax STM32F779xx
Table 2. STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts
Peripherals STM32F77xVx STM32F77xZx STM32F779Ax STM32F778Ax STM32F77xIx STM32F77xBx STM32F77xNx

Flash memory in Kbytes 1024 2048 1024 2048 1024 2048 2048 1024 2048 1024 2048 1024 2048

System 512(368+16+128)

SRAM in Kbytes Instruction 16

Backup 4

FMC memory controller Yes(1)

Quad-SPI Yes

Ethernet Yes No Yes

General-purpose 10

Advanced-control 2
Timers
Basic 2

Low-power 1
DS11243 Rev 7

Random number generator Yes

SPI / I2S 4/3 (simplex)(2) 6/3 (simplex)(2)

I2C 4

USART/UART 4/4

USB OTG FS Yes

USB OTG HS Yes

Communication
interfaces
CAN 3

SAI 2

SPDIFRX 4 inputs

SDMMC1 Yes

SDMMC2 Yes(3)

Camera interface Yes

MIPI-DSI Host(4) No Yes

LCD-TFT Yes

Description
Chrom-ART Accelerator™ (DMA2D) Yes
17/255

JPEG codec Yes

Cryptography Yes
 Table 2. STM32F777xx, STM32F778Ax and STM32F779xx features and peripheral counts (continued)
18/255

Description
Peripherals STM32F77xVx STM32F77xZx STM32F779Ax STM32F778Ax STM32F77xIx STM32F77xBx STM32F77xNx

GPIOs 82 114 128 132 159

DFSDM1 Yes (4 filters)

12-bit ADC 3

Number of channels 16 24

12-bit DAC Yes

Number of channels 2

Maximum CPU frequency 216 MHz(5)

Operating voltage 1.7 to 3.6 V(6)

Ambient temperatures: –40 to +85 °C /–40 to +105 °C(7)

Operating temperatures
Junction temperature: –40 to + 125 °C

LQFP100 UFBGA176(8)
Package LQFP144 WLCSP180 LQFP208 TFBGA216
TFBGA100 LQFP176
DS11243 Rev 7

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package.
4. DSI host interface is only available on STM32F779x sales types.
5. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range).

STM32F777xx STM32F778Ax STM32F779xx

6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.18.2: Internal reset OFF).
7. The range -40° to +105°C is not available for WLCSP packages.
8. UFBGA176 is not available for STM32F779x sales types.
STM32F777xx STM32F778Ax STM32F779xx Description

Full compatibility throughout the family

The STM32F777xx, STM32F778Ax and STM32F779xx devices are fully pin-to-pin,

compatible with the STM32F4xxxx devices, allowing the user to try different peripherals,
and reaching higher frequency for a greater degree of freedom during the development
cycle.
Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx
families.

Figure 1. Compatible board design for LQFP100 package

STM32F427xx / STM32F437xx
STM32F429xx / STM32F439xx
STM32F415xx / STM32F417xx
PC3 18 STM32F405xx / STM32F407xx
VDD 19
VSSA 20
VREF+ 21
VDDA 22
PA0-WKUP 23
PA1 24
PA2 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PE12

VCAP1
PE13
PE14

PB10
PE15
PE11
VDD

PB11
VSS

VDD
PA3

PC4
PC5

PB1
PB2

PE7
PA4
PA5

PB0

PE10
PA7

PE8
PA6

PE9
PC3 18 STM32F77xxx
VSSA 19
VREF+ 20
VDDA 21
PA0-WKUP 22
PA1 23 Pins 19 to 49 are not compatible
PA2 24
PA3 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

VCAP1
PE12

PE13

PB11
PE10

PE14

PB10
PE11

PE15

VDD
VSS
VDD

PA4
VSS

PC4

PC5

PB1

PE7

PE9
PB2

PE8
PA5

PB0
PA7
PA6

MSv39145V1

The STM32F77x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are

fully pin to pin compatible with STM32F4xx devices.

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54
Description STM32F777xx STM32F778Ax STM32F779xx

Figure 2. STM32F777xx, STM32F778Ax and STM32F779xx block diagram

JTRST, JTDI, JTAG & SW MPU FPU

JTCK/SWCLK

FIFO FIFO FIFO

ETM NVIC 3DES,
JTDO/SWD, JTDO DTCM RAM 128KB
DTCM AES256
TRACECK Arm CPU ICTM ITCM RAM 16KB HASH
TRACED[3:0] Cortex-M7

AHB2AXI
I-Cache AXIM FLASH 1MB
ACCEL/
JPEG
16KB
CACHE FLASH 1MB
D-Cache AHBP RNG
216MHz
16KB HSYNC, VSYNC

FIFO
AHBS Camera PUIXCLK, D[13:0]

11S8M
SRAM1 368KB ITF

8S7M
DP
MII or RMII as AF Ethernet MAC DMA/

FIFO
USB DM
SRAM2 16 KB

PHY
MDIO as AF FIFO SCL, SDA, INT, ID, VBUS

AHB bus-matrix
10/100

AHB BUS-MATRIX
AHB2 216 MHZ OTG FS CLK, NE [3:0], A[23:0],
USB DMA/ D[31:0], NOEN, NWEN,
DP, DM
PHY

EXT MEM CTL (FMC) NBL[3:0], SDCLKE[1:0], SDNE[1:0],

ULPI:CK, D[7:0], DIR, STP, NXT OTG HS FIFO
SRAM, SDRAM, NOR-Flash, SDNWE, NL
SCL/SDA, INT, ID, VBUS NAND-Flash, SDRAM NRAS, NCAS, NADV
GP-DMA2 8 Streams NWAIT, INTN
FIFO Quad-SPI
CLK, CS,D[7:0]
8 Streams @VDDA
GP-DMA1 AHB1 216 MHz POR
FIFO SUPPLY
reset SUPERVISION
LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], POR/PDR
LCD-TFT FIFO Int
LCD_HSYNC, LCD_VSYNC, LCD_DE, BOR VDDA, VSSA
LCD_CLK PVD NRESET
@VDDA
CHROM-ART
FIFO WKUP[4:0]
(DMA2D) RC HS @VDD33
VDDMMC33 = 1.8 to 3.6V
VDD12 BBgen + POWER MNGT
RC LS VDDUSB33 = 3.0 to 3.6 V
PA[15:0] GPIO PORT A
VOLT. REG VDD = 1.8 to 3.6 V

PWRCTRL
PLL1+PLL2+PLL3
PB[15:0] 3.3V TO 1.2V VSS
GPIO PORT B
VCAP1
PC[15:0] GPIO PORT C @VDD33
XTAL OSC OSC_IN
PD[15:0] GPIO PORT D 4- 16MHz OSC_OUT

PE[15:0] RCC WDG32K

GPIO PORT E Reset
M & control
GT

GPIO PORT F
Standby VBAT = 1.8 to 3.6 V
PF[15:0]
interface
PG[15:0] @VSW
GPIO PORT G
AHB1PCLK
APBP1CLK
APBP2CLK

AHB2PCLK

OSC32_IN
HCLK
FCLK

XTAL 32 kHz OSC32_OUT

PH[15:0]

LS
GPIO PORT H
RTC RTC_TS
PI[15:0] AWU RTC_TAMPx
GPIO PORT I
Backup register RTC_OUT
PJ[15:0] GPIO PORT J
CRC LS 4 KB BKPRAM

PK[7:0] GPIO PORT K TIM2 32b 4 channels, ETR as AF

TIM3 16b 4 channels, ETR as AF

168 AF EXT IT. WKUP
D[7:0] GPDMA2 GPDMA1 TIM4 16b 4 channels, ETR as AF
FIFO FIFO

SDMMC1
CMD, CK as AF
D[7:0] SDMMC2 AHB/APB2 AHB/APB1 TIM5 32b 4 channels
CMD, CK as AF
4 compl. chan. (TIM1_CH1[1:4]N), TIM12 16b 2 channels as AF
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF TIM1 / PWM 16b

4 compl. chan.(TIM8_CH1[1:4]N), TIM8 / PWM 16b TIM13 16b 1 channel as AF

4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF
2 channels as AF TIM9 16b TIM14 16b 1 channel as AF
1 channel as AF TIM10 16b smcard RX, TX, SCK
USART2 irDA CTS, RTS as AF
1 channel as AF
APB2 108 MHz (max)

TIM11 16b
WWDG
smcard smcard RX, TX, SCK
RX, TX, SCK, USART1 USART3
CTS, RTS as AF irDA irDA CTS, RTS as AF
RX, TX, SCK, smcard UART4 RX, TX as AF
USART6
CTS, RTS as AF irDA LPTIM1 16b RX, TX as AF
UART5
MOSI, MISO,
SPI1/I2S1
10 MHz
A P B(max)

SCK, NSS as AF UART7 RX, TX as AF

3

MOSI, MISO, SPI4

SCK, NSS as AF UART8 RX, TX as AF
APB1 54 MHz

MOSI, MISO, SPI5 MOSI, MISO, SCK

SCK, NSS as AF TIM6 16b SPI2/I2S2
SPI6 NSS as AF
MOSI, MISO,
SCK, NSS as AF TIM7 16b SPI3/I2S3
MOSI, MISO, SCK
NSS as AF
FIFO FIFO

SD, SCK, FS, MCLK as AF SAI1

I2C1/SMBUS SCL, SDA, SMBAL as AF
Digital filter

SD, SCK, FS, MCLK as AF SAI2

I2C2/SMBUS SCL, SDA, SMBAL as AF
CKIN[7:0]
DATAIN[7:0] SYSCFG
DFSDM SCL, SDA, SMBAL as AF
CKOUT I2C3/SMBUS
CKIN[7:0] MDIO Slave
DATAIN[7:0] I2C4/SMBUS SCL, SDA, SMBAL as AF
CKOUT @VDDA bxCAN1 TX, RX
FIFO

VDDREF_ADC U STemperature
AR T 2 M Bsensor
ps DSI HOST bxCAN2
@VDDA TX, RX
8 analog inputs common
ADC1 bxCAN3 TX, RX
to the 3 ADCs PLL LDO DAC1
ITF
@VDDA

8 analog inputs common ADC2

DSI PHY DAC2 SPDIFRX SPDIFRX[3:0] as AF
to the ADC1 & 2 IF
IF
ADC3
8 analog inputs for ADC3 HDMI-CEC HDMI_CEC as AF

DSI_DOP/N, DSI_D1P/N
DSI_VCAP, DSI_CKP/N DAC1 DAC2
DSI_VDD12, DSI_VSS, DSI_TE as AF as AF as AF
MSv41053V2

1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

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3 Functional overview

3.1 Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
– Six-stage dual-issue pipeline
– Dynamic branch prediction
– Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
– 64-bit AXI4 interface
– 64-bit ITCM interface
– 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
• Tightly Coupled Memory (TCM) interface.
• Harvard instruction and data caches and AXI master (AXIM) interface.
• Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow an efficient signal processing
and a complex algorithm execution.
It supports single and double precision FPU (floating point unit), speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F77xxx family.
Note: The Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

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3.3 Embedded flash memory

The STM32F777xx, STM32F778Ax and STM32F779xx devices embed a flash memory of
up to 2 Mbytes available for storing programs and data. The flash interface features:
• Single /or Dual bank operating modes,
• Read-While-Write (RWW) in Dual bank mode.

3.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

3.5 Embedded SRAM

All the devices feature:
• System SRAM up to 512 Kbytes:
– SRAM1 on AHB bus Matrix: 368 Kbytes
– SRAM2 on AHB bus Matrix: 16 Kbytes
– DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for
critical real-time data.
• Instruction RAM (ITCM-RAM) 16 Kbytes:
– It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at
CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.

3.6 AXI-AHB bus matrix

The STM32F777xx, STM32F778Ax and STM32F779xx system architecture is based on 2
sub-systems:
• An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI to 32-bit AHB bridges connected to AHB bus matrix
– 1x AXI to 64-bit AHB bridge connected to the embedded flash memory
• A multi-AHB Bus-Matrix
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (flash memory, RAM,

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FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.

Figure 3. STM32F777xx, STM32F778Ax and STM32F779xx AXI-AHB

bus matrix architecture(1)
DTCM

ITCM

AHBS

GP GP MAC USB OTG LCD-TFT Chrom-ART

Accelerator
Arm Cortex-M7 DMA1 DMA2 Ethernet HS (DMA2D)

ETHERNET_M

USB_HS_M
DMA_MEM2
DMA_P2
DMA_MEM1

DMA2D
LCD-TFT_M
DMA_PI

16KB DTCM RAM

I/D Cache 128KB
AXIM

AHBP

ITCM RAM
16KB
AXI to
multi-AHB

ITCM

ART
FLASH
64-bit AHB 2MB

64-bit BuS Matrix

SRAM1
368KB
SRAM2
16KB
AHB APB1
periph1
AHB
periph2
FMC external APB2
MemCtl
QuadSPI

32-bit Bus Matrix - S

MSv39103V2
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.

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3.7 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and the transfer sizes
between the source and the destination are independent.
The DMA can be used with the main peripherals:
• SPI and I2S
• I2C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDMMC
• Cryptographic acceleration
• Camera interface (DCMI)
• ADC
• SAI
• SPDIFRX
• Quad-SPI
• HDMI-CEC
• JPEG codec
• DFSDM1

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3.8 Flexible memory controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:
• The NOR/PSRAM memory controller
• The NAND/memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (4 memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.

3.9 Quad-SPI memory interface (QUADSPI)

All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI flash memories. It can work in:
• Direct mode through registers
• External flash status register polling mode
• Memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either
in Single Data Rate or Dual Data Rate.

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3.10 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events

3.11 Chrom-ART Accelerator (DMA2D)

The Chrom-Art Accelerator (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion
Various image format codings are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.

3.12 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.

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3.13 JPEG codec (JPEG)

The JPEG codec provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Stallable design
• Support for single, greyscale component
• Functionality to enable/disable header processing
• Internal register interface
• Fully synchronous design
• Configured for high-speed decode mode

3.14 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 25 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.

3.15 Clocks and startup

On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.

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The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.

3.16 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
• All flash address space mapped on ITCM or AXIM interface
• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the flash memory
through a serial interface. Refer to STM32 microcontroller system memory boot mode
application note (AN2606) for details.

3.17 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 3.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
• VDDSDMMC can be connected either to VDD or an external independent power supply
(1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when
the device is powered at 1.8V, an independent power supply 2.7V can be connected to
VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is
independent from VDD or VDDA but it must be the last supply to be provided and the first
to disappear. The following conditions VDDSDMMC must be respected:
– During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always
lower than VDD
– The VDDSDMMC rising and falling time rate specifications must be respected
– In operating mode phase, VDDSDMMC could be lower or higher than VDD:
All associated GPIOs powered by VDDSDMMC are operating between
VDDSDMMC_MIN and VDDSDMMC_MAX.
• VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the
device is powered at 1.8V, an independent power supply 3.3V can be connected to
VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent
from VDD or VDDA but it must be the last supply to be provided and the first to

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disappear. The following conditions VDDUSB must be respected:

– During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower
than VDD
– The VDDUSB rising and falling time rate specifications must be respected
– In operating mode phase, VDDUSB could be lower or higher than VDD:
- If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supply both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.

Figure 4. VDDUSB connected to VDD power supply

VDD

VDD_MAX

VDD= VDDA = VDDUSB

VDD_MIN

Power-down time
Power-on Operating mode

MS37591V1

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Figure 5. VDDUSB connected to external power supply

VDDUSB_MAX
USB functional area
VDDUSB

VDDUSB_MIN
USB non USB non
functional VDD = VDDA functional
area area
VDD_MIN

Power-down time
Power-on Operating mode

MS37590V1

The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
• VDDDSI is an independent DSI power supply dedicated for DSI Regulator and
MIPI D-PHY. This supply must be connected to global VDD.
• The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected
externally to VDD12DSI.
• The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data
lanes pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.
• The VSSDSI pin is an isolated supply ground used for DSI sub-system.
• If the DSI functionality is not used at all, then:
– The VDDDSI pin must be connected to global VDD.
– The VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
– The VSSDSI pin must be grounded.

3.18 Power supply supervisor

3.18.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through

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option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

3.18.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 6: Power supply supervisor interconnection with internal
reset OFF.

Figure 6. Power supply supervisor interconnection with internal reset OFF

VDD

External VDD power supply supervisor

Ext. reset controller active when

VDD < 1.7 V

Application reset
NRST signal

PDR_ON
VDD

VSS

MS31383V4

The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.

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Figure 7. PDR_ON control with internal reset OFF

V DD

PDR = 1.7 V

time

Reset by other source than

power supply supervisor

NRST

PDR_ON PDR_ON time

MS19009V7

3.19 Voltage regulator

The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF

3.19.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).

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• LPR is used in the Stop modes:

The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin.
All packages have the regulator ON feature.

Table 3. Voltage regulator configuration mode versus device operating mode(1)

Voltage regulator
Run mode Sleep mode Stop mode Standby mode
configuration

Normal mode MR MR MR or LPR -

Over-drive
MR MR - -
mode(2)
Under-drive mode - - MR or LPR -
Power-down
- - - Yes
mode
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.

3.19.2 Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In the regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.

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Figure 8. Regulator OFF

V12
External VCAP_1/2 power
supply supervisor Application reset
Ext. reset controller active signal (optional)
when VCAP_1/2 < Min V12

VDD
PA0 NRST
VDD

BYPASS_REG
V12

VCAP_1

VCAP_2
ai18498V3

The following conditions must be respected:

• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.

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Figure 9. Startup in regulator OFF: slow VDD slope

- power-down reset risen after VCAP_1,VCAP_2 stabilization

VDD

PDR = 1.7 or 1.8 V VCAP_1, VCAP_2

V12
Min V12

time

NRST

PA0

time ai18491g

1. This figure is valid whatever the internal reset mode (ON or OFF).

Figure 10. Startup in regulator OFF mode: fast VDD slope

- power-down reset risen before VCAP_1,VCAP_2 stabilization

VDD

PDR = 1.7 V or 1.8 V

VCAP_1 / VCAP_2
V12
Min V12

time
NRST
PA0 asserted externally

time
ai18492e

1. This figure is valid whatever the internal reset mode (ON or OFF).

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3.19.3 Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF

LQFP100 Yes No
Yes No
LQFP144,
LQFP208

LQFP176,
Yes Yes
UFBGA176, Yes Yes
BYPASS_REG set BYPASS_REG set
TFBGA100, PDR_ON set to VDD PDR_ON set to VSS
to VSS to VDD
TFBGA216

WLCSP180 Yes(1)

1. Available only on dedicated part number. Refer to Section 8: Ordering information.

3.20 Real-time clock (RTC), backup SRAM and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.

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The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator(LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.

3.21 Low-power modes

The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
– Normal mode (default mode when MR or LPR is enabled)
– Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and
LPTIM1 asynchronous interrupt).

Table 5. Voltage regulator modes in stop mode

Voltage regulator
Main regulator (MR) Low-power regulator (LPR)
configuration

Normal mode MR ON LPR ON

Under-drive mode MR in under-drive mode LPR in under-drive mode

• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

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Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.

3.22 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is
no more available and the VBAT pin should be connected to VDD.

3.23 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.

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Table 6. Timer feature comparison

Max Max
DMA Capture/ Complem
Timer Counter Counter Prescaler interface timer
Timer request compare entary
type resolution type factor clock clock
generation channels output
(MHz) (MHz)(1)

Any
Up,
Advanced TIM1, integer
16-bit Down, Yes 4 Yes 108 216
-control TIM8 between 1
Up/down
and 65536
Any
Up,
TIM2, integer
32-bit Down, Yes 4 No 54 108/216
TIM5 between 1
Up/down
and 65536
Any
Up,
TIM3, integer
16-bit Down, Yes 4 No 54 108/216
TIM4 between 1
Up/down
and 65536
Any
integer
TIM9 16-bit Up No 2 No 108 216
between 1
General and 65536
purpose Any
TIM10, integer
16-bit Up No 1 No 108 216
TIM11 between 1
and 65536
Any
integer
TIM12 16-bit Up No 2 No 54 108/216
between 1
and 65536
Any
TIM13, integer
16-bit Up No 1 No 54 108/216
TIM14 between 1
and 65536
Any
TIM6, integer
Basic 16-bit Up Yes 0 No 54 108/216
TIM7 between 1
and 65536
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.

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3.23.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.

3.23.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F77xxx
devices (see Table 6 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F77xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.

3.23.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.

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3.23.4 Low-power timer (LPTIM1)

The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one-shot mode
• Selectable software / hardware input trigger
• Selectable clock source:
• Internal clock source: LSE, LSI, HSI or APB clock
• External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode

3.23.5 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.

3.23.6 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.23.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

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3.24 Inter-integrated circuit interface (I2C)

The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 7. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 kbit/s) X X X X

Fast-mode (up to 400 kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
1. X: supported.

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3.25 Universal synchronous/asynchronous receiver transmitters

(USART)
The devices embed USART. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
• Full-duplex asynchronous communications
• Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
• Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
• A common programmable transmit and receive baud rate of up to 27 Mbit/s when the
USART clock source is system clock frequency (max is 216 MHz) and oversampling by
8 is used.
• Auto baud rate detection
• Programmable data word length (7 or 8 or 9 bits) word length
• Programmable data order with MSB-first or LSB-first shifting
• Programmable parity (odd, even, no parity)
• Configurable stop bits (1 or 1.5 or 2 stop bits)
• Synchronous mode and clock output for synchronous communications
• Single-wire half-duplex communications
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Multiprocessor communications
• LIN master synchronous break send capability and LIN slave break detection capability
• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
• Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard )
• Support for Modbus communication
Table 8 summarizes the implementation of all U(S)ARTs instances

Table 8. USART implementation

features(1) USART1/2/3/6 UART4/5/7/8

Data Length 7, 8 and 9 bits

Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X -

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Table 8. USART implementation (continued)

features(1) USART1/2/3/6 UART4/5/7/8

Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
1. X: supported.

3.26 Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 54 Mbits/s,
SPI2 and SPI3 can communicate at up to 27 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be
served by the DMA controller.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.

3.27 Serial audio interface (SAI)

The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.

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SAI1 and SAI2 can be served by the DMA controller

3.28 SPDIFRX Receiver Interface (SPDIFRX)

The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIFRX are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal is available, the SPDIFRX re-samples the incoming signal, decodes the
manchester stream, recognizes frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that is used to compute the exact sample rate for clock drift algorithms.

3.29 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).

3.30 Audio and LCD PLL (PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.

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3.31 SD/SDIO/MMC card host interface (SDMMC)

SDMMC host interfaces are available, that support the MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller

3.32 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time

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3.33 Controller area network (bxCAN)

The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up
to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM
are dedicated for CAN3.

3.34 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor)
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected

3.35 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface
(ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support

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• Software configurable to OTG1.3 and OTG2.0 modes of operation

• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected

3.36 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.

3.37 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image

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3.38 Management Data Input/Output (MDIO) slaves

The devices embed a MDIO slave interface it includes the following features:
• 32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO Register write
– MDIO Register read
– MDIO protocol error
• Able to operate in and wake up from STOP mode

3.39 Cryptographic acceleration

The devices embed a cryptographic accelerator. This cryptographic accelerator provides a
set of hardware acceleration for the advanced cryptographic algorithms usually needed to
provide confidentiality, authentication, data integrity and non repudiation when exchanging
messages with a peer.
• These algorithms consist of:
Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal hash
– SHA-1 and SHA-2 (secure hash algorithms)
– MD5
– HMAC
The cryptographic accelerator supports DMA request generation.

3.40 Random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.

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54
Functional overview STM32F777xx STM32F778Ax STM32F779xx

3.41 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
A fast I/O handling allows a maximum I/O toggling up to 108 MHz.

3.42 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

3.43 Digital filter for Sigma-Delta Modulators (DFSDM)

The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM
peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to
perform digital filtering of the received data streams (which represent analog value on Σ∆
modulators inputs). The DFSDM can also interface PDM (Pulse Density Modulation)
microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM
features optional parallel data stream inputs from microcontrollers memory (through
DMA/CPU transfers into DFSDM). The DFSDM transceivers support several serial interface
formats (to support various Σ∆ modulators). The DFSDM digital filter modules perform
digital processing according user selected filter parameters with up to 24-bit final ADC
resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– Configurable SPI interface to connect various SD modulator(s)
– Configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– Clock output for SD modulator(s): 0..20 MHz

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STM32F777xx STM32F778Ax STM32F779xx Functional overview

• Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: device memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
– Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• Up to 24-bit output data resolution, signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion triggered by:
– Software trigger
– Internal timers
– External events
– Start-of-conversion synchronously with first digital filter module (DFSDM0)
• Analog watchdog feature:
– Low value and high value data threshold registers
– Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– Input from final output data or from selected input digital serial channels
– Continuous monitoring independently from standard conversion
• Short circuit detector to detect saturated analog input values (bottom and top range):
– Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– Monitoring continuously each input serial channel
• Break signal generation on analog watchdog event or on short circuit detector event
• Extremes detector:
– Storage of minimum and maximum values of final conversion data
– Refreshed by software
• DMA capability to read the final conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority

Table 9. DFSDM implementation

DFSDM features DFSDM1

Number of filters: x (DFSDM_FLTx) 4

Number of input transceivers/channels: y (DFSDM_CHy) 8
Internal ADC parallel input support -
Number of external triggers (JEXTSEL size) 32
ID register support -

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54
Functional overview STM32F777xx STM32F778Ax STM32F779xx

3.44 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with the temperature.
The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.

3.45 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
• Two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.

3.46 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins
could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.

3.47 Embedded Trace Macrocell™

The Arm embedded trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F77xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

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STM32F777xx STM32F778Ax STM32F779xx Functional overview

any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.

3.48 DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
• LTDC interface:
– Used to transmit information in Video mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command mode (DBI).
• APB slave interface:
– Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
– Can operate concurrently with either LTDC interface in either Video mode or
Adapted Command mode.
• Video mode pattern generator:
– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
The DSI Host main features:
• Compliant with MIPI® Alliance standards
• Interface with MIPI® D-PHY
• Supports all commands defined in the MIPI® Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during Video mode
• Supports up to two D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports Ultra Low-power mode with PLL disabled
• ECC and Checksum capabilities
• Support for End of Transmission Packet (EoTp)
• Fault recovery schemes
• 3D transmission support
• Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video Mode interface through LTDC
– Adapted Command mode interface through LTDC
• Independently programmable Virtual Channel ID in

DS11243 Rev 7 53/255

54
Functional overview STM32F777xx STM32F778Ax STM32F779xx

– Video mode
– Adapted Command mode
– APB Slave

Video Mode interfaces features:

• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
• Programmable polarity of all LTDC interface signals
• Maximum resolution is limited by available DSI physical link bandwidth:
– Number of lanes: 2
– Maximum speed per lane: 500 Mbps1Gbps

Adapted interface features

Support for sending large amounts of data through the memory_write_start(WMS) and
memory_write_continue(WMC) DCS commands
• LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB

Video mode pattern generator:

• Vertical and horizontal color bar generation without LTDC stimuli
• BER pattern without LTDC stimuli

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STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

4 Pinouts and pin description

Figure 11. STM32F77xxx LQFP100 pinout

BOOT0

PA15
PA14
PC12
PC11
PC10
VDD

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
PE1
PE0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP2
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13-ANTI_TAMP 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0-WKUP 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE11
PE10

PB10
PB11
PE12

PE14
PE15
PE13

VDD
VCAP1
VDD

VSS
PB2
PB1
PA7

PC5
PA4

PB0

PE7
PE8
PE9
PA5
PA6

PC4
VSS

MSv34171V2

1. The above figure shows the package top view.

DS11243 Rev 7 55/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Figure 12. STM32F77xxx TFBGA100 pinout

1 2 3 4 5 6 7 8 9 10

A PC14 PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13

B PC15 VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12

C PH0 VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11

D
PH1 VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10

E BYPASS
NRST PC2 PE6 VSS VSS VCAP_2 PD1 PC9 PC7
-REG

F
PC0 PC1 PC3 VDD VDD VDDUSB PDR_ON VCAP_1 PC8 PC6

G
VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15

H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14

J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13

K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12

MSv40497V1

1. The above figure shows the package top view.

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STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Figure 13. STM32F77xxx LQFP144 pinout

VDDSDMMC
PDR_ON

BOOT0

PG15

PG14
PG13
PG12
PG11
PG10

PC12
PC11
PC10
PA15
PA14
PG9
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
VDD

VDD
VSS

VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121

109
120
119
118
117
116
115
114
113
112

110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP_2
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14 8 101 PA9
PC15 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDUSB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0 23 86 PD15
PH1 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

72
61
62
63
64
65
66
67
68
69
70
71
VCAP_1
VDD
VSS
PA3

PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12

PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9

PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VDD

VDD

VDD
VSS
VSS

MS39132V1

1. The above figure shows the package top view.

DS11243 Rev 7 57/255

102
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Figure 14. STM32F77xxx LQFP176 pinout

VDDSDMMC
PDR_ON

BOOT0

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
PG9
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3

VDD

VDD
VSS

VSS

VSS
DD
PI7
PI6
PI5
PI4

PI3
PI2
V
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153

141
140
152
151
150
149
148
147
146
145
144
143
142

139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP_2
PC14 9 124 PA13
PC15 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDDUSB
PF4 20 113 VSS
PF5 21 112 PG8
22
LQFP176 without DSI 111
VSS PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0 29 104 PD14
PH1 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2 34 99 PD11
PC3 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

80
69
70
71
72
73
74
75
76
77
78
79

88
81
82
83
84
85
86
87
VCAP_1
PC4
PC5

PF12

PF13
PF14
PF15

PH10
PG0
PG1
PH4
PH5

BYPASS_REG

PE10

PE12
PE13
PE14
PE15
PB10

PH6
PH7
PH8
PH9
PB0
PB1
PB2

PE7
PE8
PE9
VDD

VDD

VDD
VSS
VSS

PH11
PF11

PE11

PB11
PA3

PA4
PA5
PA6
PA7

VDD

MS39123V1

1. The above figure shows the package top view.

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STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Figure 15. STM32F779xx LQFP176 pinout

VDDSDMMC
PDR_ON

BOOT0

PG15

PG14
PG13
PG12

PG10

PC12

PC10
PG11

PC11

PA15
PA14
PG9
PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3

VDD

VDD
VSS

VSS

VSS
DD
PI7
PI6
PI5
PI4

PI3
PI1
V
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153

141
140
152
151
150
149
148
147
146
145
144
143
142

139
138
137
136
135
134
133
PE2 1 132 PI0
PE3 2 131 VDD
PE4 3 130 VSS
PE5 4 129 VCAP_2
PE6 5 128 PA13
VBAT 6 127 PA12
PI8 7 126 PA11
PC13 8 125 PA10
PC14 9 124 PA9
PC15 10 123 PA8
PI9 11 122 PC9
PI10 12 121 PC8
PI11 13 120 PC7
VSS 14 119 PC6
VDD 15 118 VDDUSB
PF0 16 117 VSS
PF1 17 116 PG8
PF2 18 115 PG7
PF3 19 114 PG6
PF4 20 113 PG5
PF5 21 112 PG4
22
LQFP176 with DSI 111
VSS PG3
VDD 23 110 PG2
PF6 24 109 VSSDSI
PF7 25 108 DSI_D1N
PF8 26 107 DSI_D1P
PF9 27 106 VDD12DSI
PF10 28 105 DSI_CKN
PH0 29 104 DSI_CKP
PH1 30 103 VSSDSI
NRST 31 102 DSI_D0N
PC0 32 101 DSI_D0P
PC1 33 100 VCAPDSI
PC2 34 99 VDDDSI
PC3 35 98 PD15
VDD 36 97 PD14
VSSA 37 96 VDD
VREF+ 38 95 VSS
VDDA 39 94 PD13
PA0 40 93 PD12
PA1 41 92 PD11
PA2 42 91 PD10
PH2 43 90 PD9
PH3 44 89 PD8
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

80
69
70
71
72
73
74
75
76
77
78
79

88
81
82
83
84
85
86
87
VCAP_1
PC4
PC5

PF12

PF13
PF14
PF15
PG0
PG1
PH4
PH5

BYPASS_REG

PE10

PE12
PE13
PE14
PE15
PB10

PH6
PH7
PB0
PB1
PB2

PE7
PE8
PE9
VDD

VDD

VDD

PB14
PB15
VSS
VSS
PF11

PE11

PB11
PA3

PA4
PA5
PA6
PA7

PB12
PB13
VDD

MS41054V1

1. The above figure shows the package top view.

DS11243 Rev 7 59/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Figure 16. STM32F77xxx UFBGA176 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13

PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
B PE4 PE5

PI7 PI6 PI5 VDD PDR_ON VDD VDD

C VBAT VDD PG9 PD5 PD1 PI3 PI2 PA11
SDMMC

D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10

PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9

E

F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8

PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
G

H PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6
PH1

J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6

K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3

BYPASS_
L PF10 PF9 PF8 PH11 PH10 PD15 PG2
REG

M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

R VDDA PA3 PA7 PB1 PB0 PF11

MS39130V1

1. The above figure shows the package top view.

Note: On the UFBGA176 package, the following balls are connected to Vss for package
mechanical stability and for heat dissipation purposes:
F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7,
K8, K9, K10.

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Figure 17. STM32F779Ax/STM32F778Ax WLCSP180 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13

PA14(JTCK
A NC(1) NC(1)
-SWCLK)
PD0 PD4 VDDMMC PG10 VSS PB5 BOOT0 VSS NC(1) NC(1)

B NC(1) VDD PI1 PC10 PD3 VSS PG11 VDD PB6 PE1 VDD PI7 NC(1)

C VCAP_2 VSS PI2 PC11 PD5 PG9 PG13 PB7 PE0 PDR_ON PI6 PE4 VBAT

PA13(JTMS PB4(NJ
D PA12
-SWDIO)
PI3 PC12 PD1 PD2 PG12
TRST)
PB9 PI4 PI5 PE5 PC13

PB3(JTDO/ PC15- PC15-

E PC9 PA8 PA11 PI0 PH15 PD6 PD7 TRACESWO) PB8 PE2 PE6 OSC32 OSC32_
_IN OUT

F VSS VDDUSB PC7 PA9 PA10 PH13 PH14 PA15(JTDI) PG15 PE3 PI11 VDD VSS

G PG4 PG5 PG6 PG7 PG8 PC6 PC8 PG3 PI9 PF0 PF1 PF2

H DSI_D1P DSI_D1N DSI_CKN DSI_CKP VSSDSI VCAPDSI PB12 PG2 PI10 PF3 PF4 PF5

J DSI_D0P DSI_D0N VDD12DSI PD12 PB13 PE10 PB2 PB1 VSS PA2 PA1 VDD VSS

VDDDSI PD11 PB10 PF12 PH0- PH1-

K PD15 PH9 PE11 PF14 VDD PH3 PF10
OSC_IN OSC_OUT

L PD14 PD13 PD9 PH10 PB11 PE12 PG1 PF13 PA4 PH2 NRST PC0 PC1

M VSS PD10 PD8 PH11 PH8 PE15 PE7 VDD PA7 PA3 VSSA VDDA PA0-WKUP

N NC(1) PB15 PB14 VSS VSS PE14 PE8 PG0 PF11 PA6 PH5 PH4 NC(1)

P NC(1) NC(1) PH12 VDD VCAP_1 PE13 PE9 PF15 VSS PB0 PA5 NC(1) NC(1)

MSv39614V1

1. NC ball must not be connected to GND nor to VDD.

2. The above figure shows the package top view.

DS11243 Rev 7 61/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Figure 18. STM32F77xxx LQFP208 pinout

VDDSDMMC
PDR_ON

BOOT0

PG15

PG14
PG13
PG12
PG11
PG10

PC12
PC11
PC10
PA15
PA14
VDD

VDD

VDD
PJ15
PJ14
PJ13
PJ12
PG9

PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3

PK7
PK6
PK5
PK4
PK3
PE1
PE0
VSS

VSS

VSS
PI7
PI6
PI5
PI4

PI3
165

163
162
161
160
159
158
157
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166

164
PE2 1 156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14 9 148 VCAP_2
PC15 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDDUSB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 132 PG5
VDD 26 LQFP208 131 PG4
PF6 27 130 PG3
PF7 28 129 PG2
PF8 29 128 PK2
PF9 30 127 PK1
PF10 31 126 PK0
PH0 32 125 VSS
PH1 33 124 VDD
NRST 34 123 PJ11
PC0 35 122 PJ10
PC1 36 121 PJ9
PC2 37 120 PJ8
PC3 38 119 PJ7
VDD 39 118 PJ6
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
VDD 52 105 PB13
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VCAP_1

PH10
PH11
PH12
PI15
PA4
PA5
PA6
PA7

PB10
PB11

PB12
VDD

VDD

VDD

VDD

VDD
PH6
PH7
PH8
PH9
PF11
PF12

PF13
PF14
PF15
PB0
PB1
PB2

PG0
PG1

PE10
PE11
PE12
PE13
PE14
PE15
PC4
PC5

PE7
PE8
PE9
PJ0
PJ1
PJ2
PJ3
PJ4

PJ5
VSS

VSS

VSS

VSS

MSv39131V1

1. The above figure shows the package top view.

62/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Figure 19. STM32F779xx LQFP208 pinout

VDDSDMMC
PDR_ON

BOOT0

PG15

PG14
PG13
PG12
PG11
PG10

PC12
PC11
PC10
PA15
PA14
VDD

VDD

VDD
PJ15
PJ14
PJ13
PJ12
PG9

PD7
PD6

PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8

PB7
PB6
PB5
PB4
PB3

PK7
PK6
PK5
PK4
PK3
PE1
PE0
VSS

VSS

VSS
PI7
PI6
PI5
PI4

PI3
165

163
162
161
160
159
158
157
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166

164
PE2 1 156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14 9 148 VCAP_2
PC15 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDDUSB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 132 PG5
VDD 26 LQFP208 with DSI 131 PG4
PF6 27 130 PG3
PF7 28 129 PG2
PF8 29 128 VSSDSI
PF9 30 127 DSI_D1N
PF10 31 126 DSI_D1P
PH0 32 125 VDD12DSI
PH1 33 124 DSI_CKN
NRST 34 123 DSI_CKP
PC0 35 122 VSSDSI
PC1 36 121 DSI_D0N
PC2 37 120 DSI_D0P
PC3 38 119 VCAPDSI
VDD 39 118 VDDDSI
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
VDD 52 105 PB13
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VCAP_1

PH10
PH11
PH12
PI15
PA4
PA5
PA6
PA7

PB10
PB11

PB12
VDD

VDD

VDD

VDD

VDD
PH6
PH7
PH8
PH9
PF11
PF12

PF13
PF14
PF15
PB0
PB1
PB2

PG0
PG1

PE10
PE11
PE12
PE13
PE14
PE15
PC4
PC5

PE7
PE8
PE9
PJ0
PJ1
PJ2
PJ3
PJ4

PJ5
VSS

VSS

VSS

VSS

MSv39124V1

1. The above figure shows the package top view.

DS11243 Rev 7 63/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Figure 20. STM32F77xxx TFBGA216 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 PC12 PA15 PA14 PA13

B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PDR_ BOOT0 VDD VDD VDD

E PC14 PF1 PI12 PI9 VDD VCAP2 PH13 PH14 PI0 PA9
ON SDMMC

F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD PK1 PK2 PC9 PA8

G PH0 PF2 PI13 PI15 VDD VSS VSS VDDUSB PJ11 PK0 PC8 PC7

H PH1 PF3 PI14 PH4 VDD VSS VSS VDD PJ8 PJ10 PG8 PC6

J NRST PF4 PH5 PH3 VDD VSS VSS VDD PJ7 PJ9 PG7 PG6

K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PJ6 PD15 PB13 PD10

L BYPASS-
PF10 PF9 PF8 PC3 VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8
REG

M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

MS39129V1

1. The above figure shows the package top view.

64/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Figure 21. STM32F779xx TFBGA216 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 PC12 PA15 PA14 PA13

B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PDR_ VDD
PC14 PF1 PI12 PI9 VDD
E
ON
BOOT0 VDD SDMMC VDD VCAP2 PH13 PH14 PI0 PA9

F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD DSI_ DSI_ PC9 PA8
D1P D1N

G PH0 PF2 PI13 PI15 VDD VSS VSS VDDUSB VSSDSI VDD12 PC8 PC7
DSI

H PH1 PF3 PI14 PH4 VDD VSS VSS VDDDSI DSI_ DSI_ PG8 PC6
CKP CKN

J DSI_ DSI_
NRST PF4 PH5 PH3 VDD VSS VSS VDD D0P D0N PG7 PG6

K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD VCAPDSI PD15 PB13 PD10

L BYPASS-
PF10 PF9 PF8 PC3 VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8
REG

M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

N VREF- PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

MS39125V1

1. The above figure shows the package top view.

DS11243 Rev 7 65/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 10. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O directly connected to ADC
I/O structure
B Dedicated BOOT pin
RST Bidirectional reset pin with weak pull-up resistor

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate
Functions selected through GPIOx_AFR registers
functions

Additional
Functions directly selected/enabled through peripheral registers
functions

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions
Pin Number

STM32F778Ax
Pin name (function after reset

STM32F777xx STM32F779xx
I/O structure
Pin type

Notes

Additional
Alternate functions
WLCSP180(1)

functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
A3 1 1 A2 1 1 A3 E10 1 1 A3 PE2 I/O FT - QUADSPI_BK1_IO2, -
ETH_MII_TXD3, FMC_A23,
EVENTOUT

TRACED0, SAI1_SD_B,
B3 2 2 A1 2 2 A2 F10 2 2 A2 PE3 I/O FT - -
FMC_A19, EVENTOUT

66/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TRACED1, SPI4_NSS,
SAI1_FS_A,
C3 3 3 B1 3 3 A1 C12 3 3 A1 PE4 I/O FT - DFSDM1_DATIN3, FMC_A20, -
DCMI_D4, LCD_B0,
EVENTOUT

TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
D3 4 4 B2 4 4 B1 D12 4 4 B1 PE5 I/O FT - DFSDM1_CKIN3, FMC_A21, -
DCMI_D6, LCD_G0,
EVENTOUT

TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
E3 5 5 B3 5 5 B2 E11 5 5 B2 PE6 I/O FT - SAI1_SD_A, SAI2_MCLK_B, -
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT

- - - - - - G6 - - - G6 VSS S - - - -

- - - - - - F5 - - - F5 VDD S - - - -

B2 6 6 C1 6 6 C1 C13 6 6 C1 VBAT S - - - -

RTC_TAMP2/
- - - D2 7 7 C2 NC 7 7 C2 PI8 I/O FT (2) EVENTOUT RTC_TS/
WKUP5

RTC_TAMP1/
(2) RTC_TS/
A2 7 7 D1 8 8 D1 D13 8 8 D1 PC13 I/O FT EVENTOUT
RTC_OUT/
WKUP4
(2)
PC14-
A1 8 8 E1 9 9 E1 E12 9 9 E1 I/O FT (3) EVENTOUT OSC32_IN
OSC32_IN

PC15- (2)
B1 9 9 F1 10 10 F1 E13 10 10 F1 OSC32_O I/O FT (3) EVENTOUT OSC32_OUT
UT

- - - - - - G5 - - - G5 VDD S - - - -

UART4_RX, CAN1_RX,
- - - D3 11 11 E4 G10 11 11 E4 PI9 I/O FT - FMC_D30, LCD_VSYNC, -
EVENTOUT

ETH_MII_RX_ER, FMC_D31,
- - - E3 12 12 D5 H10 12 12 D5 PI10 I/O FT - -
LCD_HSYNC, EVENTOUT

LCD_G6, OTG_HS_ULPI_DIR,
- - - E4 13 13 F3 F11 13 13 F3 PI11 I/O FT - WKUP6
EVENTOUT

- - - F2 14 14 F2 F13 14 14 F2 VSS S - - - -

DS11243 Rev 7 67/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

- - - F3 15 15 F4 F12 15 15 F4 VDD S - - - -

I2C2_SDA, FMC_A0,
- - 10 E2 16 16 D2 G11 16 16 D2 PF0 I/O FT - -
EVENTOUT

I2C2_SCL, FMC_A1,
- - 11 H3 17 17 E2 G12 17 17 E2 PF1 I/O FT - -
EVENTOUT

I2C2_SMBA, FMC_A2,
- - 12 H2 18 18 G2 G13 18 18 G2 PF2 I/O FT - -
EVENTOUT

- - - - - 19 E3 NC - 19 E3 PI12 I/O FT - LCD_HSYNC, EVENTOUT -

- - - - - 20 G3 NC - 20 G3 PI13 I/O FT - LCD_VSYNC, EVENTOUT -

- - - - - 21 H3 NC - 21 H3 PI14 I/O FT - LCD_CLK, EVENTOUT -

- - 13 J2 19 22 H2 H11 19 22 H2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9

- - 14 J3 20 23 J2 H12 20 23 J2 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14

- - 15 K3 21 24 K3 H13 21 24 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15

C2 10 16 G2 22 25 H6 J13 22 25 H6 VSS S - - - -

D2 11 17 G3 23 26 H5 J12 23 26 H5 VDD S - - - -

TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
- - 18 K2 24 27 K2 NC 24 27 K2 PF6 I/O FT - ADC3_IN4
QUADSPI_BK1_IO3,
EVENTOUT

TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
- - 19 K1 25 28 K1 NC 25 28 K1 PF7 I/O FT - ADC3_IN5
QUADSPI_BK1_IO2,
EVENTOUT

SPI5_MISO, SAI1_SCK_B,
UART7_RTS, TIM13_CH1,
- - 20 L3 26 29 L3 NC 26 29 L3 PF8 I/O FT - ADC3_IN6
QUADSPI_BK1_IO0,
EVENTOUT

SPI5_MOSI, SAI1_FS_B,
UART7_CTS, TIM14_CH1,
- - 21 L2 27 30 L2 NC 27 30 L2 PF9 I/O FT - ADC3_IN7
QUADSPI_BK1_IO1,
EVENTOUT

QUADSPI_CLK, DCMI_D11,
- - 22 L1 28 31 L1 K11 28 31 L1 PF10 I/O FT - ADC3_IN8
LCD_DE, EVENTOUT

PH0- (3)
C1 12 23 G1 29 32 G1 K12 29 32 G1 I/O FT EVENTOUT OSC_IN
OSC_IN

68/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

PH1- (3)
D1 13 24 H1 30 33 H1 K13 30 33 H1 I/O FT EVENTOUT OSC_OUT
OSC_OUT

RS
E1 14 25 J1 31 34 J1 L11 31 34 J1 NRST I/O - - -
T

DFSDM1_CKIN0,
DFSDM1_DATIN4,
ADC1_IN10,
SAI2_FS_B,
F1 15 26 M2 32 35 M2 L12 32 35 M2 PC0 I/O FT - ADC2_IN10,
OTG_HS_ULPI_STP,
ADC3_IN10
FMC_SDNWE, LCD_R5,
EVENTOUT

TRACED0, DFSDM1_DATIN0, ADC1_IN11,

SPI2_MOSI/I2S2_SD, ADC2_IN11,
F2 16 27 M3 33 36 M3 L13 33 36 M3 PC1 I/O FT - SAI1_SD_A, DFSDM1_CKIN4, ADC3_IN11,
ETH_MDC, MDIOS_MDC, RTC_TAMP3/
EVENTOUT WKUP3

DFSDM1_CKIN1, SPI2_MISO,
DFSDM1_CKOUT, ADC1_IN12,
E2 17 28 M4 34 37 M4 NC 34 37 M4 PC2 I/O FT - OTG_HS_ULPI_DIR, ADC2_IN12,
ETH_MII_TXD2, FMC_SDNE0, ADC3_IN12
EVENTOUT

DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SD, ADC1_IN13,
F3 18 29 M5 35 38 L4 NC 35 38 L4 PC3 I/O FT - OTG_HS_ULPI_NXT, ADC2_IN13,
ETH_MII_TX_CLK, ADC3_IN13
FMC_SDCKE0, EVENTOUT

- - 30 - 36 39 J5 - 36 39 J5 VDD S - - - -

- - - - - - J6 - - - J6 VSS S - - - -

G1 19 31 M1 37 40 M1 M11 37 40 M1 VSSA S - - - -

- - - N1 - - N1 - - - N1 VREF- S - - - -

- 20 32 P1 38 41 P1 - 38 41 P1 VREF+ S - - - -

H1 21 33 R1 39 42 R1 M12 39 42 R1 VDDA S - - - -

TIM2_CH1/TIM2_ETR,
ADC1_IN0,
TIM5_CH1, TIM8_ETR,
PA0- (4) ADC2_IN0,
G2 22 34 N3 40 43 N3 M13 40 43 N3 I/O FT USART2_CTS, UART4_TX,
WKUP ADC3_IN0,
SAI2_SD_B, ETH_MII_CRS,
WKUP1
EVENTOUT

DS11243 Rev 7 69/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3, ADC1_IN1,
H2 23 35 N2 41 44 N2 J11 41 44 N2 PA1 I/O FT - SAI2_MCLK_B, ADC2_IN1,
ETH_MII_RX_CLK/ETH_RMII_ ADC3_IN1
REF_CLK, LCD_R2,
EVENTOUT

TIM2_CH3, TIM5_CH3,
ADC1_IN2,
TIM9_CH1, USART2_TX,
ADC2_IN2,
J2 24 36 P2 42 45 P2 J10 42 45 P2 PA2 I/O FT - SAI2_SCK_B, ETH_MDIO,
ADC3_IN2,
MDIOS_MDIO, LCD_R1,
WKUP2
EVENTOUT

LPTIM1_IN2,
QUADSPI_BK2_IO0,
- - - F4 43 46 K4 L10 43 46 K4 PH2 I/O FT - SAI2_SCK_B, ETH_MII_CRS, -
FMC_SDCKE0, LCD_R0,
EVENTOUT

QUADSPI_BK2_IO1,
SAI2_MCLK_B,
- - - G4 44 47 J4 K10 44 47 J4 PH3 I/O FT - -
ETH_MII_COL, FMC_SDNE0,
LCD_R1, EVENTOUT

I2C2_SCL, LCD_G5,
- - - H4 45 48 H4 N12 45 48 H4 PH4 I/O FT - OTG_HS_ULPI_NXT, LCD_G4, -
EVENTOUT

I2C2_SDA, SPI5_NSS,
- - - J4 46 49 J3 N11 46 49 J3 PH5 I/O FT - -
FMC_SDNWE, EVENTOUT

TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX, ADC1_IN3,
K2 25 37 R2 47 50 R2 M10 47 50 R2 PA3 I/O FT - LCD_B2, OTG_HS_ULPI_D0, ADC2_IN3,
ETH_MII_COL, LCD_B5, ADC3_IN3
EVENTOUT

J1 26 38 - - 51 K6 J9 - 51 K6 VSS S - - - -

BYPASS_
E6 - - L4 48 - L5 -(5) 48 - L5 I FT - - -
REG

K1 27 39 K4 49 52 K5 K9 49 52 K5 VDD S - - - -

SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS, ADC1_IN4,
G3 28 40 N4 50 53 N4 L9 50 53 N4 PA4 I/O TTa - USART2_CK, SPI6_NSS, ADC2_IN4,
OTG_HS_SOF, DCMI_HSYNC, DAC_OUT1
LCD_VSYNC, EVENTOUT

70/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
ADC1_IN5,
SPI1_SCK/I2S1_CK,
H3 29 41 P4 51 54 P4 P11 51 54 P4 PA5 I/O TTa - ADC2_IN5,
SPI6_SCK,
DAC_OUT2
OTG_HS_ULPI_CK, LCD_R4,
EVENTOUT

TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
ADC1_IN6,
J3 30 42 P3 52 55 P3 N10 52 55 P3 PA6 I/O FT - SPI6_MISO, TIM13_CH1,
ADC2_IN6
MDIOS_MDC, DCMI_PIXCLK,
LCD_G2, EVENTOUT

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
ADC1_IN7,
K3 31 43 R3 53 56 R3 M9 53 56 R3 PA7 I/O FT - SPI6_MOSI, TIM14_CH1,
ADC2_IN7
ETH_MII_RX_DV/ETH_RMII_C
RS_DV, FMC_SDNWE,
EVENTOUT

DFSDM1_CKIN2, I2S1_MCK,
SPDIF_RX2, ADC1_IN14,
G4 32 44 N5 54 57 N5 NC 54 57 N5 PC4 I/O FT -
ETH_MII_RXD0/ETH_RMII_RX ADC2_IN14
D0, FMC_SDNE0, EVENTOUT

DFSDM1_DATIN2,
SPDIF_RX3,
ADC1_IN15,
H4 33 45 P5 55 58 P5 NC 55 58 P5 PC5 I/O FT - ETH_MII_RXD1/ETH_RMII_RX
ADC2_IN15
D1, FMC_SDCKE0,
EVENTOUT

- - - - - 59 L7 - - 59 L7 VDD S - - - -

- - - - - 60 L6 - - 60 L6 VSS S - - - -

TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
ADC1_IN8,
J4 34 46 R5 56 61 R5 P10 56 61 R5 PB0 I/O FT - UART4_CTS, LCD_R3,
ADC2_IN8
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT

TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1, LCD_R6, ADC1_IN9,
K4 35 47 R4 57 62 R4 J8 57 62 R4 PB1 I/O FT -
OTG_HS_ULPI_D2, ADC2_IN9
ETH_MII_RXD3, LCD_G0,
EVENTOUT

DS11243 Rev 7 71/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
G5 36 48 M6 58 63 M5 J7 58 63 M5 PB2 I/O FT - -
QUADSPI_CLK,
DFSDM1_CKIN1, EVENTOUT

LCD_G2, LCD_R0,
- - - - - 64 G4 NC - 64 G4 PI15 I/O FT - -
EVENTOUT

LCD_R7, LCD_R1,
- - - - - 65 R6 NC - 65 R6 PJ0 I/O FT - -
EVENTOUT

- - - - - 66 R7 NC - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -

- - - - - 67 P7 NC - 67 P7 PJ2 I/O FT - DSI_TE, LCD_R3, EVENTOUT -

- - - - - 68 N8 NC - 68 N8 PJ3 I/O FT - LCD_R4, EVENTOUT -

- - - - - 69 M9 NC - 69 M9 PJ4 I/O FT - LCD_R5, EVENTOUT -

SPI5_MOSI, SAI2_SD_B,
- - 49 R6 59 70 P8 N9 59 70 P8 PF11 I/O FT - FMC_SDNRAS, DCMI_D12, -
EVENTOUT

- - 50 P6 60 71 M6 K7 60 71 M6 PF12 I/O FT - FMC_A6, EVENTOUT -

- - 51 M8 61 72 K7 P9 61 72 K7 VSS S - - - -

- - 52 N8 62 73 L8 M8 62 73 L8 VDD S - - - -

I2C4_SMBA,
- - 53 N6 63 74 N6 L8 63 74 N6 PF13 I/O FT - DFSDM1_DATIN6, FMC_A7, -
EVENTOUT

I2C4_SCL, DFSDM1_CKIN6,
- - 54 R7 64 75 P6 K8 64 75 P6 PF14 I/O FT - -
FMC_A8, EVENTOUT

I2C4_SDA, FMC_A9,
- - 55 P7 65 76 M8 P8 65 76 M8 PF15 I/O FT - -
EVENTOUT

- - 56 N7 66 77 N7 N8 66 77 N7 PG0 I/O FT - FMC_A10, EVENTOUT -

- - 57 M7 67 78 M7 L7 67 78 M7 PG1 I/O FT - FMC_A11, EVENTOUT -

TIM1_ETR, DFSDM1_DATIN2,
UART7_RX,
H5 37 58 R8 68 79 R8 M7 68 79 R8 PE7 I/O FT - -
QUADSPI_BK2_IO0, FMC_D4,
EVENTOUT

TIM1_CH1N, DFSDM1_CKIN2,
UART7_TX,
J5 38 59 P8 69 80 N9 N7 69 80 N9 PE8 I/O FT - -
QUADSPI_BK2_IO1, FMC_D5,
EVENTOUT

72/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS,
K5 39 60 P9 70 81 P9 P7 70 81 P9 PE9 I/O FT - -
QUADSPI_BK2_IO2, FMC_D6,
EVENTOUT

- - 61 M9 71 82 K8 - 71 82 K8 VSS S - - - -

- - 62 N9 72 83 L9 - 72 83 L9 VDD S - - - -

TIM1_CH2N,
DFSDM1_DATIN4,
G6 40 63 R9 73 84 R9 J6 73 84 R9 PE10 I/O FT - UART7_CTS, -
QUADSPI_BK2_IO3, FMC_D7,
EVENTOUT

TIM1_CH2, SPI4_NSS,
DFSDM1_CKIN4, SAI2_SD_B,
H6 41 64 P10 74 85 P10 K6 74 85 P10 PE11 I/O FT - -
FMC_D8, LCD_G3,
EVENTOUT

TIM1_CH3N, SPI4_SCK,
DFSDM1_DATIN5,
J6 42 65 R10 75 86 R10 L6 75 86 R10 PE12 I/O FT - -
SAI2_SCK_B, FMC_D9,
LCD_B4, EVENTOUT

TIM1_CH3, SPI4_MISO,
DFSDM1_CKIN5, SAI2_FS_B,
K6 43 66 N11 76 87 R12 P6 76 87 R12 PE13 I/O FT - -
FMC_D10, LCD_DE,
EVENTOUT

TIM1_CH4, SPI4_MOSI,
G7 44 67 P11 77 88 P11 N6 77 88 P11 PE14 I/O FT - SAI2_MCLK_B, FMC_D11, -
LCD_CLK, EVENTOUT

TIM1_BKIN, FMC_D12,
H7 45 68 R11 78 89 R11 M6 78 89 R11 PE15 I/O FT - -
LCD_R7, EVENTOUT

TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
J7 46 69 R12 79 90 P12 K5 79 90 P12 PB10 I/O FT - -
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT

DS11243 Rev 7 73/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM2_CH4, I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
K7 47 70 R13 80 91 R13 L5 80 91 R13 PB11 I/O FT - OTG_HS_ULPI_D4, -
ETH_MII_TX_EN/ETH_RMII_T
X_EN, DSI_TE, LCD_G5,
EVENTOUT

F8 48 71 M10 81 92 L11 P5 81 92 L11 VCAP_1 S - - - -

- 49 - - - 93 K9 N5 - 93 K9 VSS S - - - -

- 50 72 N10 82 94 L10 P4 82 94 L10 VDD S - - - -

- - - - - 95 M14 NC - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -

I2C2_SMBA, SPI5_SCK,
TIM12_CH1, ETH_MII_RXD2,
- - - M11 83 96 P13 NC 83 96 P13 PH6 I/O FT - -
FMC_SDNE1, DCMI_D8,
EVENTOUT

I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
- - - N12 84 97 N13 NC 84 97 N13 PH7 I/O FT - -
FMC_SDCKE1, DCMI_D9,
EVENTOUT

I2C3_SDA, FMC_D16,
- - - M12 85 98 P14 M5 - 98 P14 PH8 I/O FT - DCMI_HSYNC, LCD_R2, -
EVENTOUT

I2C3_SMBA, TIM12_CH2,
- - - M13 86 99 N14 K4 - 99 N14 PH9 I/O FT - FMC_D17, DCMI_D0, -
LCD_R3, EVENTOUT

TIM5_CH1, I2C4_SMBA,
- - - L13 87 100 P15 L4 - 100 P15 PH10 I/O FT - FMC_D18, DCMI_D1, -
LCD_R4, EVENTOUT

TIM5_CH2, I2C4_SCL,
- - - L12 88 101 N15 M4 - 101 N15 PH11 I/O FT - FMC_D19, DCMI_D2, -
LCD_R5, EVENTOUT

TIM5_CH3, I2C4_SDA,
- - - K12 89 102 M15 P3 - 102 M15 PH12 I/O FT - FMC_D20, DCMI_D3, -
LCD_R6, EVENTOUT

- - - H12 90 - K10 N4 - - K10 VSS S - - - -

- - - J12 91 103 K11 - - 103 K11 VDD S - - - -

74/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK, UART5_RX,
K8 51 73 P12 92 104 L13 H8 85 104 L13 PB12 I/O FT - -
CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TX
D0, OTG_HS_ID, EVENTOUT

TIM1_CH1N,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
OTG_HS_VB
J8 52 74 P13 93 105 K14 J5 86 105 K14 PB13 I/O FT - USART3_CTS, UART5_TX,
US
CAN2_TX, OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TX
D1, EVENTOUT

TIM1_CH2N, TIM8_CH2N,
USART1_TX, SPI2_MISO,
DFSDM1_DATIN2,
H10 53 75 R14 94 106 R14 N3 87 106 R14 PB14 I/O FT - -
USART3_RTS, UART4_RTS,
TIM12_CH1, SDMMC2_D0,
OTG_HS_DM, EVENTOUT

RTC_REFIN, TIM1_CH3N,
TIM8_CH3N, USART1_RX,
SPI2_MOSI/I2S2_SD,
G10 54 76 R15 95 107 R15 N2 88 107 R15 PB15 I/O FT - DFSDM1_CKIN2, -
UART4_CTS, TIM12_CH2,
SDMMC2_D1, OTG_HS_DP,
EVENTOUT

DFSDM1_CKIN3,
K9 55 77 P15 96 108 L15 M3 89 108 L15 PD8 I/O FT - USART3_TX, SPDIF_RX1, -
FMC_D13, EVENTOUT

DFSDM1_DATIN3,
J9 56 78 P14 97 109 L14 L3 90 109 L14 PD9 I/O FT - USART3_RX, FMC_D14, -
EVENTOUT

DFSDM1_CKOUT,
H9 57 79 N15 98 110 K15 M2 91 110 K15 PD10 I/O FT - USART3_CK, FMC_D15, -
LCD_B3, EVENTOUT

I2C4_SMBA, USART3_CTS,
QUADSPI_BK1_IO0,
G9 58 80 N14 99 111 N10 K3 92 111 N10 PD11 I/O FT - SAI2_SD_A, -
FMC_A16/FMC_CLE,
EVENTOUT

DS11243 Rev 7 75/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM4_CH1, LPTIM1_IN1,
I2C4_SCL, USART3_RTS,
QUADSPI_BK1_IO1,
K10 59 81 N13 100 112 M10 J4 93 112 M10 PD12 I/O FT - -
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT

TIM4_CH2, LPTIM1_OUT,
I2C4_SDA,
J10 60 82 M15 101 113 M11 L2 94 113 M11 PD13 I/O FT - QUADSPI_BK1_IO3, -
SAI2_SCK_A, FMC_A18,
EVENTOUT

- - 83 - 102 114 J10 M1 95 114 J10 VSS S - - - -

- - 84 J13 103 115 J11 - 96 115 J11 VDD S - - - -

TIM4_CH3, UART8_CTS,
H8 61 85 M14 104 116 L12 L1 97 116 L12 PD14 I/O FT - -
FMC_D0, EVENTOUT

TIM4_CH4, UART8_RTS,
G8 62 86 L14 105 117 K13 K2 98 117 K13 PD15 I/O FT - -
FMC_D1, EVENTOUT

- - - - - 118 K12 - - - - PJ6 I/O FT - LCD_R7, EVENTOUT -

- - - - - 119 J12 - - - - PJ7 I/O FT - LCD_G0, EVENTOUT -

- - - - - 120 H12 - - - - PJ8 I/O FT - LCD_G1, EVENTOUT -

- - - - - 121 J13 - - - - PJ9 I/O FT - LCD_G2, EVENTOUT -

- - - - - 122 H13 - - - - PJ10 I/O FT - LCD_G3, EVENTOUT -

- - - - - 123 G12 - - - - PJ11 I/O FT - LCD_G4, EVENTOUT -

- - - - - 124 H11 - - - - VDD S - - - -

- - - - - - - K1 99 118 H11 VDDDSI S - - - -

- - - - - 125 H10 - - - H10 VSS S - - - -

- - - - - - - H6 100 119 K12 VCAPDSI S - - - -

- - - - - - - J3 - - G13 VDD12DSI S - - - -

- - - - - - - J1 101 120 J12 DSI_D0P I/O - - - -

- - - - - - - J2 102 121 J13 DSI_D0N I/O - - - -

- - - - - - - H5 103 122 G12 VSSDSI S - - - -

- - - - - - - H4 104 123 H12 DSI_CKP I/O - - - -

76/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

- - - - - - - H3 105 124 H13 DSI_CKN I/O - - - -

- - - - - - - - 106 125 - VDD12DSI S - - - -

- - - - - - - H1 107 126 F12 DSI_D1P I/O - - - -

- - - - - - - H2 108 127 F13 DSI_D1N I/O - - - -

- - - - - - - - 109 128 - VSSDSI S - - - -

- - - - - 126 G13 - - - - PK0 I/O FT - LCD_G5, EVENTOUT -

- - - - - 127 F12 - - - - PK1 I/O FT - LCD_G6, EVENTOUT -

- - - - - 128 F13 - - - - PK2 I/O FT - LCD_G7, EVENTOUT -

- - 87 L15 106 129 M13 H9 110 129 M13 PG2 I/O FT - FMC_A12, EVENTOUT -

- - 88 K15 107 130 M12 G9 111 130 M12 PG3 I/O FT - FMC_A13, EVENTOUT -

FMC_A14/FMC_BA0,
- - 89 K14 108 131 N12 G1 112 131 N12 PG4 I/O FT - -
EVENTOUT

FMC_A15/FMC_BA1,
- - 90 K13 109 132 N11 G2 113 132 N11 PG5 I/O FT - -
EVENTOUT

FMC_NE3, DCMI_D12,
- - 91 J15 110 133 J15 G3 114 133 J15 PG6 I/O FT - -
LCD_R7, EVENTOUT

SAI1_MCLK_A, USART6_CK,
- - 92 J14 111 134 J14 G4 115 134 J14 PG7 I/O FT - FMC_INT, DCMI_D13, -
LCD_CLK, EVENTOUT

SPI6_NSS, SPDIF_RX2,
USART6_RTS,
- - 93 H14 112 135 H14 G5 116 135 H14 PG8 I/O FT - -
ETH_PPS_OUT, FMC_SDCLK,
LCD_G7, EVENTOUT

- - 94 G12 113 136 G10 F1 117 136 G10 VSS S - - - -

F6 - 95 H13 114 137 G11 F2 118 137 G11 VDDUSB S - - - -

TIM3_CH1, TIM8_CH1,
I2S2_MCK, DFSDM1_CKIN3,
USART6_TX, FMC_NWAIT,
F10 63 96 H15 115 138 H15 G6 119 138 H15 PC6 I/O FT - -
SDMMC2_D6, SDMMC1_D6,
DCMI_D0, LCD_HSYNC,
EVENTOUT

DS11243 Rev 7 77/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

TIM3_CH2, TIM8_CH2,
I2S3_MCK, DFSDM1_DATIN3,
USART6_RX, FMC_NE1,
E10 64 97 G15 116 139 G15 F3 120 139 G15 PC7 I/O FT - -
SDMMC2_D7, SDMMC1_D7,
DCMI_D1, LCD_G6,
EVENTOUT

TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK,
F9 65 98 G14 117 140 G14 G8 121 140 G14 PC8 I/O FT -
FMC_NE2/FMC_NCE,
-
SDMMC1_D0, DCMI_D2,
EVENTOUT

MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, I2S_CKIN,
UART5_CTS,
E9 66 99 F14 118 141 F14 E1 122 141 F14 PC9 I/O FT - --
QUADSPI_BK1_IO0, LCD_G3,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT

MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL,
USART1_CK, OTG_FS_SOF,
D9 67 100 F15 119 142 F15 E2 123 142 F15 PA8 I/O FT - -
CAN3_RX, UART7_RX,
LCD_B3, LCD_R6,
EVENTOUT

TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK, OTG_FS_VB
C9 68 101 E15 120 143 E15 F4 124 143 E15 PA9 I/O FT -
USART1_TX, DCMI_D0, US
LCD_R5, EVENTOUT

TIM1_CH3, USART1_RX,
LCD_B4, OTG_FS_ID,
D10 69 102 D15 121 144 D15 F5 125 144 D15 PA10 I/O FT - -
MDIOS_MDIO, DCMI_D1,
LCD_B1, EVENTOUT

TIM1_CH4,
SPI2_NSS/I2S2_WS,
C10 70 103 C15 122 145 C15 E3 126 145 C15 PA11 I/O FT - UART4_RX, USART1_CTS, -
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT

TIM1_ETR,
SPI2_SCK/I2S2_CK,
UART4_TX, USART1_RTS,
B10 71 104 B15 123 146 B15 D1 127 146 B15 PA12 I/O FT - -
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT

78/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

PA13(JTM
A10 72 105 A15 124 147 A15 D2 128 147 A15 I/O FT - JTMS-SWDIO, EVENTOUT -
S-SWDIO)

E7 73 106 F13 125 148 E11 C1 129 148 E11 VCAP_2 S - - - -

E5 74 107 F12 126 149 F10 C2 130 149 F10 VSS S - - - -

F5 75 108 G13 127 150 F11 B2 131 150 F11 VDD S - - - -

TIM8_CH1N, UART4_TX,
- - - E12 128 151 E12 F6 - 151 E12 PH13 I/O FT - CAN1_TX, FMC_D21, -
LCD_G2, EVENTOUT

TIM8_CH2N, UART4_RX,
CAN1_RX, FMC_D22,
- - - E13 129 152 E13 F7 - 152 E13 PH14 I/O FT - -
DCMI_D4, LCD_G3,
EVENTOUT

TIM8_CH3N, FMC_D23,
- - - D13 130 153 D13 E5 - 153 D13 PH15 I/O FT - DCMI_D11, LCD_G4, -
EVENTOUT

TIM5_CH4,
SPI2_NSS/I2S2_WS,
- - - E14 131 154 E14 E4 132 154 E14 PI0 I/O FT - -
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT

TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
- - - D14 132 155 D14 B3 133 155 D14 PI1 I/O FT - -
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT

TIM8_CH4, SPI2_MISO,
- - - C14 133 156 C14 C3 - 156 C14 PI2 I/O FT - FMC_D26, DCMI_D9, -
LCD_G7, EVENTOUT

TIM8_ETR,
SPI2_MOSI/I2S2_SD,
- - - C13 134 157 C13 D3 134 157 C13 PI3 I/O FT - -
FMC_D27, DCMI_D10,
EVENTOUT

- - - D9 135 - F9 - 135 - F9 VSS S - - - -

- - - C9 136 158 E10 - 136 158 E10 VDD S - - - --

PA14(JTC
A9 76 109 A14 137 159 A14 A3 137 159 A14 I/O FT - JTCK-SWCLK, EVENTOUT -
K-SWCLK)

DS11243 Rev 7 79/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

JTDI, TIM2_CH1/TIM2_ETR,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
PA15(JTDI
A8 77 110 A13 138 160 A13 F8 138 160 A13 I/O FT - SPI3_NSS/I2S3_WS, -
)
SPI6_NSS, UART4_RTS,
CAN3_TX, UART7_TX,
EVENTOUT

DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
B9 78 111 B14 139 161 B14 B4 139 161 B14 PC10 I/O FT - -
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT

DFSDM1_DATIN5,
SPI3_MISO, USART3_RX,
UART4_RX,
B8 79 112 B13 140 162 B13 C4 140 162 B13 PC11 I/O FT - -
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT

TRACED3,
SPI3_MOSI/I2S3_SD,
C8 80 113 A12 141 163 A12 D4 141 163 A12 PC12 I/O FT - USART3_CK, UART5_TX, -
SDMMC1_CK, DCMI_D9,
EVENTOUT

DFSDM1_CKIN6,
DFSDM1_DATIN7,
D8 81 114 B12 142 164 B12 A4 142 164 B12 PD0 I/O FT - -
UART4_RX, CAN1_RX,
FMC_D2, EVENTOUT

DFSDM1_DATIN6,
DFSDM1_CKIN7, UART4_TX,
E8 82 115 C12 143 165 C12 D5 143 165 C12 PD1 I/O FT - --
CAN1_TX, FMC_D3,
EVENTOUT

TRACED2, TIM3_ETR,
B7 83 116 D12 144 166 D12 D6 144 166 D12 PD2 I/O FT - UART5_RX, SDMMC1_CMD, -
DCMI_D11, EVENTOUT

DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
C7 84 117 D11 145 167 C11 B5 145 167 C11 PD3 I/O FT - -
USART2_CTS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT

DFSDM1_CKIN0,
D7 85 118 D10 146 168 D11 A5 146 168 D11 PD4 I/O FT - USART2_RTS, FMC_NOE, -
EVENTOUT

80/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

USART2_TX, FMC_NWE,
B6 86 119 C11 147 169 C10 C5 147 169 C10 PD5 I/O FT - -
EVENTOUT

- - 120 D8 148 170 F8 B6 148 170 F8 VSS S - - - -

VDDSDM
- - 121 C8 149 171 E9 A6 149 171 E9 S - - - -
MC

DFSDM1_CKIN4,
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
C6 87 122 B11 150 172 B11 E6 150 172 B11 PD6 I/O FT - DFSDM1_DATIN1, -
SDMMC2_CK, FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT

DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SD,
DFSDM1_CKIN1,
D6 88 123 A11 151 173 A11 E7 151 173 A11 PD7 I/O FT - -
USART2_CK, SPDIF_RX0,
SDMMC2_CMD, FMC_NE1,
EVENTOUT

LCD_G3, LCD_B0,
- - - - - 174 B10 NC - 174 B10 PJ12 I/O FT - -
EVENTOUT

LCD_G4, LCD_B1,
- - - - - 175 B9 NC - 175 B9 PJ13 I/O FT - -
EVENTOUT

- - - - - 176 C9 NC - 176 C9 PJ14 I/O FT - LCD_B2, EVENTOUT -

- - - - - 177 D10 - - 177 D10 PJ15 I/O FT - LCD_B3, EVENTOUT -

SPI1_MISO, SPDIF_RX3,
USART6_RX,
QUADSPI_BK2_IO2,
- - 124 C10 152 178 D9 C6 152 178 D9 PG9 I/O FT - -
SAI2_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT

SPI1_NSS/I2S1_WS, LCD_G3,
SAI2_SD_B, SDMMC2_D1,
- - 125 B10 153 179 C8 A7 153 179 C8 PG10 I/O FT - -
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT

SPI1_SCK/I2S1_CK,
SPDIF_RX0, SDMMC2_D2,
- - 126 B9 154 180 B8 B7 154 180 B8 PG11 I/O FT - ETH_MII_TX_EN/ETH_RMII_T -
X_EN, DCMI_D3, LCD_B3,
EVENTOUT

DS11243 Rev 7 81/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

LPTIM1_IN1, SPI6_MISO,
SPDIF_RX1, USART6_RTS,
- - 127 B8 155 181 C7 D7 155 181 C7 PG12 I/O FT - LCD_B4, SDMMC2_D3, -
FMC_NE4, LCD_B1,
EVENTOUT

TRACED0, LPTIM1_OUT,
SPI6_SCK, USART6_CTS,
- - 128 A8 156 182 B3 C7 156 182 B3 PG13 I/O FT - ETH_MII_TXD0/ETH_RMII_TX -
D0, FMC_A24, LCD_R0,
EVENTOUT

TRACED1, LPTIM1_ETR,
SPI6_MOSI, USART6_TX,
QUADSPI_BK2_IO3,
- - 129 A7 157 183 A4 NC 157 183 A4 PG14 I/O FT - -
ETH_MII_TXD1/ETH_RMII_TX
D1, FMC_A25, LCD_B0,
EVENTOUT

- - 130 D7 158 184 F7 A8 158 184 F7 VSS S - - - -

- - 131 C7 159 185 E8 B8 159 185 E8 VDD S - - - -

- - - - - 186 D8 NC - 186 D8 PK3 I/O FT - LCD_B4, EVENTOUT -

- - - - - 187 D7 NC - 187 D7 PK4 I/O FT - LCD_B5, EVENTOUT -

- - - - - 188 C6 NC - 188 C6 PK5 I/O FT - LCD_B6, EVENTOUT -

- - - - - 189 C5 NC - 189 C5 PK6 I/O FT - LCD_B7, EVENTOUT -

- - - - - 190 C4 NC - 190 C4 PK7 I/O FT - LCD_DE, EVENTOUT -

USART6_CTS,
- - 132 B7 160 191 B7 F9 160 191 B7 PG15 I/O FT - FMC_SDNCAS, DCMI_D13, -
EVENTOUT

JTDO/TRACESWO,
TIM2_CH2,
PB3
SPI1_SCK/I2S1_CK,
(JTDO/
A7 89 133 A10 161 192 A10 E8 161 192 A10 I/O FT - SPI3_SCK/I2S3_CK, -
TRACESW
SPI6_SCK, SDMMC2_D2,
O)
CAN3_RX, UART7_RX,
EVENTOUT

NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
PB4(NJTR SPI2_NSS/I2S2_WS,
A6 90 134 A9 162 193 A9 D8 162 193 A9 I/O FT - -
ST) SPI6_MISO, SDMMC2_D3,
CAN3_TX, UART7_TX,
EVENTOUT

82/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

UART5_RX, TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
C5 91 135 A6 163 194 A8 A9 163 194 A8 PB5 I/O FT - SPI6_MOSI, CAN2_RX, -
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10,
LCD_G7, EVENTOUT

UART5_TX, TIM4_CH1,
HDMI_CEC, I2C1_SCL,
DFSDM1_DATIN5,
B5 92 136 B6 164 195 B6 B9 164 195 B6 PB6 I/O FT - USART1_TX, CAN2_TX, -
QUADSPI_BK1_NCS,
I2C4_SCL, FMC_SDNE1,
DCMI_D5, EVENTOUT

TIM4_CH2, I2C1_SDA,
DFSDM1_CKIN5,
A5 93 137 B5 165 196 B5 C8 165 196 B5 PB7 I/O FT - USART1_RX, I2C4_SDA, -
FMC_NL, DCMI_VSYNC,
EVENTOUT

D5 94 138 D6 166 197 E6 A10 166 197 E6 BOOT0 I B - - VPP

I2C4_SCL, TIM4_CH3,
TIM10_CH1, I2C1_SCL,
DFSDM1_CKIN7, UART5_RX,
B4 95 139 A5 167 198 A7 E9 167 198 A7 PB8 I/O FT - CAN1_RX, SDMMC2_D4, -
ETH_MII_TXD3, SDMMC1_D4,
DCMI_D6, LCD_B6,
EVENTOUT

I2C4_SDA, TIM4_CH4,
TIM11_CH1, I2C1_SDA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN7, UART5_TX,
A4 96 140 B4 168 199 B4 D9 168 199 B4 PB9 I/O FT - -
CAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5,
DCMI_D7, LCD_B7,
EVENTOUT

TIM4_ETR, LPTIM1_ETR,
UART8_RX, SAI2_MCLK_A,
D4 97 141 A4 169 200 A6 C9 169 200 A6 PE0 I/O FT - -
FMC_NBL0, DCMI_D2,
EVENTOUT

LPTIM1_IN2, UART8_TX,
C4 98 142 A3 170 201 A5 B10 170 201 A5 PE1 I/O FT - FMC_NBL1, DCMI_D3, -
EVENTOUT

DS11243 Rev 7 83/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

E4 99 - D5 - 202 F6 A11 - 202 F6 VSS S - - - -

F7 - 143 C6 171 203 E5 C10 171 203 E5 PDR_ON S - - - -

F4 100 144 C5 172 204 E7 B11 172 204 E7 VDD S - - - -

TIM8_BKIN, SAI2_MCLK_A,
- - - D4 173 205 C3 D10 173 205 C3 PI4 I/O FT - FMC_NBL2, DCMI_D5, -
LCD_B4, EVENTOUT

TIM8_CH1, SAI2_SCK_A,
- - - C4 174 206 D3 D11 174 206 D3 PI5 I/O FT - FMC_NBL3, DCMI_VSYNC, -
LCD_B5, EVENTOUT

TIM8_CH2, SAI2_SD_A,
- - - C3 175 207 D6 C11 175 207 D6 PI6 I/O FT - FMC_D28, DCMI_D6, LCD_B6, -
EVENTOUT

TIM8_CH3, SAI2_FS_A,
- - - C2 176 208 D4 B12 176 208 D4 PI7 I/O FT - FMC_D29, DCMI_D7, LCD_B7, -
EVENTOUT

- - - F6 - - - - - - - VSS S - - - -

- - - F7 - - - - - - - VSS S - - - -

- - - F8 - - - - - - - VSS S - - - -

- - - F9 - - - - - - - VSS S - - - -

- - - F10 - - - - - - - VSS S - - - -

- - - G6 - - - - - - - VSS S - - - -

- - - G7 - - - - - - - VSS S - - - -

- - - G8 - - - - - - - VSS S - - - -

- - - G9 - - - - - - - VSS S - - - -

- - - G10 - - - - - - - VSS S - - - -

- - - H6 - - - - - - - VSS S - - - -

- - - H7 - - - - - - - VSS S - - - -

- - - H8 - - - - - - - VSS S - - - -

- - - H9 - - - - - - - VSS S - - - -

- - - H10 - - - - - - - VSS S - - - -

- - - J6 - - - - - - - VSS S - - - -

84/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 11. STM32F777xx, STM32F778Ax and STM32F779xx pin and

ball definitions (continued)
Pin Number

STM32F778Ax

Pin name (function after reset

STM32F777xx STM32F779xx

I/O structure
Pin type

Notes
Additional
WLCSP180(1) Alternate functions
functions
UFBGA176
TFBGA100

TFBGA216

TFBGA216
LQFP100

LQFP144

LQFP176

LQFP208

LQFP176

LQFP208

- - - J7 - - - - - - - VSS S - - - -

- - - J8 - - - - - - - VSS S - - - -

- - - J9 - - - - - - - VSS S - - - -

- - - J10 - - - - - - - VSS S - - - -

- - - K6 - - - - - - - VSS S - - - -

- - - K7 - - - - - - - VSS S - - - -

- - - K8 - - - - - - - VSS S - - - -

- - - K9 - - - - - - - VSS S - - - -

- - - K10 - - - - - - - VSS S - - - -

1. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid an extra current consumption in low-power modes. list of pins: PI8, PI12, PI13, PI14, PF6,
PF7, PF8, PF9, PC2, PC3, PC4, PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14,
PK3, PK4, PK5, PK6 and PK7.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os
must not be used as a current source (e.g. to drive an LED).
3. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
4. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).

5. Internally connected to VDD or VSS depending on part number.

DS11243 Rev 7 85/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 12. FMC pin definition

NOR/PSRAM/SR NOR/PSRAM
Pin name NAND16 SDRAM
AM Mux

PF0 A0 - - A0
PF1 A1 - - A1
PF2 A2 - - A2
PF3 A3 - - A3
PF4 A4 - - A4
PF5 A5 - - A5
PF12 A6 - - A6
PF13 A7 - - A7
PF14 A8 - - A8
PF15 A9 - - A9
PG0 A10 - - A10
PG1 A11 - - A11
PG2 A12 - - A12
PG3 A13 - - -
PG4 A14 - - BA0
PG5 A15 - - BA1
PD11 A16 A16 CLE -
PD12 A17 A17 ALE -
PD13 A18 A18 - -
PE3 A19 A19 - -
PE4 A20 A20 - -
PE5 A21 A21 - -
PE6 A22 A22 - -
PE2 A23 A23 - -
PG13 A24 A24 - -
PG14 A25 A25 - -
PD14 D0 DA0 D0 D0
PD15 D1 DA1 D1 D1
PD0 D2 DA2 D2 D2
PD1 D3 DA3 D3 D3
PE7 D4 DA4 D4 D4
PE8 D5 DA5 D5 D5
PE9 D6 DA6 D6 D6
PE10 D7 DA7 D7 D7

86/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Pinouts and pin description

Table 12. FMC pin definition (continued)

NOR/PSRAM/SR NOR/PSRAM
Pin name NAND16 SDRAM
AM Mux

PE11 D8 DA8 D8 D8
PE12 D9 DA9 D9 D9
PE13 D10 DA10 D10 D10
PE14 D11 DA11 D11 D11
PE15 D12 DA12 D12 D12
PD8 D13 DA13 D13 D13
PD9 D14 DA14 D14 D14
PD10 D15 DA15 D15 D15
PH8 D16 - - D16
PH9 D17 - - D17
PH10 D18 - - D18
PH11 D19 - - D19
PH12 D20 - - D20
PH13 D21 - - D21
PH14 D22 - - D22
PH15 D23 - - D23
PI0 D24 - - D24
PI1 D25 - - D25
PI2 D26 - - D26
PI3 D27 - - D27
PI6 D28 - - D28
PI7 D29 - - D29
PI9 D30 - - D30
PI10 D31 - - D31
PD7 NE1 NE1 - -
PG6 NE3 - - -
PG9 NE2 NE2 NCE -
PG10 NE3 NE3 - -
PG11 - - - -
PG12 NE4 NE4 - -
PD3 CLK CLK - -
PD4 NOE NOE NOE -
PD5 NWE NWE NWE -
PD6 NWAIT NWAIT NWAIT -

DS11243 Rev 7 87/255

102
Pinouts and pin description STM32F777xx STM32F778Ax STM32F779xx

Table 12. FMC pin definition (continued)

NOR/PSRAM/SR NOR/PSRAM
Pin name NAND16 SDRAM
AM Mux

PB7 NADV NADV - -

PF6 - - - -
PF7 - - - -
PF8 - - - -
PF9 - - - -
PF10 - - - -
PG6 - - - -
PG7 - - INT -
PE0 NBL0 NBL0 - NBL0
PE1 NBL1 NBL1 - NBL1
PI4 NBL2 - - NBL2
PI5 NBL3 - - NBL3
PG8 - - - SDCLK
PC0 - - - SDNWE
PF11 - - - SDNRAS
PG15 - - - SDNCAS
PH2 - - - SDCKE0
PH3 - - - SDNE0
PH6 - - - SDNE1
PH7 - - - SDCKE1
PH5 - - - SDNWE
PC2 - - - SDNE0
PC3 - - - SDCKE0
PC6 NWAIT NWAIT NWAIT -
PB5 - - - SDCKE1
PB6 - - - SDNE1

88/255 DS11243 Rev 7

 STM32F777xx STM32F778Ax STM32F779xx
Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
function mapping
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

TIM2_C
TIM5_C TIM8_ET USART2 UART4_ SAI2_SD_ ETH_MII_ EVEN
PA0 - H1/TIM2 - - - - - - -
H1 R _CTS TX B CRS TOUT
_ETR

ETH_MII_
QUADSP RX_CLK/
TIM2_C TIM5_C USART2 UART4_ SAI2_MC EVEN
PA1 - - - - - I_BK1_IO ETH_RMI - - LCD_R2
H2 H2 _RTS RX K_B TOUT
3 I_REF_C
LK
DS11243 Rev 7

TIM2_C TIM5_C TIM9_CH USART2 SAI2_SC ETH_MDI MDIOS_ EVEN

PA2 - - - - - - - LCD_R1
H3 H3 1 _TX K_B O MDIO TOUT

TIM2_C TIM5_C TIM9_CH USART2 OTG_HS_ ETH_MII_ EVEN

PA3 - - - - - LCD_B2 - - LCD_B5
H4 H4 2 _RX ULPI_D0 COL TOUT

SPI1_NS SPI3_NS
USART2 SPI6_NS OTG_HS DCMI_H LCD_VS EVEN
PA4 - - - - - S/I2S1_ S/I2S3_ - - -
_CK S _SOF SYNC YNC TOUT
WS WS

Port A TIM2_C SPI1_SC

TIM8_CH SPI6_SC OTG_HS_ EVEN
PA5 - H1/TIM2 - - K/I2S1_ - - - - - - LCD_R4
1N K ULPI_CK TOUT
_ETR CK

TIM1_B TIM3_C TIM8_BKI SPI1_MI SPI6_MI TIM13_C MDIOS_ DCMI_PI EVEN

PA6 - - - - - - LCD_G2
KIN H1 N SO SO H1 MDC XCLK TOUT

Pinouts and pin description

ETH_MII_
SPI1_M
TIM1_C TIM3_C TIM8_CH SPI6_MO TIM14_C RX_DV/E FMC_SD EVEN
PA7 - - OSI/I2S1 - - - - -
H1N H2 1N SI H1 TH_RMII_ NWE TOUT
_SD
CRS_DV

TIM1_C TIM8_BKI I2C3_SC USART1 OTG_FS_ CAN3_R UART7_ EVEN

PA8 MCO1 - - - - - LCD_B3 LCD_R6
H1 N2 L _CK SOF X RX TOUT

SPI2_SC
TIM1_C I2C3_SM USART1 DCMI_D EVEN
PA9 - - - K/I2S2_ - - - - - - LCD_R5
H2 BA _TX 0 TOUT
CK

TIM1_C USART1 OTG_FS_ MDIOS_ DCMI_D EVEN

PA10 - - - - - - - LCD_B4 - LCD_B1
89/255

H3 _RX ID MDIO 1 TOUT

 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
90/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

SPI2_NS
TIM1_C UART4_ USART1 CAN1_R OTG_FS_ EVEN
PA11 - - - - S/I2S2_ - - - - LCD_R4
H4 RX _CTS X DM TOUT
WS

SPI2_SC
TIM1_ET UART4_ USART1 SAI2_FS CAN1_T OTG_FS_ EVEN
PA12 - - - - K/I2S2_ - - - LCD_R5
R TX _RTS _B X DP TOUT
CK

Port A JTMS- EVEN

PA13 - - - - - - - - - - - - - -
SWDIO TOUT
DS11243 Rev 7

JTCK- EVEN
PA14 - - - - - - - - - - - - - -
SWCLK TOUT

TIM2_C SPI1_NS SPI3_NS

HDMI- SPI6_NS UART4_ UART7_ EVEN
PA15 JTDI H1/TIM2 - - S/I2S1_ S/I2S3_ - - CAN3_TX - -
CEC S RTS TX TOUT
_ETR WS WS

TIM1_C TIM3_C TIM8_CH DFSDM1 UART4_ OTG_HS_ ETH_MII_ EVEN

STM32F777xx STM32F778Ax STM32F779xx

PB0 - - - - LCD_R3 - - LCD_G1
H2N H3 2N _CKOUT CTS ULPI_D1 RXD2 TOUT

TIM1_C TIM3_C TIM8_CH DFSDM1 OTG_HS_ ETH_MII_ EVEN

PB1 - - - - - LCD_R6 - - LCD_G0
H3N H4 3N _DATIN1 ULPI_D2 RXD3 TOUT

SPI3_MO
SAI1_SD QUADSP DFSDM1_ EVEN
PB2 - - - - - -
_A
SI/I2S3_ - I_CLK CKIN1
- - - -
TOUT
SD

JTDO/T SPI1_SC SPI3_SC

TIM2_C SPI6_SC SDMMC2 CAN3_R UART7_ EVEN
PB3 RACES - - - K/I2S1_ K/I2S3_ - - - -
H2 K _D2 X RX TOUT
Port B WO CK CK

SPI2_NS
TIM3_C SPI1_MI SPI3_MI SPI6_MI SDMMC2 UART7_ EVEN
PB4 NJTRST - - - S/I2S2_ - CAN3_TX - -
H1 SO SO SO _D3 TX TOUT
WS

SPI1_M SPI3_M
UART5_ TIM3_C I2C1_SM SPI6_MO CAN2_R OTG_HS_ ETH_PPS FMC_SD DCMI_D EVEN
PB5 - - OSI/I2S1 OSI/I2S3 - LCD_G7
RX H2 BA SI X ULPI_D7 _OUT CKE1 10 TOUT
_SD _SD

QUADSPI
UART5_ TIM4_C HDMI- I2C1_SC DFSDM1 USART1 CAN2_T I2C4_SC FMC_SD DCMI_D EVEN
PB6 - - - _BK1_NC -
TX H1 CEC L _DATIN5 _TX X L NE1 5 TOUT
S
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

TIM4_C I2C1_SD DFSDM1 USART1 I2S4_SD DCMI_V EVEN

PB7 - - - - - - - FMC_NL -
H2 A _CKIN5 _RX A SYNC TOUT

I2C4_SC TIM4_C TIM10_C I2C1_SC DFSDM1 UART5_ CAN1_R SDMMC2 ETH_MII_ SDMMC DCMI_D EVEN
PB8 - - - LCD_B6
L H3 H1 L _CKIN7 RX X _D4 TXD3 _D4 6 TOUT

SPI2_NS
I2C4_SD TIM4_C TIM11_CH I2C1_SD DFSDM1 UART5_T CAN1_T SDMMC2 I2C4_SM SDMMC DCMI_D EVEN
PB9 - S/I2S2_ - LCD_B7
A H4 1 A _DATIN7 X X _D5 BA _D5 7 TOUT
WS

-
SPI2_SC
TIM2_C I2C2_SC DFSDM1 USART3 QUADSP OTG_HS_ ETH_MII_ EVEN
DS11243 Rev 7

PB10 - - - K/I2S2_ - - - LCD_G4

H3 L _DATIN7 _TX I_BK1_N ULPI_D3 RX_ER TOUT
CK
CS

ETH_MII_
TIM2_C I2C2_SD DFSDM1 USART3 OTG_HS_ TX_EN/E EVEN
PB11 - - - - - - - DSI_TE LCD_G5
H4 A _CKIN7 _RX ULPI_D4 TH_RMII_ TOUT
Port B
TX_EN

ETH_MII_
SPI2_NS
TIM1_B I2C2_SM DFSDM1 USART3 UART5_ CAN2_R OTG_HS_ TXD0/ET OTG_HS EVEN
PB12 - - - S/I2S2_ - -
KIN BA _DATIN1 _CK RX X ULPI_D5 H_RMII_T _ID TOUT
WS
XD0

ETH_MII_
SPI2_SC
TIM1_C DFSDM1 USART3 UART5_T CAN2_T OTG_HS_ TXD1/ET EVEN
PB13 - - - - K/I2S2_ - - -
H1N _CKIN1 _CTS X X ULPI_D6 H_RMII_T TOUT
CK

Pinouts and pin description

XD1

TIM1_C TIM8_CH USART1_ SPI2_MI DFSDM1 USART3 UART4_ TIM12_C SDMMC2 OTG_HS EVEN
PB14 - - - - -
H2N 2N TX SO _DATIN2 _RTS RTS H1 _D0 _DM TOUT

SPI2_M
RTC_RE TIM1_C TIM8_CH USART1_ DFSDM1 UART4_ TIM12_C SDMMC2 OTG_HS EVEN
PB15 - OSI/I2S2 - - - -
FIN H3N 3N RX _CKIN2 CTS H2 _D1 _DP TOUT
_SD
91/255
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
92/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

OTG_HS_
DFSDM1_ DFSDM1 SAI2_FS FMC_SD EVEN
PC0 - - - - - - - ULPI_ST - - LCD_R5
CKIN0 _DATIN4 _B NWE TOUT
P

SPI2_M
TRACED DFSDM1_ SAI1_SD DFSDM1_ ETH_MD MDIOS_ EVEN
PC1 - - - OSI/I2S2 - - - - -
0 DATAIN0 _A CKIN4 C MDC TOUT
_SD

DFSDM1_ SPI2_MI DFSDM1 OTG_HS_ ETH_MII_ FMC_SD EVEN

PC2 - - - - - - - - -
CKIN1 SO _CKOUT ULPI_DIR TXD2 NE0 TOUT

SPI2_M OTG_HS_
DS11243 Rev 7

DFSDM1_ ETH_MII_ FMC_SD EVEN

PC3 - - - - OSI/I2S2 - - - - ULPI_NX - -
DATAIN1 TX_CLK CKE0 TOUT
_SD T

ETH_MII_
DFSDM1_ I2S1_M SPDIF_R RXD0/ET FMC_SD EVEN
PC4 - - - - - - - - - -
CKIN2 CK X2 H_RMII_ NE0 TOUT
RXD0

STM32F777xx STM32F778Ax STM32F779xx

ETH_MII_
Port C DFSDM1_ SPDIF_R RXD1/ET FMC_SD EVEN
PC5 - - - - - - - - - - -
DATAIN2 X3 H_RMII_ CKE0 TOUT
RXD1

TIM3_C TIM8_CH I2S2_M DFSDM1 USART6 FMC_NW SDMMC2 SDMMC DCMI_D LCD_HS EVEN
PC6 - - - - -
H1 1 CK _CKIN3 _TX AIT _D6 _D6 0 YNC TOUT

DFSDM1
TIM3_C TIM8_ I2S3_M USART6 FMC_NE SDMMC2 SDMMC DCMI_D EVEN
PC7 - - - - _DATAIN - LCD_G6
H2 CH2 CK _RX 1 _D7 _D7 1 TOUT
3

FMC_NE
TRACED TIM3_C TIM8_ UART5_ USART6 SDMMC DCMI_D EVEN
PC8 - - - - 2/FMC_N - - -
1 H3 CH3 RTS _CK _D0 2 TOUT
CE

QUADSP
TIM3_C TIM8_ I2C3_SD I2S_CKI UART5_ SDMMC DCMI_D EVEN
PC9 MCO2 - - - I_BK1_IO LCD_G3 - LCD_B2
H4 CH4 A N CTS _D1 3 TOUT
0

SPI3_SC QUADSP
DFSDM1_ USART3 UART4_T SDMMC DCMI_D EVEN
PC10 - - - - - K/I2S3_ I_BK1_IO - - LCD_R2
CKIN5 _TX X _D2 8 TOUT
CK 1
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

QUADSP
DFSDM1_ SPI3_MI USART3 UART4_ SDMMC DCMI_D EVEN
PC11 - - - - - I_BK2_N - - -
DATAIN5 SO _RX RX _D3 4 TOUT
CS

SPI3_M
TRACED USART3 UART5_T SDMMC DCMI_D EVEN
PC12 - - - - - OSI/I2S3 - - - -
3 _CK X _CK 9 TOUT
_SD
Port C
EVEN
PC13 - - - - - - - - - - - - - - -
TOUT

EVEN
DS11243 Rev 7

PC14 - - - - - - - - - - - - - - -
TOUT

EVEN
PC15 - - - - - - - - - - - - - - -
TOUT

DFSDM1
DFSDM1_ UART4_ CAN1_R EVEN
PD0 - - - - - _DATAIN - - - FMC_D2 - -
CKIN6 RX X TOUT
7

DFSDM1_ DFSDM1 UART4_T CAN1_T EVEN

PD1 - - - - - - - - FMC_D3 - -
DATAIN6 _CKIN7 X X TOUT

TRACED TIM3_ET UART5_ SDMMC DCMI_D EVEN

PD2 - - - - - - - - - -
2 R RX _CMD 11 TOUT

SPI2_SC DFSDM1
DFSDM1_ USART2 FMC_CL DCMI_D EVEN
PD3 - - - - K/I2S2_ _DATAIN - - - - LCD_G7

Pinouts and pin description

CKOUT _CTS K 5 TOUT
CK 0
Port D
DFSDM1 USART2 FMC_N EVEN
PD4 - - - - - - - - - - - -
_CKIN0 _RTS OE TOUT

USART2 FMC_N EVEN

PD5 - - - - - - - - - - - - -
_TX WE TOUT

SPI3_M
DFSDM1_ SAI1_SD USART2 DFSDM1_ SDMMC2 FMC_N DCMI_D EVEN
PD6 - - - - OSI/I2S3 - - LCD_B2
CKIN4 _A _RX DATAIN1 _CK WAIT 10 TOUT
_SD

SPI1_M
DFSDM1_ DFSDM1 USART2 SPDIF_R SDMMC2 FMC_NE EVEN
93/255

PD7 - - - - OSI/I2S1 - - - -
DATAIN4 _CKIN1 _CK X0 _CMD 1 TOUT
_SD
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
94/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

DFSDM1_ USART3 SPDIF_R FMC_D1 EVEN

PD8 - - - - - - - - - - -
CKIN3 _TX X1 3 TOUT

DFSDM1_ USART3 FMC_D1 EVEN

PD9 - - - - - - - - - - - -
DATAIN3 _RX 4 TOUT

DFSDM1_ USART3 FMC_D1 EVEN

PD10 - - - - - - - - - - - LCD_B3
CKOUT _CK 5 TOUT

QUADSP FMC_A1
I2C4_SM USART3 SAI2_SD_ EVEN
PD11 - - - - - - - I_BK1_IO - 6/FMC_ - -
BA _CTS A TOUT
0 CLE
DS11243 Rev 7

Port D QUADSP FMC_A1

TIM4_C LPTIM1_I I2C4_SC USART3 SAI2_FS_ EVEN
PD12 - - - - - I_BK1_IO - 7/FMC_ - -
H1 N1 L _RTS A TOUT
1 ALE

QUADSP
TIM4_C LPTIM1_ I2C4_SD SAI2_SC FMC_A1 EVEN
PD13 - - - - - - I_BK1_IO - - -

STM32F777xx STM32F778Ax STM32F779xx

H2 OUT A K_A 8 TOUT
3

TIM4_C UART8_ EVEN

PD14 - - - - - - - - - - FMC_D0 - -
H3 CTS TOUT

TIM4_C UART8_ EVEN

PD15 - - - - - - - - - - FMC_D1 - -
H4 RTS TOUT

TIM4_ET LPTIM1_E UART8_ SAI2_MC FMC_NB DCMI_D EVEN

PE0 - - - - - - - - -
R TR Rx K_A L0 2 TOUT

LPTIM1_I UART8_T FMC_NB DCMI_D EVEN

PE1 - - - - - - - - - - -
N2 x L1 3 TOUT
Port E
QUADSP
TRACEC SPI4_SC SAI1_M ETH_MII_ FMC_A2 EVEN
PE2 - - - - - - I_BK1_IO - - -
LK K CLK_A TXD3 3 TOUT
2

TRACED SAI1_SD FMC_A1 EVEN

PE3 - - - - - - - - - - - -
0 _B 9 TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

TRACED SPI4_NS SAI1_FS DFSDM1_ FMC_A2 DCMI_D EVEN

PE4 - - - - - - - - LCD_B0
1 S _A DATAIN3 0 4 TOUT

TRACED TIM9_CH SPI4_MI SAI1_SC DFSDM1_ FMC_A2 DCMI_D EVEN

PE5 - - - - - - - LCD_G0
2 1 SO K_A CKIN3 1 6 TOUT

TRACED TIM1_B TIM9_CH SPI4_M SAI1_SD SAI2_MC FMC_A2 DCMI_D EVEN

PE6 - - - - - - LCD_G1
3 KIN2 2 OSI _A K_B 2 7 TOUT

DFSDM1
TIM1_ET UART7_ QUADSPI EVEN
PE7 - - - - - _DATAIN - - - FMC_D4 - -
R Rx _BK2_IO0 TOUT
2
DS11243 Rev 7

TIM1_C DFSDM1 UART7_T QUADSPI EVEN

PE8 - - - - - - - - FMC_D5 - -
H1N _CKIN2 x _BK2_IO1 TOUT

TIM1_C DFSDM1 UART7_ QUADSPI EVEN

PE9 - - - - - - - - FMC_D6 - -
H1 _CKOUT RTS _BK2_IO2 TOUT
Port E
DFSDM1
TIM1_C UART7_ QUADSPI EVEN
PE10 - - - - - _DATAIN - - - FMC_D7 - -
H2N CTS _BK2_IO3 TOUT
4

TIM1_C SPI4_NS DFSDM1 SAI2_SD_ EVEN

PE11 - - - - - - - - FMC_D8 - LCD_G3
H2 S _CKIN4 B TOUT

DFSDM1
TIM1_C SPI4_SC SAI2_SC EVEN
PE12 - - - - _DATAIN - - - - FMC_D9 - LCD_B4
H3N K K_B TOUT
5

Pinouts and pin description

TIM1_C SPI4_MI DFSDM1 SAI2_FS_ FMC_D1 EVEN
PE13 - - - - - - - - - LCD_DE
H3 SO _CKIN5 B 0 TOUT

TIM1_C SPI4_M SAI2_MC FMC_D1 LCD_CL EVEN

PE14 - - - - - - - - - -
H4 OSI K_B 1 K TOUT

TIM1_B FMC_D1 EVEN

PE15 - - - - - - - - - - - - LCD_R7
KIN 2 TOUT
95/255
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
96/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

I2C2_SD EVEN
PF0 - - - - - - - - - - - FMC_A0 - -
A TOUT

I2C2_SC EVEN
PF1 - - - - - - - - - - - FMC_A1 - -
L TOUT

I2C2_SM EVEN
PF2 - - - - - - - - - - - FMC_A2 - -
BA TOUT

EVEN
PF3 - - - - - - - - - - - - FMC_A3 - -
TOUT
DS11243 Rev 7

EVEN
PF4 - - - - - - - - - - - - FMC_A4 - -
TOUT

EVEN
PF5 - - - - - - - - - - - - FMC_A5 - -
TOUT

Port F QUADSP
TIM10_C SPI5_NS SAI1_SD UART7_ EVEN

STM32F777xx STM32F778Ax STM32F779xx

PF6 - - - - - I_BK1_IO - - - - -
H1 S _B Rx TOUT
3

QUADSP
TIM11_CH SPI5_SC SAI1_M UART7_T EVEN
PF7 - - - - - I_BK1_IO - - - - -
1 K CLK_B x TOUT
2

SPI5_MI SAI1_SC UART7_ TIM13_C QUADSPI EVEN

PF8 - - - - - - - - - -
SO K_B RTS H1 _BK1_IO0 TOUT

SPI5_M SAI1_FS UART7_ TIM14_C QUADSPI EVEN

PF9 - - - - - - - - - -
OSI _B CTS H1 _BK1_IO1 TOUT

QUADSP DCMI_D EVEN

PF10 - - - - - - - - - - - - LCD_DE
I_CLK 11 TOUT

SPI5_M SAI2_SD_ FMC_SD DCMI_D EVEN

PF11 - - - - - - - - - - -
OSI B NRAS 12 TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

EVEN
PF12 - - - - - - - - - - - - FMC_A6 - -
TOUT

DFSDM1
I2C4_SM EVEN
PF13 - - - - - _DATAIN - - - - - FMC_A7 - -
BA TOUT
6
Port F
I2C4_SC DFSDM1 EVEN
PF14 - - - - - - - - - - FMC_A8 - -
L _CKIN6 TOUT

I2C4_SD EVEN
PF15 - - - - - - - - - - - FMC_A9 - -
A TOUT
DS11243 Rev 7

FMC_A1 EVEN
PG0 - - - - - - - - - - - - - -
0 TOUT

FMC_A1 EVEN
PG1 - - - - - - - - - - - - - -
1 TOUT

FMC_A1 EVEN
PG2 - - - - - - - - - - - - - -
2 TOUT

FMC_A1 EVEN
PG3 - - - - - - - - - - - - - -
3 TOUT

Port G FMC_A1
EVEN
PG4 - - - - - - - - - - - - 4/FMC_ - -
TOUT
BA0

Pinouts and pin description

FMC_A1
EVEN
PG5 - - - - - - - - - - - - 5/FMC_ - -
TOUT
BA1

FMC_NE DCMI_D EVEN

PG6 - - - - - - - - - - - - LCD_R7
3 12 TOUT

SAI1_M USART6 FMC_IN DCMI_D LCD_CL EVEN

PG7 - - - - - - - - - -
CLK_A _CK T 13 K TOUT
97/255
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
98/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

SPI6_NS SPDIF_R USART6 ETH_PPS FMC_SD EVEN

PG8 - - - - - - - - - LCD_G7
S X2 _RTS _OUT CLK TOUT

QUADSP FMC_NE
SPI1_MI SPDIF_R USART6 SAI2_FS_ SDMMC2 DCMI_V EVEN
PG9 - - - - - - I_BK2_IO 2/FMC_ -
SO X3 _RX B _D0 SYNC TOUT
2 NCE

SPI1_NS
SAI2_SD_ SDMMC2 FMC_NE DCMI_D EVEN
PG10 - - - - - S/I2S1_ - - - LCD_G3 LCD_B2
B _D1 3 2 TOUT
WS

ETH_MII_
DS11243 Rev 7

SPI1_SC
SPDIF_R SDMMC2 TX_EN/E DCMI_D EVEN
PG11 - - - - - K/I2S1_ - - - - LCD_B3
X0 _D2 TH_RMII_ 3 TOUT
CK
TX_EN
Port G
LPTIM1_I SPI6_MI SPDIF_R USART6 SDMMC2 FMC_NE EVEN
PG12 - - - - - LCD_B4 - - LCD_B1
N1 SO X1 _RTS _D3 4 TOUT

STM32F777xx STM32F778Ax STM32F779xx

ETH_MII_
TRACED LPTIM1_ SPI6_SC USART6 TXD0/ET FMC_A2 EVEN
PG13 - - - - - - - - LCD_R0
0 OUT K _CTS H_RMII_T 4 TOUT
XD0

ETH_MII_
QUADSP
TRACED LPTIM1_E SPI6_M USART6 TXD1/ET FMC_A2 EVEN
PG14 - - - - - I_BK2_IO - - LCD_B0
1 TR OSI _TX H_RMII_T 5 TOUT
3
XD1

USART6 FMC_SD DCMI_D EVEN

PG15 - - - - - - - - - - - -
_CTS NCAS 13 TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

EVEN
PH0 - - - - - - - - - - - - - - -
TOUT

EVEN
PH1 - - - - - - - - - - - - - - -
TOUT

QUADSP
LPTIM1_I SAI2_SC ETH_MII_ FMC_SD EVEN
PH2 - - - - - - - - I_BK2_IO - LCD_R0
N2 K_B CRS CKE0 TOUT
0

QUADSP
SAI2_MC ETH_MII_ FMC_SD EVEN
PH3 - - - - - - - - - I_BK2_IO - LCD_R1
DS11243 Rev 7

K_B COL NE0 TOUT

1

OTG_HS_
I2C2_SC EVEN
PH4 - - - - - - - - LCD_G5 ULPI_NX - - - LCD_G4
L TOUT
T

I2C2_SD SPI5_NS FMC_SD EVEN

PH5 - - - - - - - - - - - -
A S NWE TOUT

I2C2_SM SPI5_SC TIM12_C ETH_MII_ FMC_SD DCMI_D EVEN

Port H PH6 - - - - - - - - -
BA K H1 RXD2 NE1 8 TOUT

I2C3_SC SPI5_MI ETH_MII_ FMC_SD DCMI_D EVEN

PH7 - - - - - - - - - -
L SO RXD3 CKE1 9 TOUT

I2C3_SD FMC_D1 DCMI_H EVEN

PH8 - - - - - - - - - - - LCD_R2
A 6 SYNC TOUT

Pinouts and pin description

I2C3_SM TIM12_C FMC_D1 DCMI_D EVEN
PH9 - - - - - - - - - - LCD_R3
BA H2 7 0 TOUT

TIM5_C I2C4_SM FMC_D1 DCMI_D EVEN

PH10 - - - - - - - - - - LCD_R4
H1 BA 8 1 TOUT

TIM5_C I2C4_SC FMC_D1 DCMI_D EVEN

PH11 - - - - - - - - - - LCD_R5
H2 L 9 2 TOUT

TIM5_C I2C4_SD FMC_D2 DCMI_D EVEN

PH12 - - - - - - - - - - LCD_R6
H3 A 0 3 TOUT
99/255

TIM8_CH UART4_T CAN1_T FMC_D2 EVEN

PH13 - - - - - - - - - - LCD_G2
1N X X 1 TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
100/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

TIM8_CH UART4_ CAN1_R FMC_D2 DCMI_D EVEN

PH14 - - - - - - - - - LCD_G3
2N RX X 2 4 TOUT
Port H
TIM8_CH FMC_D2 DCMI_D EVEN
PH15 - - - - - - - - - - - LCD_G4
3N 3 11 TOUT

SPI2_NS
TIM5_C FMC_D2 DCMI_D EVEN
PI0 - - - - S/I2S2_ - - - - - - LCD_G5
H4 4 13 TOUT
WS

SPI2_SC
TIM8_BKI FMC_D2 DCMI_D EVEN
PI1 - - - - K/I2S2_ - - - - - - LCD_G6
DS11243 Rev 7

N2 5 8 TOUT
CK

TIM8_CH SPI2_MI FMC_D2 DCMI_D EVEN

PI2 - - - - - - - - - - LCD_G7
4 SO 6 9 TOUT

SPI2_M
TIM8_ET FMC_D2 DCMI_D EVEN
PI3 - - - - OSI/I2S2 - - - - - - -

STM32F777xx STM32F778Ax STM32F779xx

R 7 10 TOUT
_SD

TIM8_BKI SAI2_MC FMC_NB DCMI_D EVEN

PI4 - - - - - - - - - - LCD_B4
N K_A L2 5 TOUT

TIM8_CH SAI2_SC FMC_NB DCMI_V EVEN

Port I PI5 - - - - - - - - - - LCD_B5
1 K_A L3 SYNC TOUT

TIM8_CH SAI2_SD_ FMC_D2 DCMI_D EVEN

PI6 - - - - - - - - - - LCD_B6
2 A 8 6 TOUT

TIM8_CH SAI2_FS_ FMC_D2 DCMI_D EVEN

PI7 - - - - - - - - - - LCD_B7
3 A 9 7 TOUT

EVEN
PI8 - - - - - - - - - - - - - - -
TOUT

UART4_ CAN1_R FMC_D3 LCD_VS EVEN

PI9 - - - - - - - - - - -
RX X 0 YNC TOUT

ETH_MII_ FMC_D3 LCD_HS EVEN

PI10 - - - - - - - - - - - -
RX_ER 1 YNC TOUT

OTG_HS_ EVEN
PI11 - - - - - - - - - LCD_G6 - - - -
ULPI_DIR TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate

STM32F777xx STM32F778Ax STM32F779xx

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

LCD_HS EVEN
PI12 - - - - - - - - - - - - - -
YNC TOUT

LCD_VS EVEN
PI13 - - - - - - - - - - - - - -
YNC TOUT
Port I
LCD_CL EVEN
PI14 - - - - - - - - - - - - - -
K TOUT

EVEN
PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0
TOUT
DS11243 Rev 7

EVEN
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1
TOUT

EVEN
PJ1 - - - - - - - - - - - - - - LCD_R2
TOUT

EVEN
PJ2 - - - - - - - - - - - - - DSI_TE LCD_R3
TOUT

EVEN
PJ3 - - - - - - - - - - - - - - LCD_R4
TOUT

EVEN
PJ4 - - - - - - - - - - - - - - LCD_R5
TOUT

EVEN
Port J PJ5 - - - - - - - - - - - - - - LCD_R6
TOUT

Pinouts and pin description

EVEN
PJ6 - - - - - - - - - - - - - - LCD_R7
TOUT

EVEN
PJ7 - - - - - - - - - - - - - - LCD_G0
TOUT

EVEN
PJ8 - - - - - - - - - - - - - - LCD_G1
TOUT

EVEN
PJ9 - - - - - - - - - - - - - - LCD_G2
TOUT
101/255

EVEN
PJ10 - - - - - - - - - - - - - - LCD_G3
TOUT
 Table 13. STM32F777xx, STM32F778Ax and STM32F779xx alternate
102/255

Pinouts and pin description

function mapping (continued)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SPI2/I2S SAI2/QU
SPI2/I2S SPI6/SAI
SPI1/I2S 2/SPI3/I2 CAN1/2/T ADSPI/S UART7/
Port TIM8/9/10/ 2/SPI3/I2 2/USART
I2C4/UA I2C1/2/3/ 1/SPI2/I2 S3/SPI6/ IM12/13/ DMMC2/D I2C4/CAN FMC/SD
11/LPTIM S3/SAI1/ 6/UART4/ DCMI/L
SYS RT5/TIM TIM3/4/5 4/USART S2/SPI3/ USART1/ 14/QUAD FSDM1/O 3/SDMM MMC1/M LCD SYS
1/DFSDM I2C4/UA 5/7/8/OT CD/DSI
1/2 1/CEC I2S3/SPI 2/3/UART SPI/FMC/ TG2_HS/ C2/ETH DIOS/OT
1/CEC RT4/DF G_FS/SP
4/5/6 5/DFSDM LCD OTG1_FS G2_FS
SDM1 DIF
1/SPDIF /LCD

EVEN
PJ11 - - - - - - - - - - - - - - LCD_G4
TOUT

EVEN
PJ12 - - - - - - - - - LCD_G3 - - - - LCD_B0
TOUT

EVEN
Port J PJ13 - - - - - - - - - LCD_G4 - - - - LCD_B1
TOUT

EVEN
PJ14 - - - - - - - - - - - - - - LCD_B2
TOUT
DS11243 Rev 7

EVEN
PJ15 - - - - - - - - - - - - - - LCD_B3
TOUT

EVEN
PK0 - - - - - - - - - - - - - - LCD_G5
TOUT

EVEN
PK1 - - - - - - - - - - - - - - LCD_G6

STM32F777xx STM32F778Ax STM32F779xx

TOUT

EVEN
PK2 - - - - - - - - - - - - - - LCD_G7
TOUT

EVEN
PK3 - - - - - - - - - - - - - - LCD_B4
TOUT
Port K
EVEN
PK4 - - - - - - - - - - - - - - LCD_B5
TOUT

EVEN
PK5 - - - - - - - - - - - - - - LCD_B6
TOUT

EVEN
PK6 - - - - - - - - - - - - - - LCD_B7
TOUT

EVEN
PK7 - - - - - - - - - - - - - - LCD_DE
TOUT
STM32F777xx STM32F778Ax STM32F779xx Memory mapping

5 Memory mapping

Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.

DS11243 Rev 7 103/255

103
Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 22.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 23.

Figure 22. Pin loading conditions Figure 23. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19011V2 MS19010V2

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STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics

6.1.6 Power supply scheme

Figure 24. STM32F769xx/STM32F779xx power supply scheme

VBAT

Backup circuitry
VBAT = Power switch (OSC32K,RTC,
1.65 to 3.6V Wakeup logic
Backup registers,
backup RAM)

Level shifter
OUT
IO
GP I/Os Logic
IN

VDDSDMMC

Level shifter
OUT
IO
PG[9..12], PD[6,7]
Logic
IN Kernel logic
(CPU,
VCAP_1
VCAP_2 digital
2 × 2.2 μF & RAM)
VDD
VDD Voltage
1/2/...14/20
regulator
20 × 100 nF VSS
+ 1 × 4.7 μF 1/2/...14/20

BYPASS_REG Flash memory

VDDUSB
VDDUSB
OTG FS
100 nF PHY
+ 1 μF
VDDDSI
DSI
VCAPDSI
voltage
regulator

VDD12DSI
DSI
2.2 μF PHY
VSSDSI

Reset
PDR_ON controller
VDD
VDDA

VREF
VREF+

100 nF Analog:
100 nF VREF- ADC RCs, PLL,
+ 1 μF + 1 μF
...
VSSA

MSv39619V1

DS11243 Rev 7 105/255

219
Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx

Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme

V BAT

backup circuitry
Power switch (OSC32K, RTC,
VBAT =
1.65 to 3.6V Wakeup logic,
Backup registers,
backup RAM)

Level shifter
OUT
IO
GP I/O s Logic
V IN
DDSDMMC
V
DDSDMMC
100 nF

Level shifter
+ 1 μF OUT
PG[9..12], PD[6,7]
IO

IN
Logic

Level shifter
OUT
PA[11,12], PB[14,15]
IO
V DDUSB
IN
Logic
VDDUSB

100 nF
+ 1 μF
OTG FS
PHY Kernel logic

V CAP_1
(CPU,
V CAP_2 digital
2 × 2.2 μF
& RAM)
V DD
V DD
1/2/...14/20
Voltage
regulator
20 × 100nF V SS
+ 1 × 4.7 μF 1/2/...14/20

BYPASS_REG Flash memory

Reset
PDR_ON controller

V DD
V DDA

V REF
V REF+

100 nF Analog:
100 nF V REF- ADC
+ 1 μF + 1 μF RCs,...PLL,

V SSA

MSv41016V1

1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.18: Power supply supervisor and
Section 3.19: Voltage regulator.
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA=VDD and VSSA=VSS.

106/255 DS11243 Rev 7

STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

Figure 26. Current consumption measurement scheme

IDD_VBAT
VBAT

IDD
VDD

VDDA

ai14126

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. The device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission
profiles are available on demand.

Table 14. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage (including VDDA, VDD,

VDD–VSS − 0.3 4.0
VBAT, VDDUSB, VDDDSI (1) and VDDSDMMC)(2)
Input voltage on FT pins(3) VSS − 0.3 VDD+4.0
V
Input voltage on TTa pins VSS − 0.3 4.0
VIN
Input voltage on any other pin VSS − 0.3 4.0
Input voltage on BOOT pin VSS 9.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX −VSS| Variations between all the different ground pins(4) - 50
see Section 6.3.18:
Absolute maximum
VESD(HBM) Electrostatic discharge voltage (human body model) -
ratings (electrical
sensitivity)

DS11243 Rev 7 107/255

219
Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx

1. Applicable only for STM32F7x9 sales types.

2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
3. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
4. Include VREF- pin.

Table 15. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 420
(1)
Σ IVSS Total current out of sum of all VSS_x ground lines (sink) −420
Σ IVDDUSB Total current into VDDUSB power line (source) 25
Σ IVDDSDMMC Total current into VDDSDMMC power line (source) 60
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVDDSDMMC Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100
(1)
IVSS Maximum current out of each VSS_x ground line (sink) −100
Output current sunk by any I/O and control pin 25
IIO mA
Output current sourced by any I/Os and control pin −25
Total output current sunk by sum of all I/O and control pins (2) 120
Total output current sunk by sum of all USB I/Os 25
ΣIIO
Total output current sunk by sum of all SDMMC I/Os 120
Total output current sourced by sum of all I/Os and control pins except USB I/Os(2) −120
Injected current on FT, FTf, RST and B pins (3) −5/+0
IINJ(PIN)
Injected current on TTa pins(4) ±5

ΣIINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(5) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 14: Voltage characteristics for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).

Table 16. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range − 65 to +150

°C
TJ Maximum junction temperature 125

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6.3 Operating conditions

6.3.1 General operating conditions

Table 17. General operating conditions

Symbol Parameter Conditions(1) Min Typ Max Unit

Power Scale 3 (VOS[1:0] bits in

PWR_CR register = 0x01), Regulator 0 - 144
ON, over-drive OFF
Over-
drive - 168
Power Scale 2 (VOS[1:0] bits OFF
in PWR_CR register = 0x10), 0
Regulator ON Over-
fHCLK Internal AHB clock frequency drive - 180
ON
Over-
MHz
drive - 180
Power Scale 1 (VOS[1:0] bits OFF
in PWR_CR register= 0x11), 0
Regulator ON Over-
drive - 216(2)
ON
Over-drive OFF 0 - 45
fPCLK1 Internal APB1 clock frequency
Over-drive ON 0 - 54
Over-drive OFF 0 - 90
fPCLK2 Internal APB2 clock frequency
Over-drive ON 0 - 108
VDD Standard operating voltage - 1.7(3) - 3.6
Analog operating voltage
1.7(3) - 2.4
(ADC limited to 1.2 M samples)
VDDA(4)(5) Must be the same potential as VDD(6)
Analog operating voltage
2.4 - 3.6
(ADC limited to 2.4 M samples)
USB supply voltage (supply USB not used 1.7 3.3 3.6
VDDUSB voltage for PA11,PA12, PB14 V
and PB15 pins) USB used 3.0 - 3.6

VBAT Backup operating voltage - 1.65 - 3.6

SDMMC2 supply voltage (supply
VDDSDMMC voltage for PG[12:9] and PD6 It can be different from VDD - 1.7 - 3.6
pins)
VDDDSI DSI system operating - 1.7 - 3.6

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Table 17. General operating conditions (continued)

Symbol Parameter Conditions(1) Min Typ Max Unit

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 144 MHz 1.08 1.14 1.20
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 168 MHz
Regulator ON: 1.2 V internal 1.20 1.26 1.32
HCLK max frequency with over-drive
voltage on VCAP_1/VCAP_2 pins
OFF or 180 MHz with over-drive ON
V12 Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 180 MHz
1.26 1.32 1.40
HCLK max frequency with over-drive
OFF or 216 MHz with over-drive ON V
Regulator OFF: 1.2 V external Max frequency 144 MHz 1.10 1.14 1.20
voltage must be supplied from
Max frequency 168MHz 1.20 1.26 1.32
external regulator on
VCAP_1/VCAP_2 pins(7) Max frequency 180 MHz 1.26 1.32 1.38

Input voltage on RST and FT 2 V ≤VDD ≤3.6 V − 0.3 - 5.5

pins(8) VDD ≤2 V − 0.3 - 5.2
VIN VDDA+
Input voltage on TTa pins - − 0.3 -
0.3
Input voltage on BOOT pin - 0 - 9
LQFP100 - - 465
WLCSP180 - - 641
LQFP144 - - 500
Power dissipation at TA = 85 °C LQFP176 - - 526
PD for suffix 6 or TA = 105 °C for mW
suffix 7(9) UFBGA176 - - 513
LQFP208 - - 1053
TFBGA216 - - 690
TFBGA100 - - 552

Ambient temperature for 6 suffix Maximum power dissipation − 40 - 85

°C
version Low power dissipation(10) − 40 - 105
TA
Ambient temperature for 7 suffix Maximum power dissipation − 40 - 105
°C
version Low power dissipation(10) − 40 - 125
6 suffix version − 40 - 105
TJ Junction temperature range °C
7 suffix version − 40 - 125
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
4. When the ADC is used, refer to Table 72: ADC characteristics.
5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

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6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 18. Limitations depending on the operating power supply range

Maximum Flash
Maximum HCLK
Operating memory access Possible Flash
frequency vs Flash
power supply ADC operation frequency with I/O operation memory
memory wait states
range no wait states (1)(2) operations
(fFlashmax)

180 MHz with 8 wait 8-bit erase and

VDD =1.7 to Conversion time No I/O
20 MHz states and over-drive program
2.1 V(3) up to 1.2 Msps compensation
OFF operations only
216 MHz with 9 wait 16-bit erase and
VDD = 2.1 to Conversion time No I/O
22 MHz states and over-drive program
2.4 V up to 1.2 Msps compensation
ON operations
216 MHz with 8 wait 16-bit erase and
VDD = 2.4 to Conversion time I/O compensation
24 MHz states and over-drive program
2.7 V up to 2.4 Msps works
ON operations
216 MHz with 6 wait 32-bit erase and
VDD = 2.7 to Conversion time I/O compensation
30 MHz states and over-drive program
3.6 V(4) up to 2.4 Msps works
ON operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins are degraded between 2.7 and 3 V.

6.3.2 VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 19.

Figure 27. External capacitor CEXT

ESR

R Leak
MS19044V2

1. Legend: ESR is the equivalent series resistance.

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Table 19. VCAP1/VCAP2 operating conditions(1)

Symbol Parameter Conditions

CEXT Capacitance of external capacitor 2.2 µF

ESR ESR of external capacitor <2Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.

6.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for TA.

Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit

VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞

6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.

Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)

Symbol Parameter Conditions Min Max Unit

VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.

6.3.5 Reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

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Table 22. Reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V

PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V

Programmable voltage PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V

VPVD
detector level selection PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V
PLS[2:0]=101 (falling edge) 2.75 2.84 2.92 V
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V
VPVDhyst(1) PVD hysteresis - - 100 - mV

Power-on/power-down Falling edge 1.60 1.68 1.76 V

VPOR/PDR
reset threshold Rising edge 1.64 1.72 1.80 V
VPDRhyst(1) PDR hysteresis - - 40 - mV

Brownout level 1 Falling edge 2.13 2.19 2.24 V

VBOR1
threshold Rising edge 2.23 2.29 2.33 V

Brownout level 2 Falling edge 2.44 2.50 2.56 V

VBOR2
threshold Rising edge 2.53 2.59 2.63 V

Brownout level 3 Falling edge 2.75 2.83 2.88 V

VBOR3
threshold Rising edge 2.85 2.92 2.97 V
VBORhyst(1) BOR hysteresis - - 100 - mV
TRSTTEMPO
(1)(2) POR reset temporization - 0.5 1.5 3.0 ms

InRush current on
voltage regulator power-
IRUSH(1) - - 160 250 mA
on (POR or wakeup
from Standby)
InRush energy on
voltage regulator power- VDD = 1.7 V, TA = 105 °C,
ERUSH(1) - - 5.4 µC
on (POR or wakeup IRUSH = 171 mA for 31 µs
from Standby)

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1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.

6.3.6 Over-drive switching characteristics

When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are subject to general
operating conditions for TA.

Table 23. Over-drive switching characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

HSI - 45 -
HSE max for 4 MHz
Over_drive switch 45 - 100
Tod_swen and min for 26 MHz
enable time
External HSE
- 40 -
50 MHz
µs
HSI - 20 -
HSE max for 4 MHz
Over_drive switch 20 - 80
Tod_swdis and min for 26 MHz.
disable time
External HSE
- 15 -
50 MHz
1. Guaranteed by design.

6.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 26: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.

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Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 18: Limitations depending on the operating power supply range).
• When the regulator is ON, the voltage scaling and over-drive mode are adjusted to
fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 144 MHz
– Scale 2 for 144 MHz < fHCLK ≤ 168 MHz
– Scale 1 for 168 MHz < fHCLK ≤ 216 MHz. The over-drive is only ON at 216 MHz.
• When the regulator is OFF, the V12 is provided externally as described in Table 17:
General operating conditions:
• The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
• External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
• The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage
range and for TA= 25 °C unless otherwise specified.
• The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA) unless otherwise specified.
• For the voltage range 1.7 V ≤ VDD ≤ 3.6 V, the maximum frequency is 180 MHz.

Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C

216 193 221(4) 258(4) -

200 179 207 244 279
(4)
180 159 176 210(4) 238(4)
All peripherals
168 142 156 187 211
enabled(2)(3)
144 122 135 167 190
60 49 55 81 103
Supply 25 23 28 54 76
IDD current in mA
RUN mode 216 95 107(4) 153(4) -
200 88 100 146 180
180 78 88(4) 122(4) 147(4)
All peripherals
168 70 78 109 133
disabled(3)
144 60 68 99 123
60 24 29 55 76
25 12 16 42 63
1. Guaranteed by characterization results, unless otherwise specified.

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2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
4. Guaranteed by test in production.

Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C

216 190 219 255 -

200 177 205 241 268
180 157 173 208 228
All peripherals
168 139 153 185 204
enabled(2)(3)
144 107 117 144 161
60 48 54 81 98
Supply 25 23 28 54 71 mA
IDD current in
RUN mode 216 92 104 150 -
200 86 97 143 170
180 76 85 119 140
All peripherals
168 67 75 107 126
disabled(3)
144 52 58 84 101
60 23 28 54 71
25 11 15 42 56
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON),
regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C

216 190 219 255 -

200 177 204 242 268
180 157 173 208 228
All peripherals
168 139 153 185 204
enabled(2)(3)
144 107 117 144 161
60 48 54 81 98
Supply 25 23 28 54 71 mA
IDD current in
RUN mode 216 92 104 150 -
200 86 97 143 170
180 76 85 119 140
All peripherals
168 67 75 107 126
disabled(3)
144 52 58 84 101
60 23 28 54 71
25 11 15 42 59
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode) or SRAM on AXI (L1-cache disabled),
regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA= 25 °C TA=85 °C TA=105 °C

216 190 209 255 -

200 177 194 241 268
180 160 175 211 232
All peripherals
168 144 156 189 209
enabled(2)(3)
144 115 125 152 170
60 56 62 89 107
Supply 25 27 32 59 79 mA
IDD current in
RUN mode 216 92 103 150 -
200 86 96 243 171
180 79 87 123 144
All peripherals
168 71 79 111 131
disabled(3)
144 60 65 92 110
60 32 36 63 80
25 16 20 46 64
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode), regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA= 25 °C TA=85 °C TA=105 °C

216 176 194 240 -

200 164 181 227 255
180 149 163 198 220
All peripherals
168 133 145 178 198
enabled(2)(3)
144 106 116 143 161
60 54 60 87 105
Supply 25 27 31 58 76 mA
IDD current in
RUN mode 216 77 88 135 -
200 72 82 129 157
180 67 75 110 131
All peripherals
168 60 67 99 120
disabled(3)
144 50 56 83 101
60 29 34 60 78
25 15 19 45 63
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode) on ITCM interface (ART disabled),
regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA= 25 °C TA=85 °C TA=105 °C

216 215 242 281 -

200 200 218 265 293
180 185 200 237 258
All peripherals
168 166 179 213 233
enabled(2)(3)
144 134 144 172 190
60 61 68 95 112
Supply 25 29 34 61 78
IDD current in mA
RUN mode 216 118 129 177 -
200 110 120 168 196
180 104 113 149 170
All peripherals
168 94 102 135 155
disabled(3)
144 79 85 113 130
60 37 42 69 86
25 18 22 48 66
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode) on ITCM interface (ART disabled),
regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA= 25 °C TA=85 °C TA=105 °C

216 191 218 255 -

200 178 195 241 269
180 164 179 214 236
All peripherals
168 147 160 192 212
enabled(2)(3)
144 121 130 157 175
60 60 66 93 111
Supply 25 28 33 59 77
IDD current in mA
RUN mode 216 93 104 150 -
200 87 97 144 171
180 83 92 126 148
All peripherals
168 75 82 114 134
disabled(3)
144 65 71 97 115
60 35 40 66 84
25 16 20 47 64
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

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Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Single bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
Max(1)
Typ Unit
fHCLK
Symbol Parameter Conditions TA= 25 °C TA= 85 °C TA= 105 °C
(MHz)
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD

180 152 1 167 2 200 2 220 2

168 136 1 148 2 179 2 198 2
All
Peripherals 144 105 1 115 2 141 2 158 2
Supply Enabled(2)(3)
60 47 1 53 2 79 2 96 2
current in
IDD12/ RUN mode 25 22 1 27 2 53 2 70 2
mA
IDD from V12 180 74 1 83 2 116 2 136 2
and VDD
supply 168 65 1 73 2 104 2 123 2
All
Peripherals 144 50 1 57 2 83 2 100 2
Disabled(3)
60 22 1 27 2 53 2 70 2
25 10 1 14 2 41 2 58 2
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from flash memory (Dual bank mode, ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF
Max(1)
Typ Unit
fHCLK
Symbol Parameter Conditions TA= 25 °C TA= 85 °C TA= 105 °C
(MHz)
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD

180 152 1 167 2 200 2 220 2

168 136 1 148 2 179 2 198 2
All
Peripherals 144 105 1 115 2 141 2 158 2
Supply Enabled(2)(3)
60 47 1 53 2 79 2 96 2
current in
IDD12/ RUN mode 25 22 1 27 2 53 2 70 2
mA
IDD from V12 180 74 1 82 2 114 2 137 2
and VDD
supply 168 65 1 73 2 104 2 123 2
All
Peripherals 144 50 1 57 2 83 2 100 2
Disabled(3)
60 22 1 27 2 53 2 70 2
25 10 1 14 2 41 2 58 2

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1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.

Table 33. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C

216 128 144(3) 190(3) -

200 119 134 180 214
180 105 118(3) 153(3) 178(3)
All
peripherals 168 93 105 136 156
enabled(2)
144 72 80 107 124
60 33 39 65 82
Supply 25 17 21 47 65 mA
IDD current in
Sleep mode 216 18 25(3) 71(3) -
200 17 24 70 112
180 14 20(3) 54(3) 75(3)
All
peripherals 168 13 18 49 69
disabled
144 10 14 40 58
60 6 10 36 53
25 4 8 34 51
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. Guaranteed by test in production.

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Table 34. Typical and maximum current consumption in Sleep mode, regulator OFF
Max(1)
Typ Unit
fHCLK
Symbol Parameter Conditions TA= 25 °C TA= 85 °C TA= 105 °C
(MHz)
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD

180 102 1 114 2 148 2 168 2

168 91 1 101 2 132 2 152 2
All
Peripherals 144 71 1 78 2 105 2 122 2
Supply Enabled(2)
60 32 1 37 2 64 2 81 2
current in
IDD12/ RUN mode 25 16 1 20 2 46 2 64 2
mA
IDD from V12 180 13 1 18 2 53 2 73 2
and VDD
supply 168 12 1 16 2 47 2 67 2
All
Peripherals 144 9 1 13 2 39 2 56 2
Disabled
60 5 1 9 2 35 2 52 2
25 3 1 7 2 33 2 50 2
1. Guaranteed by characterization results, unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.

Table 35. Typical and maximum current consumptions in Stop mode

Max(1)
Typ
Symbol Parameter Conditions VDD = 3.6 V Unit
TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C
Flash memory in Stop mode,
Supply current in Stop all oscillators OFF, no IWDG 0.55 3 18 27
mode, main regulator in
Run mode Flash memory in Deep power
0.5 3 18 27
down mode, all oscillators OFF
IDD_STOP_NM
(normal mode) Flash memory in Stop mode, all
0.42 2.5 15 24
Supply current in Stop oscillators OFF, no IWDG
mode, main regulator in Flash memory in Deep power
Low-power mode down mode, all oscillators OFF, no 0.37 2.5 15 24
IWDG mA

Regulator in Run mode, Flash

memory in Deep power down
0.18 1.2 6 10
Supply current in Stop mode, all oscillators OFF, no
IDD_STOP_UDM
mode, main regulator in IWDG
(under-drive Low voltage and under-
mode) Regulator in Low-power mode,
drive modes Flash memory in Deep power
0.13 1.1 6 10
down mode, all oscillators OFF, no
IWDG
1. Data based on characterization, tested in production.

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Table 36. Typical and maximum current consumptions in Standby mode

Typ(1) Max(2)

TA = TA = TA =
TA = 25 °C
Symbol Parameter Conditions 25 °C 85 °C 105 °C Unit

VDD = VDD= VDD =

VDD = 3.3 V
1.7 V 2.4 V 3.3 V

Backup SRAM OFF, RTC and

1.1 1.9 2.4 5(3) 18(3) 38(3)
LSE OFF
Backup SRAM ON, RTC and
1.9 2.7 3.2 6(3) 23(3) 48(3)
LSE OFF
Backup SRAM OFF, RTC ON
1.7 2.7 3.5 7 26 55
and LSE in low drive mode
Backup SRAM OFF, RTC ON
and LSE in medium low drive 1.7 2.7 3.5 7 26 56
mode
Backup SRAM OFF, RTC ON
and LSE in medium high drive 1.8 2.8 3.6 8 28 57
Supply current mode
IDD_STBY in Standby µA
mode Backup SRAM OFF, RTC ON
1.9 2.9 3.7 8 28 59
and LSE in high drive mode
Backup SRAM ON, RTC ON
2.4 3.4 4.3 8 31 65
and LSE in low drive mode
Backup SRAM ON, RTC ON
and LSE in Medium low drive 2.4 3.5 4.3 8 31 65
mode
Backup SRAM ON, RTC ON
and LSE in Medium high drive 2.6 3.7 4.5 8 33 68
mode
Backup SRAM ON, RTC ON
2.6 3.7 4.5 9 33 68
and LSE in High drive mode
1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset
OFF), the typical current consumption is reduced by additional 1.2 µA.
2. Guaranteed by characterization results, unless otherwise specified.
3. Guaranteed by test in production.

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Table 37. Typical and maximum current consumptions in VBAT mode

Typ Max(2)

TA =25 °C TA =85 °C TA =105 °C

Symbol Parameter Conditions(1) Unit
VBAT = VBAT= VBAT=
VBAT = 3.6 V
1.7 V 2.4 V 3.3 V
Backup SRAM OFF, RTC and
0.03 0.04 0.04 0.2 0.4
LSE OFF
Backup SRAM ON, RTC and
0.77 0.78 0.83 3.2 7.4
LSE OFF
Backup SRAM OFF, RTC ON
0.62 0.8 1.13 4.4 10.2
and LSE in low drive mode
Backup SRAM OFF, RTC ON
and LSE in medium low drive 0.65 0.83 1.17 4.6 10.6
mode
Backup SRAM OFF, RTC ON
Supply current and LSE in medium high drive 0.75 0.94 1.28 5.0 11.4
IDD_VBAT µA
in VBAT mode mode
Backup SRAM OFF, RTC ON
0.9 1.08 1.43 5.5 12.8
and LSE in high drive mode
Backup SRAM ON, RTC ON and
1.35 1.54 1.91 7.3 17.2
LSE in low drive mode
Backup SRAM ON, RTC ON and
1.38 1.57 1.93 7.9 18.4
LSE in Medium low drive mode
Backup SRAM ON, RTC ON and
1.53 1.73 2.11 8.0 18.7
LSE in Medium high drive mode
Backup SRAM ON, RTC ON and
1.67 1.87 2.26 9.0 21.0
LSE in High drive mode
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull resistors generate current consumption when the pin is
externally held to the opposite level. The value of this current consumption can be simply
computed by using the pull-up/pull-down resistors values given in Table 66: I/O static
characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring

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these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 39: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:

I SW = V DD × f SW × C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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Table 38. Switching output I/O current consumption(1)

I/O toggling
Typ Typ
Symbol Parameter Conditions frequency (fsw) Unit
VDD = 3.3 V VDD = 1.8 V
MHz

2 0.1 0.1
8 0.4 0.2
25 1.1 0.7

CEXT = 0 pF 50 2.4 1.3

C = CINT + CS + CEXT 60 3.1 1.6
84 4.3 2.4
90 4.9 2.6

I/O switching 100 5.4 2.8

IDDIO mA
Current 2 0.2 0.1
8 0.6 0.3
25 1.8 1.1
CEXT = 10 pF 50 3.1 2.3
C = CINT + CS + CEXT
60 4.6 3.4
84 9.7 3.6
90 10.12 5.2
100 14.92 5.4
2 0.3 0.1
8 1.0 0.5
25 3.5 1.6
CEXT = 22 pF
50 5.9 4.2
C = CINT + CS + CEXT
60 10.0 4.4

I/O switching 84 19.12 5.8

IDDIO mA
Current 90 19.6 -
2 0.3 0.2
8 1.3 0.7
CEXT = 33 pF
25 3.5 2.3
C = CINT + CS + CEXT
50 10.26 5.19
60 16.53 -
1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF.

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On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled.
• The ART/L1-cache is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
• Ambient operating temperature is 25 °C and VDD=3.3 V.

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Table 39. Peripheral current consumption

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

GPIOA 2.9 2.8 2.2

GPIOB 3.0 2.9 2.2
GPIOC 2.9 2.8 2.2
GPIOD 3.1 3.0 2.3
GPIOE 3.1 3.0 2.3
GPIOF 2.9 2.8 2.2
GPIOG 2.9 2.8 2.2
GPIOH 3.1 3.1 2.4
GPIOI 3.0 2.9 2.2
GPIOJ 2.9 2.9 2.2
AHB1
(up to GPIOK 2.8 2.8 2.4 µA/MHz
216 MHz) CRC 1.0 0.9 0.8
BKPSRAM 0.9 0.9 0.7
DMA1 3.17 x N + 11.63 3.08 x N + 11.39 2.6 x N + 9.64
DMA2 3.33 x N + 12.84 3.27 x N + 11.84 2.75 x N + 10.10
DMA2D 77.7 76.3 63.5
ETH_MAC
ETH_MAC_TX
40.1 39.5 32.8
ETH_MAC_RX
ETH_MAC_PTP
OTG_HS 58.5 57.4 48.1
OTG_HS+ULPI 58.5 57.4 48.1
DCMI 2.9 2.8 2.1
JPEG 74.8 73.4 61.9
AHB2
(up to CRYP 1.9 1.7 1.4
µA/MHz
216 MHz) HASH 4.5 4.4 3.6
RNG 6.7 6.7 5.4
USB_OTG_FS 32.4 31.9 26.7

AHB3 FMC 18.6 18.2 15.1

(up to µA/MHz
216 MHz) QSPI 22.3 21.8 18.1

Bus matrix(2) 3.94 3.25 2.12 µA/MHz

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Table 39. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

TIM2 19.1 18.7 14.7

TIM3 14.6 14.0 10.6
TIM4 15.4 14.7 11.4
TIM5 18.1 17.6 13.6
TIM6 3.1 2.7 1.4
TIM7 3.0 2.7 1.1
TIM12 8.1 7.8 5.6
TIM13 5.4 5.1 3.1
TIM14 5.6 5.3 3.3
LPTIM1 9.8 9.6 6.9
WWDG 1.9 1.6 1,4
(3)
SPI2/I2S2 3.0 2.9 1.4
SPI3/I2S3(3) 3.0 3.3 1.4
SPDIFRX 2.4 2.0 1.7
APB1 USART2 12.6 12.7 9.2
(up to µA/MHz
54 MHz) USART3 12.4 12.4 9.4
UART4 10.7 10.9 8.1
UART5 10.7 10.7 8.1
I2C1 8.9 8.9 6.4
I2C2 8.3 8.2 6.1
I2C3 8.1 8.2 6.1
I2C4 8.0 8.2 5.8
CAN1 6.3 6.4 4.4
CAN2 5.7 5.8 3.9
CAN3 7.4 7.1 5.6
HDMI-CEC 2.2 1.8 1.4
PWR 1.3 0.9 0.8
(4)
DAC 4.8 4.2 3.6
UART7 10.4 10.4 7.8
UART8 11.1 11.3 8.3

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Table 39. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3

TIM1 24.1 23.8 19.6

TIM8 24.5 24.2 20.0
USART1 17.7 17.4 14.3
USART6 11.9 11.8 9.4
ADC1(5) 4.5 4.7 3.5
(5)
ADC2 4.5 4.7 3.3
(5)
ADC3 4.5 4.6 3.3
SDMMC1 8.4 8.3 6.9
SDMMC2 8.2 8.2 6.4
(3)
SPI1/I2S1 3.9 3.6 3.1
SPI4 3.9 3.6 3.1
APB2
(up to SYSCFG 2.5 2.2 1.9 µA/MHz
108 MHz)
TIM9 8.0 8.0 6.2
TIM10 5.0 5.1 3.7
TIM11 6.9 6.9 5.3
SPI5 2.7 2.8 1.8
SPI6 3.1 3.2 2.2
SAI1 3.2 3.3 2.2
DFSDM1 10.9 10.7 9.0
SAI2 3.9 3.9 2.8
MDIO 7.1 7.0 5.8
LTDC 51.2 50.3 41.8
DSI 8.5 8.4 8.1
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.75 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.73 mA per ADC for the analog part.

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6.3.8 Wakeup time from low-power modes

The wakeup times given in Table 40 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Table 40. Low-power mode wakeup timings

Symbol Parameter Conditions Typ(1) Max(1) Unit

CPU
tWUSLEEP(2) Wakeup from Sleep - 13 13 clock
cycles
Main regulator is ON 14 14.9

Main regulator is ON and Flash

104.1 107.6
memory in Deep power down mode
Wakeup from Stop mode
tWUSTOP(2) with MR/LP regulator in
normal mode Low power regulator is ON 21.4 24.2

Low power regulator is ON and Flash

111.5 116.5
memory in Deep power down mode
µs
Main regulator in under-drive mode
(Flash memory in Deep power-down 107.4 113.2
Wakeup from Stop mode mode)
tWUSTOP(2) with MR/LP regulator in Low power regulator in under-drive
Under-drive mode mode
112.7 120
(Flash memory in Deep power-down
mode )

tWUSTDBY Wakeup from Standby Exit Standby mode on rising edge 308 313
(2)
mode Exit Standby mode on falling edge 307 313
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first

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6.3.9 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 66: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 28.
The characteristics given in Table 41 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.

Table 41. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

External user clock source

fHSE_ext 1 - 50 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
-
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 10
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - - 5 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
IL OSC_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
1. Guaranteed by design.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 66: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 29.
The characteristics given in Table 42 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.

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Table 42. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3VDD
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - - 5 - pF
DuCy(LSE) Duty cycle - 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
1. Guaranteed by design.

Figure 28. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32F

ai17528

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Figure 29. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32F

ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 43. HSE 4-26 MHz oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 26 MHz

RF Feedback resistor - - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 450 -
CL=5 pF@25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 530 -
CL=10 pF@25 MHz
ACCHSE(2) HSE accuracy - − 500 - 500 ppm
Gm_crit_max Maximum critical crystal gm Startup - - 1 mA/V
tSU(HSE(3) Startup time VDD is stabilized - 2 - ms
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is guaranteed by characterization results. It is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.

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Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for STM8AF/AL/S, STM32 MCUs and MPUs” available from the ST website
www.st.com.

Figure 30. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32F

CL2
ai17530

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 44. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0]=00
- 250 -
Low drive capability
LSEDRV[1:0]=10
- 300 -
Medium low drive capability
IDD LSE current consumption nA
LSEDRV[1:0]=01
- 370 -
Medium high drive capability
LSEDRV[1:0]=11
- 480 -
High drive capability
LSEDRV[1:0]=00
- - 0.48
Low drive capability
LSEDRV[1:0]=10
- - 0.75
Medium low drive capability
Gm_crit_max Maximum critical crystal gm µA/V
LSEDRV[1:0]=01
- - 1.7
Medium high drive capability
LSEDRV[1:0]=11
- - 2.7
High drive capability
tSU(2) start-up time VDD is stabilized - 2 - s
1. Guaranteed by design.

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2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled
(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for STM8AF/AL/S, STM32 MCUs and MPUs” available from the ST website
www.st.com.

Figure 31. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors
C L1
OSC32_ IN f LSE

Bias
32.768 kHz RF controlled
resonator
gain
OSC32_ OU T STM32F
C L2
ai17531a

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6.3.10 Internal clock source characteristics

The parameters given in Table 45 and Table 46 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.

High-speed internal (HSI) RC oscillator

Table 45. HSI oscillator characteristics (1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 16 - MHz

HSI user trimming step(2) - - - 1 %
(3)
TA = –40 to 105 °C −8 - 4.5 %
ACCHSI
Accuracy of the HSI oscillator TA = –10 to 85 °C(3) −4 - 4 %
TA = 25 °C(4) −1 - 1 %
tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 µs
IDD(HSI) (2) HSI oscillator power consumption - - 60 80 µA
1. VDD = 3.3 V, PLL OFF, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.

Figure 32. ACCHSI versus temperature

2
ACCHSI(%)

0
-40 0 25 55 85 105 125
TA ( °C)
-2

-4

Min Max Typical

-6

-8

MSv41055V1

1. Guaranteed by characterization results.

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Low-speed internal (LSI) RC oscillator

Table 46. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit

fLSI(2) Frequency 17 32 47 kHz

(3)
tsu(LSI) LSI oscillator startup time - 15 40 µs
IDD(LSI) (3) LSI oscillator power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.

Figure 33. LSI deviation versus temperature

8.0%

6.0%

4.0%
Normalized deviation (%)

2.0%

Min
0.0% Max
-40°C 0°C 25°C 85°C 105°C 125°C
Typical

-2.0%

-4.0%

-6.0%

-8.0%
Temperature (°C)
MS37554V1

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6.3.11 PLL characteristics

The parameters given in Table 47 and Table 48 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.

Table 47. Main PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

fPLL_OUT PLL multiplier output clock - 24 - 216
48 MHz PLL multiplier output MHz
fPLL48_OUT - - 48 75
clock
fVCO_OUT PLL VCO output - 100 - 432
VCO freq = 192 MHz 75 - 200
tLOCK PLL lock time µs
VCO freq = 432 MHz 100 - 300
RMS - 25 -

Cycle-to-cycle jitter peak

to - ±150 -
System clock peak
216 MHz RMS - 15 -

Period Jitter peak

to - ±200 -
Jitter(3) ps
peak
Main clock output (MCO) for Cycle to cycle at 50 MHz
- 32 -
RMII Ethernet on 1000 samples
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
- 40 -
Ethernet on 1000 samples
Cycle to cycle at 1 MHz
Bit Time CAN jitter - 330 -
on 1000 samples
VCO freq = 192 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD - mA
VCO freq = 432 MHz 0.45 0.75
VCO freq = 192 MHz 0.30 0.40
IDDA(PLL)(4) PLL power consumption on VDDA - mA
VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.

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Table 48. PLLI2S characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10

PLLI2S multiplier output clock for
fPLLI2SP_OUT - - - 216
SPDIFRX
PLLI2S multiplier output clock for
fPLLI2SQ_OUT - - - 216 MHz
SAI
PLLI2S multiplier output clock for
fPLLI2SR_OUT - - - 216
I2S
fVCO_OUT PLLI2S VCO output - 100 - 432
VCO freq = 192 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO freq = 432 MHz 100 - 300

Cycle to cycle at RMS - 90 - -

12.288 MHz on peak
48KHz period, to - ±280 - ps
N=432, R=5 peak
Master I2S clock jitter
(3) Average frequency of
Jitter
12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
WS I2S clock jitter - 400 - ps
on 1000 samples
PLLI2S power consumption on VCO freq = 192 MHz 0.15 0.40
IDD(PLLI2S)(4) - mA
VDD VCO freq = 432 MHz 0.45 0.75

PLLI2S power consumption on VCO freq = 192 MHz 0.30 0.40

IDDA(PLLI2S)(4) - mA
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.

Table 49. PLLISAI characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLLSAI_IN PLLSAI input clock(1) - 0.95(2) 1 2.10

PLLSAI multiplier output clock
fPLLSAIP_OUT - - 48 75
for 48 MHz
PLLSAI multiplier output clock
fPLLSAIQ_OUT - - - 216 MHz
for SAI
PLLSAI multiplier output clock
fPLLSAIR_OUT - - - 216
for LCD-TFT
fVCO_OUT PLLSAI VCO output - 100 - 432

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Table 49. PLLISAI characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VCO freq = 192 MHz 75 - 200

tLOCK PLLSAI lock time µs
VCO freq = 432 MHz 100 - 300

Cycle to cycle at RMS - 90 - -

12.288 MHz on peak
48KHz period, to - ±280 - ps
N=432, R=5 peak
Master SAI clock jitter
(3) Average frequency of
Jitter
12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
FS clock jitter - 400 - ps
on 1000 samples
PLLSAI power consumption on VCO freq = 192 MHz 0.15 0.40
IDD(PLLSAI)(4) - mA
VDD VCO freq = 432 MHz 0.45 0.75

PLLSAI power consumption on VCO freq = 192 MHz 0.30 0.40

IDDA(PLLSAI)(4) - mA
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 62: EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz
(Setting 2)). It is available only on the main PLL.

Table 50. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit

fMod Modulation frequency - - 10 KHz

md Peak modulation depth 0.25 - 2 %
15 −1
MODEPER * INCSTEP - - - 2 -
1. Guaranteed by design.

Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]

fPLL_IN and fMod must be expressed in Hz.

As an example:

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If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250

Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )

As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.002%(peak)

Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.

Figure 34. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT)

md
F0
md

Time
tmode 2xtmode
ai17291

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Figure 35. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)

F0
2xmd

Time
tmode 2xtmode
ai17292b

6.3.13 MIPI D-PHY characteristics

The parameters given in Table 51 and Table 52 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.

Table 51. MIPI D-PHY characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Hi-Speed Input/Output Characteristics

UINST UI instantaneous - 2 - 12.5 ns
HS transmit common mode
VCMTX - 150 200 250
voltage
VCMTX mismatch when output
|∆VCMTX| - - - 5
is Differential-1 or Differential-0
mV
|VOD| HS transmit differential voltage - 140 200 270
VOD mismatch when output is
|∆VOD| - - - 14
Differential-1 or Differential-0
VOHHS HS output high voltage - - - 360
Single ended output
ZOS - 40 50 62.5 Ω
impedance
Single ended output
∆ZOS - - - 10 %
impedance mismatch
tHSr & tHSf 20%-80% rise and fall time - 100 - 0.35*UI ps
LP Receiver Input Characteristics
Logic 0 input voltage (not in
VIL - - - 550
ULP State)
Logic 0 input voltage in ULP
VIL-ULPS - - - 300 mV
State
VIH Input high level voltage - 880 - -
Vhys Voltage hysteresis - 25 - -
LP Emitter Output Characteristics

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Table 51. MIPI D-PHY characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

VIL Output low level voltage - 1.1 1.2 1.2 V

VIL-ULPS Output high level voltage - -50 - 50 mV
Output impedance of LP
VIH - 110 - - Ω
transmitter
Vhys 15%-85% rise and fall time - - - 25 ns
LP Contention Detector Characteristics
VILCD Logic 0 contention threshold - - - 200
mV
VIHCD Logic 0 contention threshold - 450 - -
1. Guaranteed based on test during characterization.

Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP

transitions(1)
Symbol Parameter Conditions Min Typ Max Unit

Transmitted length of any Low-

TLPX - 50 - -
Power state period
Time that the transmitter drives
the Clock Lane LP-00 Line
TCLK-PREPARE state immediately before the - 38 - 95
ns
HS-0 Line state starting the HS
transmission.
TCLK-PREPARE Time that the transmitter drives
+ the HS-0 state prior to starting - 300 - -
TCLK-ZERO the clock.
Time that the HS clock shall be
driven by the transmitter prior to
TCLK-PRE any associated Data Lane - 8 - - UI
beginning the transition from
LP to HS mode.

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Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP

transitions(1) (continued)
Symbol Parameter Conditions Min Typ Max Unit

Time that the transmitter

continues to send HS clock
TCLK-POST after the last associated Data - 62+52*UI - -
Lane has transitioned to LP
Mode.
Time that the transmitter drives
the HS-0 state after the last
TCLK-TRAIL - 60 - -
payload clock bit of an HS
transmission burst.
Time that the transmitter drives
the Data Lane LP-00 Line state
THS-PREPARE immediately before the HS-0 - 40+4*UI - 85+6*UI
Line state starting the HS
transmission.
THS-PREPARE+ Time that the
THS-PREPARE ns
transmitter drives the HS-0
+ - 145+10*UI - -
state prior to transmitting the
THS-ZERO
Sync sequence.
Time that the transmitter drives
Max
the flipped differential state
THS-TRAIL - (n*8*UI, - -
after last payload data bit of a
60+n*4*UI)
HS transmission burst.
Time that the transmitter drives
THS-EXIT - 100 - -
LP-11 following a HS burst.
TREOT 30%-85% rise time and fall time - - - 35
Transmitted time interval from
the start of THS-TRAIL or
105+
TEOT TCLK-TRAIL, to the start of the - - -
n*12UI
LP-11 state following a HS
burst.
1. Guaranteed based on test during characterization.

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Figure 36. MIPI D-PHY HS/LP clock lane transition timing diagram

TCLK-POST TEOT

Clock VIL
Lane

TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE TLPX THS-PREPARE

Data VIL
Lane

MS38282V1

Figure 37. MIPI D-PHY HS/LP data lane transition timing diagram

Clock
Lane
TLPX THS-PREPARE THS-ZERO

Data
VIL
Lane
TREOT
LP-11 LP-01 LP-00 TEOT

THS-TRAIL THS-EXIT

MS38283V1

6.3.14 MIPI D-PHY PLL characteristics

The parameters given in Table 53 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.

Table 53. DSI-PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock - 4 - 100

fPLL_INFIN PFD input clock - 4 - 25
MHz
fPLL_OUT PLL multiplier output clock - 31.25 - 500
fVCO_OUT PLL VCO output - 500 - 1000
tLOCK PLL lock time - - - 200 µs

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Table 53. DSI-PLL characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

fVCO_OUT = 500 MHz - 0.55 0.70

IDD(PLL) PLL power consumption on VDD12 fVCO_OUT = 600 MHz - 0.65 0.80 mA
fVCO_OUT = 1000 MHz - 0.95 1.20
1. Based on test during characterization.

6.3.15 MIPI D-PHY regulator characteristics

The parameters given in Table 54 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.

Table 54. DSI regulator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD12DSI 1.2 V internal voltage on VDD12DSI - 1.15 1.20 1.30 V

CEXT External capacitor on VCAPDSI - 1.1 2.2 3.3 μF
ESR External Serial Resistor - 0 25 600 mΩ
IDDDSIREG Regulator power consumption - 100 120 125 µA
Ultra Low Power Mode
- 290 600
DSI system (regulator, PLL and (Reg. ON + PLL OFF)
IDDDSI µA
D-PHY) current consumption on VDDDSI Stop State
- 290 600
(Reg. ON + PLL OFF)
10 MHz escape clock
- 4.3 5.0
DSI system current consumption on (Reg. ON + PLL OFF)
IDDDSILP mA
VDDDSI in LP mode communication(2) 20 MHz escape clock
- 4.3 5.0
(Reg. ON + PLL OFF)
300 Mbps - 1 data lane
- 8.0 8.8
(Reg. ON + PLL ON)
300 Mbps - 2data lane
DSI system (regulator, PLL and - 11.4 12.5
(Reg. ON + PLL ON)
D-PHY) current consumption on VDDDSI
in HS mode communication(3) 500 Mbps - 1 data lane
- 13.5 14.7
IDDDSIHS (Reg. ON + PLL ON) mA
500 Mbps - 2data lane
- 18.0 19.6
(Reg. ON + PLL ON)
DSI system (regulator, PLL and
500 Mbps - 2data lane
D-PHY) current consumption on VDDDSI - 21.4 23.3
(Reg. ON + PLL ON)
in HS mode with CLK like payload
CEXT = 2.2 µF - 110 -
tWAKEUP Startup delay µs
CEXT = 3.3 µF - - 160
IINRUSH Inrush current on VDDDSI External capacitor load at start - 60 200 mA
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

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6.3.16 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.

Table 55. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max Unit

Write / Erase 8-bit mode, VDD = 1.7 V - 14 -

IDD Supply current Write / Erase 16-bit mode, VDD = 2.1 V - 17 - mA
Write / Erase 32-bit mode, VDD = 3.3 V - 24 -

Table 56. Flash memory programming (single bank configuration

nDBANK=1)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
Program/erase
- 400 800
parallelism (PSIZE) = x 8
Program/erase
tERASE32KB Sector (32 KB) erase time - 250 600 ms
parallelism (PSIZE) = x 16
Program/erase
- 200 500
parallelism (PSIZE) = x 32
Program/erase
- 1100 2400
parallelism (PSIZE) = x 8
Program/erase
tERASE128KB Sector (128 KB) erase time - 800 1400 ms
parallelism (PSIZE) = x 16
Program/erase
- 500 1100
parallelism (PSIZE) = x 32
Program/erase
- 2.1 4
parallelism (PSIZE) = x 8
Program/erase
tERASE256KB Sector (256 KB) erase time - 1.5 2.6 s
parallelism (PSIZE) = x 16
Program/erase
- 1 2
parallelism (PSIZE) = x 32
Program/erase
- 16 32
parallelism (PSIZE) = x 8
Program/erase
tME Mass erase time - 11 22 s
parallelism (PSIZE) = x 16
Program/erase
- 8 16
parallelism (PSIZE) = x 32

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Table 56. Flash memory programming (single bank configuration

nDBANK=1) (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit

32-bit program operation 2.7 - 3 V

Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.

Table 57. Flash memory programming (dual bank configuration

nDBANK=0)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
Program/erase
- 400 800
parallelism (PSIZE) = x 8
Program/erase
tERASE16KB Sector (16 KB) erase time - 250 600 ms
parallelism (PSIZE) = x 16
Program/erase
- 200 500
parallelism (PSIZE) = x 32
Program/erase
- 1100 2400
parallelism (PSIZE) = x 8
Program/erase
tERASE64KB Sector (64 KB) erase time - 800 1400 ms
parallelism (PSIZE) = x 16
Program/erase
- 500 1100
parallelism (PSIZE) = x 32
Program/erase
- 2.1 4
parallelism (PSIZE) = x 8
Program/erase
tERASE128KB Sector (128 KB) erase time - 1.5 2.6 s
parallelism (PSIZE) = x 16
Program/erase
- 1 2
parallelism (PSIZE) = x 32
Program/erase
- 16 32
parallelism (PSIZE) = x 8
Program/erase
tME Mass erase time - 11 22 s
parallelism (PSIZE) = x 16
Program/erase
- 8 16
parallelism (PSIZE) = x 32

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Table 57. Flash memory programming (dual bank configuration

nDBANK=0) (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase
- 16 32
parallelism (PSIZE) = x 8
Program/erase
tBE Bank erase time - 11 22 s
parallelism (PSIZE) = x 16
Program/erase
- 8 16
parallelism (PSIZE) = x 32
32-bit program operation 2.7 - 3 V
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.

Table 58. Flash memory programming with VPP

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

tprog Double word programming - 16 100(2) µs

tERASE32KB Sector (32 KB) erase time TA = 0 to +40 °C - 180 -
tERASE128KB Sector (128 KB) erase time VDD = 3.3 V - 450 - ms
tERASE256KB Sector (256 KB) erase time VPP = 8.5 V - 900 -
tME Mass erase time - 6.9 - s
Vprog Programming voltage - 2.7 - 3.6 V
VPP VPP voltage range - 7 - 9 V
Minimum current sunk on
IPP - 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - - 1 hour
which VPP is applied
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.

Table 59. Flash memory endurance and data retention

Value
Symbol Parameter Conditions Unit
Min(1)

TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
tRET Data retention 1 kcycle(2) at TA = 105 °C 10 Years
10 kcycles(2) at TA = 55 °C 20

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1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

6.3.17 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 60. They are based on the EMS levels and classes
defined in application note AN1709.

Table 60. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, TA = +25 °C, fHCLK =

Voltage limits to be applied on any I/O pin to
VFESD 216 MHz, conforms to IEC 61000- 2B
induce a functional disturbance
4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA =+25 °C, fHCLK =
VFTB applied through 100 pF on VDD and VSS 168 MHz, conforms to IEC 61000- 5A
pins to induce a functional disturbance 4-2

As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.

Table 61. EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 1)
Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/200 MHz

0.1 to 30 MHz 5
30 to 130 MHz 10
Peak (1) VDD = 3.6 V, TA = 25 °C, TFBGA216 package, dBµV
conforming to IEC61967-2 ART/L1-cache ON, 130 MHz to 1 GHz 18
SEMI
over-drive ON, all peripheral clocks enabled,
1 GHz to 2 GHz 10
clock dithering disabled.
0.1 to 2 GHz
Level(2) 3.5 -

1. Refer to the “EMI radiated test” in AN1709.

2. Refer to the “EMI level classification” in AN1709.

Table 62. EMI characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 2)
Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/200 MHz

0.1 to 30 MHz 2
VDD = 3.6 V, TA = 25 °C, TFBGA216 package,
30 to 130 MHz 9
Peak (1) conforming to IEC61967-2 ART/L1-cache ON, dBµV
SEMI
over-drive ON, all peripheral clocks enabled, 130 MHz to 1 GHz 14
clock dithering enabled.
1 GHz to 2 GHz 9

Level(2) 0.1 to 2 GHz 3 -

1. Refer to the “EMI radiated test” in AN1709.

2. Refer to the “EMI level classification” in AN1709.

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6.3.18 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.

Table 63. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge
TA = +25 °C conforming to ANSI/ESDA/JEDEC
VESD(HBM) voltage (human body 2 2000
JS-001-2012
model)
TA = +25 °C conforming to ANSI/ESD S5.3.1- V
Electrostatic discharge 3 250
2009, all packages except TFBGA100
VESD(CDM) voltage (charge device
model) TA = +25 °C conforming to ANSI/ESD S5.3.1-
4 500
2009, TFBGA100 package
1. Guaranteed by characterization results.

Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.

Table 64. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II level A

6.3.19 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during the normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when an abnormal injection accidentally happens, susceptibility tests are performed
on a sample basis during the device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.

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The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
A negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 65.

Table 65. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0, DSI_D0P, DSI_D0N, DSI_D1P,

−0 0
DSI_D1N, DSI_CKP, DSI_CKN pin
Injected current on NRST pin −0 NA(1)
IINJ mA
Injected current on PC0, PC2, PH1_OSCOUT pins −0 NA(1)
Injected current on any other FT pin −5 NA(1)
Injected current on any other pins −5 +5
1. Injection is not possible.

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.

6.3.20 I/O port characteristics

For information on GPIO configuration, refer to the application note STM32 GPIO
configuration for hardware settings and low-power consumption (AN4899), available from
the ST website www.st.com.

General input/output characteristics

Unless otherwise specified, the parameters given in Table 66: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 17. All I/Os are
CMOS and TTL compliant.

Table 66. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

FT, TTa and NRST I/O input 0.35VDD − 0.04(1)

1.7 V≤VDD≤3.6 V - -
low level voltage 0.3VDD(2)

VIL 1.75 V≤VDD ≤3.6 V, – V

- -
BOOT I/O input low level 40 °C≤TA ≤105 °C
0.1VDD+0.1(1)
voltage 1.7 V≤VDD ≤3.6 V,
- -
0 °C≤TA ≤105 °C

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Table 66. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

0.45VDD+0.3 (1)
FT, TTa and NRST I/O input
1.7 V≤VDD≤3.6 V - -
high level voltage(5) 0.7VDD(2)

VIH 1.75 V≤VDD ≤3.6 V, – V

BOOT I/O input high level 40 °C≤TA ≤105 °C
0.17VDD+0.7(1) - -
voltage 1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
FT, TTa and NRST I/O input
1.7 V≤VDD≤3.6 V 10%VDD(3) - -
hysteresis
1.75 V≤VDD ≤3.6 V, –
VHYS V
40 °C≤TA ≤105 °C
BOOT I/O input hysteresis 0.1 - -
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
I/O input leakage current (4) VSS ≤VIN ≤VDD - - ±1
Ilkg I/O FT input leakage current µA
(5) VIN = 5 V - - 3

All pins
except for
PA10/PB12
30 40 50
(OTG_FS_I
Weak pull-up D,OTG_HS_
RPU equivalent ID) VIN = VSS
resistor(6)
PA10/PB12
(OTG_FS_I
7 10 14
D,OTG_HS_
ID)
kΩ
All pins
except for
PA10/PB12
30 40 50
Weak pull- (OTG_FS_I
down D,OTG_HS_
RPD ID) VIN = VDD
equivalent
resistor(7) PA10/PB12
(OTG_FS_I
7 10 14
D,OTG_HS_
ID)
CIO(8) I/O pin capacitance - - 5 - pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 65: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 65: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).

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Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 38.

Figure 38. FT I/O input characteristics

VIL/VIH (V)

2.52
DD
7V
0.
=
in
I Hm
tV
en
m
u ire TTL requirement
req VIHmin = 2V
2.0 OS
M .3
1.92 -C +0
on V DD
i .45
ct 0
1.7 odu in=
pr VIH
m
in ,
d ns
st
e
la tio
Te simu
s ign
1.22 De
on
1.19 sed Area not determined
-0.0
4
Ba VDD
.35
1.065 a x= 0
VILm
lati ons,
n simu
0.8 esig
ed on D
Bas TTL requirement
0.55 VILmax = 0.8V
0.51
Tested in production - CMOS requirement VILmax = 0.3VDD

VDD (V)
1.7 2.0 2.4 2.7 3.3 3.6
MS33746V2

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

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In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
∑IVDD (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
∑IVSS (see Table 15).

Output voltage levels

Unless otherwise specified, the parameters given in Table 67 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.

Table 67. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit
(2)
CMOS port
VOL(1) Output low level voltage for an I/O pin IIO = +8 mA - 0.4
2.7 V ≤VDD ≤3.6 V

CMOS port(2)
Output high level voltage for an I/O pin
VOH(3) IIO = -8 mA VDD − 0.4 - V
except PC14
2.7 V ≤VDD ≤3.6 V

CMOS port(2)
VOH(3) Output high level voltage for PC14 IIO = -2 mA VDD − 0.4 -
2.7 V ≤VDD ≤3.6 V
TTL port(2)
VOL (1) Output low level voltage for an I/O pin IIO =+8mA - 0.4
2.7 V ≤VDD ≤3.6 V
V
TTL port(2)
Output high level voltage for an I/O pin
VOH (3) IIO =-8mA 2.4 -
except PC14
2.7 V ≤VDD ≤3.6 V
IIO = +20 mA
VOL(1) Output low level voltage for an I/O pin - 1.3(4)
2.7 V ≤VDD ≤3.6 V
V
Output high level voltage for an I/O pin IIO = -20 mA
VOH(3) VDD −1.3(4) -
except PC14 2.7 V ≤VDD ≤3.6 V
IIO = +6 mA
VOL(1) Output low level voltage for an I/O pin - 0.4(4)
1.8 V ≤VDD ≤3.6 V
V
Output high level voltage for an I/O pin IIO = -6 mA
VOH(3) VDD −0.4(4) -
except PC14 1.8 V ≤VDD ≤3.6 V

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Table 67. Output voltage characteristics (continued)

Symbol Parameter Conditions Min Max Unit

IIO = +4 mA
VOL(1) Output low level voltage for an I/O pin - 0.4(5)
1.7 V ≤VDD ≤3.6V
Output high level voltage for an I/O pin IIO = -4 mA
VOH(3) VDD −0.4(5) - V
except PC14 1.7 V ≤VDD ≤3.6V
IIO = -1 mA
VOH(3) Output high level voltage for PC14 VDD −0.4(5) -
1.7 V ≤VDD ≤3.6V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
5. Guaranteed by design.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 39 and
Table 68, respectively.
Unless otherwise specified, the parameters given in Table 68 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.

Table 68. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 50 pF, VDD ≥ 2.7 V - - 4

CL = 50 pF, VDD ≥ 1.7 V - - 2
fmax(IO)out Maximum frequency(3) CL = 10 pF, VDD ≥ 2.7 V - - 8 MHz

00 CL = 10 pF, VDD ≥ 1.8 V - - 4

CL = 10 pF, VDD ≥ 1.7 V - - 3
Output high to low level fall
tf(IO)out/ CL = 50 pF, VDD = 1.7 V to
time and output low to high - - 100 ns
tr(IO)out 3.6 V
level rise time

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Table 68. I/O AC characteristics(1)(2) (continued)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 50 pF, VDD≥ 2.7 V - - 25

CL = 50 pF, VDD≥ 1.8 V - - 12.5
CL = 50 pF, VDD≥ 1.7 V - - 10
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.7 V - - 50
CL = 10 pF, VDD≥ 1.8 V - - 20
01
CL = 10 pF, VDD≥ 1.7 V - - 12.5
CL = 50 pF, VDD ≥ 2.7 V - - 10
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 6
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 50 pF, VDD ≥ 1.7 V - - 20
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 10
CL = 40 pF, VDD ≥ 2.7 V - - 50(4)
CL = 10 pF, VDD ≥ 2.7 V - - 100(4)
fmax(IO)out Maximum frequency(3) CL = 40 pF, VDD ≥ 1.7 V - - 25 MHz
CL = 10 pF, VDD ≥ 1.8 V - - 50
10 CL = 10 pF, VDD ≥ 1.7 V - - 42.5
CL = 40 pF, VDD ≥2.7 V - - 6
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 4
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 40 pF, VDD ≥ 1.7 V - - 10
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 6
CL = 30 pF, VDD ≥ 2.7 V - - 100(4)
CL = 30 pF, VDD ≥ 1.8 V - - 50
CL = 30 pF, VDD ≥ 1.7 V - - 42.5
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD≥ 2.7 V - - 180(4)
CL = 10 pF, VDD ≥ 1.8 V - - 100
CL = 10 pF, VDD ≥ 1.7 V - - 72.5
11
CL = 30 pF, VDD ≥ 2.7 V - - 4
CL = 30 pF, VDD ≥1.8 V - - 6
Output high to low level fall CL = 30 pF, VDD ≥1.7 V - - 7
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD ≥ 2.7 V - - 2.5
level rise time
CL = 10 pF, VDD ≥1.8 V - - 3.5
CL = 10 pF, VDD ≥1.7 V - - 4
Pulse width of external signals
- tEXTIpw detected by the EXTI - 10 - - ns
controller

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1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F76xxx and STM32F77xxx reference
manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 39.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.

Figure 39. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

t r(IO)out t f(IO)out

Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.

6.3.21 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 66: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.

Table 69. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

VF(NRST) (2) NRST Input filtered pulse - - - 100 ns
(2)
VNF(NRST) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.

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Figure 40. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32F

ai14132c

1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 66. Otherwise the reset is not taken into account by the device.

6.3.22 TIM timer characteristics

The parameters given in Table 70 are guaranteed by design.
Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 70. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
216 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
100 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 216 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK =
4x PCLKx.

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6.3.23 RTC characteristics

Table 71. RTC characteristics

Symbol Parameter Conditions Min Max

Any read/write operation

- fPCLK1/RTCCLK frequency ratio 4 -
from/to an RTC register

6.3.24 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 72 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 72. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit

VDDA Power supply 1.7(1) - 3.6 V

VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage 1.7(1) - VDDA V
VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz
fADC ADC clock frequency
VDDA = 2.4 to 3.6 V 0.6 30 36 MHz
fADC = 30 MHz,
- - 1764 kHz
fTRIG(2) External trigger frequency 12-bit resolution
- - - 17 1/fADC
0
VAIN Conversion voltage range(3) - (VSSA or VREF- - VREF+ V
tied to ground)
See Equation 1 for
RAIN(2) External input impedance - - 50 kΩ
details
RADC(2)(4) Sampling switch resistance - 1.5 - 6 kΩ
Internal sample and hold
CADC(2) - - 4 7 pF
capacitor

Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(2)
latency - - - 3(5) 1/fADC

Regular trigger conversion fADC = 30 MHz - - 0.067 µs

tlatr(2)
latency - - - 2(5) 1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(2) Sampling time
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs

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Table 72. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

fADC = 30 MHz
0.50 - 16.40 µs
12-bit resolution
fADC = 30 MHz
0.43 - 16.34 µs
10-bit resolution
Total conversion time (including fADC = 30 MHz
tCONV(2) 0.37 - 16.27 µs
sampling time) 8-bit resolution
fADC = 30 MHz
0.30 - 16.20 µs
6-bit resolution
9 to 492 (tS for sampling +n-bit resolution for successive
1/fADC
approximation)
12-bit resolution
- - 2.4 Msps
Single ADC

Sampling rate 12-bit resolution

Interleave Dual ADC - - 4.5 Msps
fS(2) (fADC = 36 MHz, and
mode
tS = 3 ADC cycles)
12-bit resolution
Interleave Triple ADC - - 7.2 Msps
mode
ADC VREF DC current
IVREF+(2) consumption in conversion - - 300 500 µA
mode
ADC VDDA DC current
IVDDA(2) consumption in conversion - - 1.6 1.8 mA
mode
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 72.

Equation 1: RAIN max formula

R AIN
( k – 0.5 )
= ---------------------------------------------------------------
- – R ADC
N+2
f ADC × C ADC × ln ( 2 )

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.

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Table 73. ADC static accuracy at fADC = 18 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±3 ±4

fADC =18 MHz
EO Offset error ±2 ±3
VDDA = 1.7 to 3.6 V
LSB
EG Gain error VREF = 1.7 to 3.6 V ±1 ±3
ED Differential linearity error VDDA −VREF < 1.2 V ±1 ±2
EL Integral linearity error ±2 ±3
1. Guaranteed by characterization results.

Table 74. ADC static accuracy at fADC = 30 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±2 ±5

fADC = 30 MHz,
EO Offset error ±1.5 ±2.5
RAIN < 10 kΩ,
EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±4 LSB
VREF = 1.7 to 3.6 V,
ED Differential linearity error ±1 ±2
VDDA −VREF < 1.2 V
EL Integral linearity error ±1.5 ±3
1. Guaranteed by characterization results.

Table 75. ADC static accuracy at fADC = 36 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±4 ±7

EO Offset error fADC =36 MHz, ±2 ±3

VDDA = 2.4 to 3.6 V,
EG Gain error ±3 ±6 LSB
VREF = 1.7 to 3.6 V
ED Differential linearity error VDDA −VREF < 1.2 V ±2 ±3
EL Integral linearity error ±3 ±6
1. Guaranteed by characterization results.

Table 76. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.3 10.4 - bits

fADC =18 MHz
SINAD Signal-to-noise and distortion ratio VDDA = VREF+= 1.7 V 64 64.2 -
SNR Signal-to-noise ratio Input Frequency = 20 KHz 64 65 - dB
Temperature = 25 °C
THD Total harmonic distortion − 67 − 72 -
1. Guaranteed by characterization results.

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Table 77. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.6 10.8 - bits

fADC =36 MHz
SINAD Signal-to noise and distortion ratio VDDA = VREF+ = 3.3 V 66 67 -
SNR Signal-to noise ratio Input Frequency = 20 KHz 64 68 - dB
Temperature = 25 °C
THD Total harmonic distortion − 70 − 72 -
1. Guaranteed by characterization results.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ∑IINJ(PIN) in
Section 6.3.20 does not affect the ADC accuracy.

Figure 41. ADC accuracy characteristics

V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093

(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1

0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c

1. See also Table 74.

2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.

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Figure 42. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 72 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
3. Refer to Section Table 66.: I/O static characteristics for the value of lIkg,
4. Refer to Section 6.1.6: Power supply scheme.

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General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 43 or Figure 44,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F

VREF+ (1)

1 μF // 10 nF
VDDA

1 μF // 10 nF

(1)
VSSA/VREF-

ai17535b

1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on
UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA.

Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F

VREF+/VDDA (1)

1 μF // 10 nF

(1)
VREF-/VSSA

ai17536c

1. VREF+ input is available on all packages except TFBGA100 whereas the VREF– s available only on
UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA.

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Electrical characteristics STM32F777xx STM32F778Ax STM32F779xx

6.3.25 Temperature sensor characteristics

Table 78. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10 µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs
1. Guaranteed by characterization results.
2. Guaranteed by design.

Table 79. Temperature sensor calibration values

Symbol Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FF0 F44C - 0x1FF0 F44D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 F44E - 0x1FF0 F44F

6.3.26 VBAT monitoring characteristics

Table 80. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 4 - -
Er(1) Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1 mV accuracy
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.27 Reference voltage

The parameters given in Table 81 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

Table 81. internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
ADC sampling time when reading the
TS_vrefint(1) - 10 - - µs
internal reference voltage
Internal reference voltage spread over the
VREFINT_s(2) VDD = 3V ± 10mV - 3 5 mV
temperature range

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Table 81. internal reference voltage (continued)

Symbol Parameter Conditions Min Typ Max Unit

TCoeff(2) Temperature coefficient - - 30 50 ppm/°C

tSTART(2) Startup time - - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.

Table 82. Internal reference voltage calibration values

Symbol Parameter Memory address

VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FF0 F44A - 0x1FF0 F44B

6.3.28 DAC electrical characteristics

Table 83. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments

VDDA Analog supply voltage 1.7(1) - 3.6 V -

VREF+ Reference supply voltage 1.7(1) - 3.6 V VREF+ ≤VDDA

VSSA Ground 0 - 0 V -
Connected to
5 - -
(2) Resistive load VSSA
RLOAD kΩ -
with buffer ON Connected to
25 - -
VDDA
When the buffer is OFF, the Minimum
Impedance output with buffer
RO(2) - - 15 kΩ resistive load between DAC_OUT and
OFF
VSS to have a 1% accuracy is 1.5 MΩ
Maximum capacitive load at DAC_OUT
CLOAD(2) Capacitive load - - 50 pF
pin (when the buffer is ON).

DAC_OUT Lower DAC_OUT voltage It gives the maximum output excursion of

0.2 - - V the DAC.
min(2) with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
DAC_OUT Higher DAC_OUT voltage VDDA −
- - V (0x1C7) to (0xE38) at VREF+ = 1.7 V
max(2) with buffer ON 0.2
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(2) with buffer OFF It gives the maximum output excursion of
DAC_OUT Higher DAC_OUT voltage VREF+ − the DAC.
- - V
max(2) with buffer OFF 1LSB

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Table 83. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments

With no load, worst code (0x800) at

- 170 240 VREF+ = 3.6 V in terms of DC
DAC DC VREF current consumption on the inputs
IVREF+(4) consumption in quiescent µA
mode (Standby mode) With no load, worst code (0xF1C) at
- 50 75 VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, middle code (0x800) on the
- 280 380 µA
DAC DC VDDA current inputs
IDDA(4) consumption in quiescent With no load, worst code (0xF1C) at
mode(3) - 475 625 µA VREF+ = 3.6 V in terms of DC
consumption on the inputs

Differential non linearity - - ±0.5 LSB Given for the DAC in 10-bit configuration.
DNL(4) Difference between two
consecutive code-1LSB)
- - ±2 LSB Given for the DAC in 12-bit configuration.
Integral non linearity - - ±1 LSB Given for the DAC in 10-bit configuration.
(difference between
measured value at Code i
INL(4)
and the value at Code i on a - - ±4 LSB Given for the DAC in 12-bit configuration.
line drawn between Code 0
and last Code 1023)
- - ±10 mV Given for the DAC in 12-bit configuration
Offset error
(difference between Given for the DAC in 10-bit at VREF+ =
- - ±3 LSB
Offset(4) measured value at Code 3.6 V
(0x800) and the ideal value =
Given for the DAC in 12-bit at VREF+ =
VREF+/2) - - ±12 LSB
3.6 V
Gain
Gain error - - ±0.5 % Given for the DAC in 12-bit configuration
error(4)
Settling time (full scale: for a
10-bit input code transition
(4) between the lowest and the CLOAD ≤ 50 pF,
tSETTLING - 3 6 µs
highest input codes when RLOAD ≥ 5 kΩ
DAC_OUT reaches final
value ±4LSB
Total Harmonic Distortion CLOAD ≤ 50 pF,
THD(4) - - - dB
Buffer ON RLOAD ≥ 5 kΩ

Max frequency for a correct

Update DAC_OUT change when CLOAD ≤ 50 pF,
- - 1 MS/s
rate(2) small variation in the input RLOAD ≥ 5 kΩ
code (from code i to i+1LSB)

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Table 83. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments

Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

tWAKEUP(4) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and highest
DAC Control register) possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF
measurement)
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.

Figure 45. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)
RL

12-bit DAC_OUTx
digital to
analog
converter
CL

ai17157V3

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.

6.3.29 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0410 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:

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Table 84. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min Unit

Standard-mode - 2
Analog filter ON
8
DNF=0
Fast-mode
Analog filter OFF
I2CCLK 9
f(I2CCLK) DNF=1 MHz
frequency
Analog filter ON
16
DNF=0
Fast-mode Plus
Analog filter OFF
16
DNF=1

The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but is still present.
• The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
Tr(SDA/SCL)=0.8473xRpxCload
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 85 for the analog filter
characteristics:

Table 85. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 70(3) ns
are suppressed by the analog filter
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 86 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 86. SPI dynamic characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode
SPI1,4,5,6 54(2)
2.7≤VDD≤3.6
Master mode
SPI1,4,5,6 27
1.71≤VDD≤3.6
Master transmitter mode
SPI1,4,5,6 54
1.71≤VDD≤3.6
Slave receiver mode
fSCK SPI1,4,5,6 54
SPI clock frequency 1.71≤VDD≤3.6 - - MHz
1/tc(SCK)
Slave mode transmitter/full
duplex
50(3)
SPI1,4,5,6
2.7≤VDD≤3.6
Slave mode transmitter/full
duplex
37(3)
SPI1,4,5,6
1.71≤VDD≤3.6
Master & Slave mode
SPI2,3 27
1.71≤VDD≤3.6
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*TPLCK - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*TPLCK - -
ns
tw(SCKH)
SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2
tw(SCKL)

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Table 86. SPI dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

5
tsu(MI) Master mode - -
Data input setup time 10(4)
tsu(SI) Slave mode 4.5 - -
2
th(MI) Master mode - -
Data input hold time 0(4)
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode 7 - 21
ns
tdis(SO) Data output disable time Slave mode 5 - 12
Slave mode 2.7≤VDD≤3.6V - 6.5 10
tv(SO)
Data output valid time Slave mode 1.71≤VDD≤3.6V - 6.5 13.5
tv(MO) Master mode - 2 6
Slave mode
4.5 - -
th(SO) Data output hold time 1.71≤VDD≤3.6V
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz.
3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
4. Only for SPI6.

Figure 46. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

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Figure 47. SPI timing diagram - slave mode and CPHA = 1

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

Figure 48. SPI timing diagram - master mode

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

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I2S interface characteristics

Unless otherwise specified, the parameters given in Table 87 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).

Table 87. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S Main clock output - 256x8K 256xFs(2) MHz

Master data - 64xFs
fCK I2S clock frequency MHz
Slave data - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode - 3
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 5 -
th(WS) WS hold time Slave mode 2 -
tsu(SD_MR) Master receiver 2.5 -
Data input setup time
tsu(SD_SR) Slave receiver 2.5 -
ns
th(SD_MR) Master receiver 3.5 -
Data input hold time
th(SD_SR) Slave receiver 2 -
tv(SD_ST) Slave transmitter (after enable edge) - 12
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 3
th(SD_ST) Slave transmitter (after enable edge) 5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0 -
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 49.152 MHz (APB1 maximum frequency).

Note: Refer to RM0410 reference manual I2S section for more details about the sampling
frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The
values of these parameters might be slightly impacted by the source clock precision. DCK
depends mainly on the value of ODD bit. The digital contribution leads to a minimum value
of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.

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Figure 49. I2S slave timing diagram (Philips protocol)(1)

tc(CK)

CPOL = 0
CK Input

CPOL = 1

tw(CKH) tw(CKL) th(WS)

WS input

tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(1) MSB transmit Bitn transmit LSB transmit

tsu(SD_SR) th(SD_SR)

SDreceive LSB receive(1) MSB receive Bitn receive LSB receive

MS46528V1

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 50. I2S master timing diagram (Philips protocol)(1)

tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(1) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive (1)
LSB receive MSB receive Bitn receive LSB receive

MS46529V1

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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JATG/SWD characteristics
Unless otherwise specified, the parameters given in Table 88 for JTAG/SWD are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).

Table 88. Dynamics characteristics: JTAG characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp 2.7V <VDD< 3.6V - - 40

MHz
TCK clock frequency
1/tc(TCK) - - 35
1.71 <VDD< 3.6V

tw(TCKH)
SCK high and low time - TPCLK − 1 TPCLK TPCLK + 1
tw(TCKL)

tsu(TMS) TMS input setup time - 3 - -

th(TMS) TMS input hold time - 0 - -

tsu(TDI) TDI input setup time - 0.5 - - ns

th(TDI) TDI input hold time - 2 - -

2.7V <VDD< 3.6V - 9 11

tov (TDO) TDO output valid time
- 9 13
1.71 <VDD< 3.6V

toh(TDO) TDO output hold time - 7.5 - -

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Table 89. Dynamics characteristics: SWD characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fpp 2.7V <VDD< 3.6V - - 80

MHz
SWCLK clock frequency
1/tc(SWCLK) - - 50
1.71 <VDD< 3.6V

tw(SWCLKH)
SCK high and low time - TPCLK − 1 TPCLK TPCLK + 1
tw(SWCLKL)

tsu(SWDIO) SWDIO input setup time - 3.5 - -

th(SWDIO) SWDIO input hold time - 0 - - ns

2.7V <VDD< 3.6V - 11 12

tov (SWDIO) SWDIO output valid time
- 11 16.5
1.71 <VDD< 3.6V

toh(SWDIO) SWDIO output hold time - 9 - -

JTAG/SWD timing diagrams

Figure 51. JTAG timing diagram

tc(TCK)

TCK

tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS

tov(TDO) toh(TDO)

TDO

MSv40458V1

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Figure 52. SWD timing diagram

tc(SWCLK)

SWCLK

tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)

tov(SWDIO) toh(SWDIO)

SWDIO
(transmit)

MSv40459V1

SAI characteristics:
Unless otherwise specified, the parameters given in Table 90 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).

Table 90. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK SAI Main clock output - 256 x 8K 256xFs MHz

Master data: 32 bits - 128xFs(3)
FCK SAI clock frequency(2) MHz
Slave data: 32 bits - 128xFs
Master mode
- 15
2.7≤VDD≤3.6V
tv(FS) FS valid time
Master mode
- 20
1.71≤VDD≤3.6V
tsu(FS) FS setup time Slave mode 7 -
Master mode 1 - ns
th(FS) FS hold time
Slave mode 1 -
tsu(SD_A_MR) Master receiver 3 -
Data input setup time
tsu(SD_B_SR) Slave receiver 3.5 -
th(SD_A_MR) Master receiver 5 -
Data input hold time
th(SD_B_SR) Slave receiver 1 -

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Table 90. SAI characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

Slave transmitter (after enable edge)

- 12
2.7≤VDD≤3.6V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 20
1.71≤VDD≤3.6V
th(SD_B_MT) Data output hold time Slave transmitter (after enable edge) 5 -
ns
Master transmitter (after enable edge)
- 15
2.7≤VDD≤3.6V
tv(SD_MT)_A Data output valid time
Master transmitter (after enable edge)
- 20
1.71≤VDD≤3.6V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 5 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192kHz.

Figure 53. SAI master timing waveforms

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

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Figure 54. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 91. USB OTG full speed startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB OTG full speed transceiver startup time 1 µs

1. Guaranteed by design.

Table 92. USB OTG full speed DC electrical characteristics

Min. Max.
Symbol Parameter Conditions (1) Typ. (1) Unit

USB OTG full speed

VDDUSB transceiver operating - 3.0(2) - 3.6 V
voltage
I(USB_FS_DP/DM,
Input VDI(3) Differential input sensitivity 0.2 - -
USB_HS_DP/DM)
levels
Differential common mode
VCM(3) Includes VDI range 0.8 - 2.5 V
range
Single ended receiver
VSE(3) - 1.3 - 2.0
threshold

Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6

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Table 92. USB OTG full speed DC electrical characteristics (continued)

Min. Max.
Symbol Parameter Conditions (1) Typ. (1) Unit

PA11, PA12, PB14, PB15

(USB_FS_DP/DM, 17 21 24
USB_HS_DP/DM)
RPD VIN = VDD
PA9, PB13
(OTG_FS_VBUS, 2.4 5.2 8
OTG_HS_VBUS) kΩ
PA12, PB15 (USB_FS_DP,
VIN = VSS 1.5 1.8 2.1
USB_HS_DP)
RPU PA9, PB13
(OTG_FS_VBUS, VIN = VSS 0.55 0.95 1.35
OTG_HS_VBUS)
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.

Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.

Figure 55. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

Table 93. USB OTG full speed electrical characteristics(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit

tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage - 1.3 2.0 V
Driving high or
ZDRV Output driver impedance(3) 28 44 Ω
low
1. Guaranteed by design.

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2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.

USB high speed (HS) characteristics

Unless otherwise specified, the parameters given in Table 96 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 95
and VDD supply voltage conditions summarized in Table 94, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
• Capacitive load C = 20 pF, unless otherwise specified
• Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.

Table 94. USB HS DC electrical characteristics

Symbol Parameter Min.(1) Max.(1) Unit

Input level VDD USB OTG HS operating voltage 1.7 3.6 V

1. All the voltages are measured from the local ground potential.

Table 95. USB HS clock timing parameters(1)

Symbol Parameter Min Typ Max Unit

fHCLK value to guarantee proper operation of

- 30 - - MHz
USB HS interface
FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz
FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz
DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 %
DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 %
Time to reach the steady state frequency and
tSTEADY - - 1.4 ms
duty cycle after the first transition
tSTART_DEV Clock startup time after the Peripheral - - 5.6
ms
tSTART_HOST de-assertion of SuspendM Host - - -
PHY preparation time after the first transition
tPREP - - - µs
of the input clock
1. Guaranteed by design.

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Figure 56. ULPI timing diagram

Clock

tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)

tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c

Table 96. Dynamic characteristics: USB ULPI(1)

Symbol Parameter Conditions Min. Typ. Max. Unit

tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 2 - -

tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1.5 - -
tSD Data in setup time - 2 - -
tHD Data in hold time - 1 - -
ns
2.7 V < VDD < 3.6 V,
- 6.5 8
CL = 20 pF
tDC/tDD Data/control output delay - -
1.7 V < VDD < 3.6 V, 6.5 11
-
CL = 15 pF
1. Guaranteed by characterization results.

Ethernet characteristics
Unless otherwise specified, the parameters given in Table 97, Table 98 and Table 99 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 97 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 57 shows the corresponding timing diagram.

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Figure 57. Ethernet SMI timing diagram

tMDC

ETH_MDC

td(MDIO)

ETH_MDIO(O)

tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

Table 97. Dynamics characteristics: Ethernet MAC signals for SMI(1)

Symbol Parameter Min Typ Max Unit

tMDC MDC cycle time(2.38 MHz) 400 400 403

Td(MDIO) Write data valid time THCLK + 1 THCLK + 1.5 THCLK + 3
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
1. Guaranteed by characterization results.

Table 98 gives the list of Ethernet MAC signals for the RMII and Figure 58 shows the
corresponding timing diagram.

Figure 58. Ethernet RMII timing diagram

RMII_REF_CLK

td(TXEN)
td(TXD)

RMII_TX_EN
RMII_TXD[1:0]

tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)

RMII_RXD[1:0]
RMII_CRS_DV

ai15667b

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Table 98. Dynamics characteristics: Ethernet MAC signals for RMII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 1 - -

tih(RXD) Receive data hold time 2 - -
tsu(CRS) Carrier sense setup time 2 - -
ns
tih(CRS) Carrier sense hold time 2 - -
td(TXEN) Transmit enable valid delay time 7.5 8 12
td(TXD) Transmit data valid delay time 7 7.5 12.5
1. Guaranteed by characterization results.

Table 99 gives the list of Ethernet MAC signals for MII and Figure 58 shows the
corresponding timing diagram.

Figure 59. Ethernet MII timing diagram

MII_RX_CLK

tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK

td(TXEN)
td(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668b

Table 99. Dynamics characteristics: Ethernet MAC signals for MII(1)

Symbol Parameter Min Typ Max Unit

tsu(RXD) Receive data setup time 1 - -

tih(RXD) Receive data hold time 2.5 - -
tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 0.5 - -
ns
tsu(ER) Error setup time 2.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 8 10 13
td(TXD) Transmit data valid delay time 7.5 9 13

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1. Guaranteed by characterization results.

Table 100. MDIO Slave timing parameters

Symbol Parameter Min Typ Max Unit

FsDC Management Data clock - - 40 MHz

td(MDIO) Management Data input/output output valid time 7 8 20
tsu(MDIO) Management Data input/output setup time 4 - - ns
th(MDIO) Management Data input/output hold time 1 - -

The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC

Figure 60. MDIO Slave timing diagram

tMDC)

td(MDIO)

tsu(MDIO) th(MDIO)

MSv40460V1

CAN (controller area network) interface

Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).

6.3.30 FMC characteristics

Unless otherwise specified, the parameters given in Table 101 to Table 114 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD

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Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.

Asynchronous waveforms and timings

Figure 61 through Figure 64 represent asynchronous waveforms and Table 101 through
Table 108 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capcitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period

Figure 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)

FMC_NE

tv(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

tv(A_NE) t h(A_NOE)

FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)

FMC_NBL[1:0]

t h(Data_NE)

t su(Data_NOE) th(Data_NOE)

t su(Data_NE)

FMC_D[15:0] Data

t v(NADV_NE)

tw(NADV)

FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32753V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 2THCLK − 1 2 THCLK +1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2THCLK − 1 2THCLK + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
ns
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time THCLK − 1 -
tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK − 1 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - THCLK + 1
1. CL = 30 pF.
2. Guaranteed by characterization results.

Table 102. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 7THCLK +1 7THCLK +1

tw(NOE) FMC_NWE low time 5THCLK −1 5THCLK +1

ns
tw(NWAIT) FMC_NWAIT low time THCLK −0.5 -
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 -
1. Guaranteed by characterization results.

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Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)

FMC_NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)

FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)

FMC_D[15:0] Data
t v(NADV_NE)

tw(NADV)
FMC_NADV (1)

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 103. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit
tw(NE) FMC_NE low time 3THCLK − 1 3THCLK + 1
tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK − 1 THCLK + 0.5
tw(NWE) FMC_NWE low time THCLK − 1.5 THCLK + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high THCLK − 0.5 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - THCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - THCLK + 1
1. Guaranteed by characterization results.

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Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT

timings(1)
Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK − 1 8THCLK + 1

tw(NWE) FMC_NWE low time 6THCLK − 1.5 6THCLK + 0.5

ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK − 1 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4THCLK + 2 -
invalid
1. Guaranteed by characterization results.

Figure 63. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)

FMC_ NE
tv(NOE_NE) t h(NE_NOE)

FMC_NOE

t w(NOE)

FMC_NWE

tv(A_NE) th(A_NOE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)
tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)

MS32755V1

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Table 105. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 3THCLK − 1 3THCLK + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK 2THCLK + 0.5
ttw(NOE) FMC_NOE low time THCLK − 1 THCLK + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time THCLK − 0.5 THCLK+1
FMC_AD(address) valid hold time after
th(AD_NADV) THCLK + 0.5 - ns
FMC_NADV high)
th(A_NOE) Address hold time after FMC_NOE high THCLK − 0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tsu(Data_NE) Data to FMC_NEx high setup time THCLK − 1 -
tsu(Data_NOE) Data to FMC_NOE high setup time THCLK − 1 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
1. Guaranteed by characterization results.

Table 106. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 8THCLK − 1 8THCLK + 1

tw(NOE) FMC_NWE low time 5THCLK − 1.5 5THCLK + 0.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK + 1.5 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4THCLK+ 1 -
invalid
1. Guaranteed by characterization results.

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Figure 64. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FMC_ NEx

FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

tv(A_NE) th(A_NWE)

FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)

FMC_ AD[15:0] Address Data

t v(NADV_NE) th(AD_NADV)

tw(NADV)

FMC_NADV

FMC_NWAIT
th(NE_NWAIT)

tsu(NWAIT_NE)
MS32756V1

Table 107. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 4THCLK − 1 4THCLK + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK − 1 THCLK + 0.5
tw(NWE) FMC_NWE low time 2THCLK − 0.5 2THCLK+ 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK − 0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time THCLK THCLK+ 1
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) THCLK − 0.5 -
FMC_NADV high)
th(A_NWE) Address hold time after FMC_NWE high THCLK + 0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - THCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high THCLK + 0.5 -

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1. Guaranteed by characterization results.

Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

Symbol Parameter Min Max Unit

tw(NE) FMC_NE low time 9THCLK – 1 9THCLK + 1

tw(NWE) FMC_NWE low time 7THCLK – 0.5 7THCLK + 0.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK + 2 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4THCLK – 1 -
invalid
1. Guaranteed by characterization results.

Synchronous waveforms and timings

Figure 65 through Figure 68 represent synchronous waveforms and Table 109 through
Table 112 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all the timing tables, the THCLK is the HCLK clock period.
– For 2.7 V≤ VDD ≤ 3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
– For 1.71 V≤ VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).

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Figure 65. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)

FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32757V1

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Table 109. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2THCLK − 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 2.5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 2.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
1. Guaranteed by characterization results.

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Figure 66. Synchronous multiplexed PSRAM write timings

tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16]

td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)

FMC_AD[15:0] AD[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Table 110. Synchronous multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2THCLK − 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2 .5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 0.5 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 -
1. Guaranteed by characterization results.

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Figure 67. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)

FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV
td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)

FMC_D[15:0] D1 D2

tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)

MS32759V1

Table 111. Synchronous non-multiplexed NOR/PSRAM read timings(1)

Symbol Parameter Min Max Unit

tw(CLK) FMC_CLK period 2THCLK − 0.5 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 2.5 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -

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1. Guaranteed by characterization results.

Figure 68. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)

FMC_CLK

td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx

td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV

td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0]

td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE

td(CLKL-Data) td(CLKL-Data)

FMC_D[15:0] D1 D2

FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL

MS32760V1

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Table 112. Synchronous non-multiplexed PSRAM write timings(1)

Symbol Parameter Min Max Unit

t(CLK) FMC_CLK period 2THCLK − 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK -
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK + 1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK + 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 -
1. Guaranteed by characterization results.

NAND controller waveforms and timings

Figure 69 through Figure 72 represent synchronous waveforms, and Table 113 and
Table 114 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.

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Figure 69. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)

FMC_NWE

tw(NOE)

FMC_NOE (NRE)

tsu(D-NOE) th(NOE-D)

FMC_D[y:0]

MSv73150V1

1. y = 7 or 15 depending on the NAND flash memory interface.

Figure 70. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)

FMC_NWE

FMC_NOE (NRE)

td(D-NWE)

tv(NWE-D) th(NWE-D)

FMC_D[y:0]

MSv73151V1

1. y = 7 or 15 depending on the NAND flash memory interface.

Table 113. Switching characteristics for NAND flash read cycles(1)

Symbol Parameter Min Max Unit

tw(N0E) FMC_NOE low width 4THCLK − 0.5 4THCLK + 0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK + 1
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4THCLK − 2 -
1. Guaranteed by characterization results.

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Table 114. Switching characteristics for NAND flash write cycles(1)

Symbol Parameter Min Max Unit

tw(NWE) FMC_NWE low width 4THCLK − 0.5 4THCLK + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2THCLK − 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK − 1 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3THCLK + 1
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2THCLK − 2 -
1. Guaranteed by characterization results.

SDRAM waveforms and timings

• CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
– For 3.0 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 100 MHz at CL=20 pF (on
FMC_SDCLK).
– For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK).
– For 1.71 V≤ VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on
FMC_SDCLK).

Figure 71. SDRAM read access waveforms (CL = 1)

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

MS32751V2

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Table 115. SDRAM read timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5

tsu(SDCLKH _Data) Data input setup time 2.5 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 3.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Guaranteed by characterization results.

Table 116. LPSDR SDRAM read timings(1)

Symbol Parameter Min Max Unit

tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5

tsu(SDCLKH_Data) Data input setup time 1 -

th(SDCLKH_Data) Data input hold time 3.5 -

td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL_SDNE) Chip select valid time - 2.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
1. Guaranteed by characterization results.

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Figure 72. SDRAM write access waveforms

FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)

FMC_A[12:0] Row n Col1 Col2 Coli Coln

th(SDCLKL_AddC)

td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)

FMC_SDNRAS

td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE
td(SDCLKL_Data)

FMC_D[31:0] Data1 Data2 Datai Datan

td(SDCLKL_NBL) th(SDCLKL_Data)

FMC_NBL[3:0]
MS32752V2

Table 117. SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5

td(SDCLKL _Data) Data output valid time - 3
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 3.5
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
1. Guaranteed by characterization results.

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Table 118. LPSDR SDRAM write timings(1)

Symbol Parameter Min Max Unit

tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5

td(SDCLKL _Data) Data output valid time - 2.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2.5
td(SDCLKL-SDNWE) SDNWE valid time - 2.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 0.5
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
1. Guaranteed by characterization results.

6.3.31 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 119 and Table 120 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics.

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Table 119. QUADSPI characteristics in SDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V≤VDD<3.6 V
- - 108
QUADSPI clock CL=20 pF
Fck1/t(CK) MHz
frequency 1.71 V<VDD<3.6 V
- - 100
CL=15 pF
tw(CKH) QUADSPI clock high and t(CK)/2 - 1 - t(CK)/2
-
tw(CKL) low time t(CK)/2 - t(CK)/2 + 1
2.7 V<VDD<3.6 V 1.5 - -
ts(IN) Data input setup time
1.71 V<VDD<3.6 V 1.5 - -
2.7 V<VDD<3.6 V 1.5 - - ns
th(IN) Data input hold time
1.71 V<VDD<3.6 V 2 - -
2.7 V<VDD<3.6 V - 1.5 2
tv(OUT) Data output valid time
1.71 V<VDD<3.6 V - 1.5 3.5
th(OUT) Data output hold time - 0.5 - -
1. Guaranteed by characterization results.

Table 120. QUADSPI characteristics in DDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

2.7 V<VDD<3.6 V
- - 80
CL=20 pF
QUADSPI clock 1.8 V<VDD<3.6 V
Fck1/t(CK) - - 80 MHz
frequency CL=15 pF
1.71 V<VDD<3.6 V
- - 80
CL=10 pF

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Table 120. QUADSPI characteristics in DDR mode(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tw(CKH) t(CK)/2 - 1 - t(CK)/2

QUADSPI clock high
- t(CK)/2
tw(CKL) and low time t(CK)/2 -
+1
ts(IN),
Data input setup time 1.71 V<VDD<3.6 V 1.75 - -
tsf(IN)

thr(IN), 2.7 V<VDD<3.6 V 1 - -

Data input hold time
thf(IN) 1.71 V<VDD<3.6 V 2 - -
2.7 V<VDD<3.6 V - 8.5 10 ns
1.71 V<VDD<3.6 V
tvr(OUT), - 8 12
Data output valid time DHHC=0
tvf(OUT)
DHHC=1 THCLK/2 + THCLK/2
-
Pres=1, 2... 1.5 + 2.5
DHHC=0 7.5 - -
thr(OUT),
Data output hold time DHHC=1 THCLK/2
thf(OUT) - -
Pres=1, 2... + 0.5
1. Guaranteed by characterization results.

Figure 73. Quad-SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V1

Figure 74. Quad-SPI timing diagram - DDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output D0 D1 D2 D3 D4 D5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input D0 D1 D2 D3 D4 D5
MSv36879V1

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6.3.32 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 121 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits

Table 121. DCMI characteristics(1)

Symbol Parameter Min Max Unit

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 54 MHz
DPixel Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2 -
th(DATA) Data input hold time 0.5 -
tsu(HSYNC) ns
DCMI_HSYNC/DCMI_VSYNC input setup time 2.5 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time 3 -
th(VSYNC)
1. Guaranteed by characterization results.

Figure 75. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK

tsu(HSYNC) th(HSYNC)

DCMI_HSYNC

tsu(VSYNC) th(HSYNC)

DCMI_VSYNC
tsu(DATA) th(DATA)

DATA[0:13]

MS32414V2

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6.3.33 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 122 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits

Table 122. LTDC characteristics (1)

Symbol Parameter Min Max Unit

fCLK LTDC clock output frequency - 83 MHz

DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)/2−0.5 tw(CLK)/2+0.5
tw(CLKL)
tv(DATA) Data output valid time - 6

th(DATA) Data output hold time 0 -

tv(HSYNC), ns
tv(VSYNC), HSYNC/VSYNC/DE output valid time - 3.5
tv(DE)
th(HSYNC),
th(VSYNC), HSYNC/VSYNC/DE output hold time 0.5 -
th(DE)
1. Guaranteed by characterization results.

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Figure 76. LCD-TFT horizontal timing diagram

tCLK

LCD_CLK

LCD_VSYNC

tv(HSYNC) tv(HSYNC)

LCD_HSYNC
tv(DE) th(DE)

LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)

HSYNC Horizontal Active width Horizontal

width back porch back porch

One line
MS32749V1

Figure 77. LCD-TFT vertical timing diagram

tCLK

LCD_CLK

tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]

VSYNC Vertical Active width Vertical

width back porch back porch

One frame
MS32750V1

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6.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 123 for DFSDM are derived from
tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage
summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for
DFSDM1).

Table 123. DFSDM measured timing 1.71-3.6V

Uni
Symbol Parameter Conditions Min Typ Max
t

fDFSDMCL
DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK
K

SPI mode (SITP[1:0]=0,1), 20

External clock mode (SPICKSEL[1:0]=0), - - (fDFSDMCLK/
1.71 < VDD < 3.6 V 4)

SPI mode (SITP[1:0]=0,1), 20

External clock mode (SPICKSEL[1:0]=0), - - (fDFSDMCLK/
2.7 < VDD < 3.6 V 4)

fCKIN Input clock

SPI mode (SITP[1:0]=0,1), 20 MH
(1/TCKIN) frequency
Internal clock mode (SPICKSEL[1:0]≠0), - - (fDFSDMCLK/ z
1.71 < VDD < 3.6 V 4)

SPI mode (SITP[1:0]=0,1), 20

Internal clock mode (SPICKSEL[1:0]≠0), - - (fDFSDMCLK/
2.7 < VDD < 3.6 V 4)

Output clock
fCKOUT 1.71 < VDD < 3.6 V - - 20
frequency

Even division
CKOUTDIV = n, 1, 3, 45 50 55
Output clock 5...
DuCyCK
frequency 1.62 < VDD < 3.6 V (((n/2 (((n/2+1)/(n+ %
OUT duty cycle Odd division
(((n/2+1)/(n+ +1)/(n 1))*100)+5
CKOUTDIV = n, 2, 4,
1))*100)-5 +1))*1
6...
00)

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Table 123. DFSDM measured timing 1.71-3.6V (continued)

Uni
Symbol Parameter Conditions Min Typ Max
t

SPI mode
Input clock (SITP[1:0]=0,1),
twh(CKIN) TCKIN/2 - TCKIN/
high and low External clock mode - -
twl(CKIN) 0.5 2
time (SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V

SPI mode
(SITP[1:0]=0,1),
Data input
tsu External clock mode - 2 - -
setup time
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V

ns

SPI mode
(SITP[1:0]=0,1),
Data input
th External clock mode - 3 - -
hold time
(SPICKSEL[1:0]=0),
1.71 < VDD < 3.6 V

Manchester mode
Manchester
(SITP[1:0]=2,3), (CKOUTDIV (2*CKOUTD
TManchest data period
Internal clock mode - +1) * - IV) *
er (recovered
(SPICKSEL[1:0]≠0), TDFSDMCLK TDFSDMCLK
clock period)
1.71 < VDD < 3.6 V

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6.3.35 DFSDM timing diagrams

Figure 78. Channel transceiver timing diagrams

DFSDM_CKINy

(SPICKSEL=0)
SPI timing : SPICKSEL = 0

twl twh tr tf
tsu th
DFSDM_DATINy

SITP = 00

tsu th

SITP = 01

SPICKSEL=3
DFSDM_CKOUT

SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3

SPICKSEL=1

twl twh tr tf
tsu th
DFSDM_DATINy

SITP = 0

tsu th

SITP = 1

SITP = 2
DFSDM_DATINy
Manchester timing

SITP = 3

recovered clock

recovered data 0 0 1 1 0
MS30766V2

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6.3.36 SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 124 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.

Figure 79. SDIO high-speed mode

Figure 80. SD default mode

CK
tOVD tOHD
D, CMD
(output)

ai14888

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Table 124. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 -
ns
tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in MMC and SD HS mode

tISU Input setup time HS fpp =50 MHz 4.5 - -

ns
tIH Input hold time HS fpp =50 MHz 1.5 - -

CMD, D outputs (referenced to CK) in MMC and SD HS mode

tOV Output valid time HS fpp =50 MHz - 11 12

ns
tOH Output hold time HS fpp =50 MHz 9 - -

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD fpp =25 MHz 4.5 - -

ns
tIHD Input hold time SD fpp =25 MHz 1.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD fpp =25 MHz - 0.5 1.5
ns
tOHD Output hold default time SD fpp =25 MHz 0 - -
1. Guaranteed by characterization results.

Table 125. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 -
ns
tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 -

CMD, D inputs (referenced to CK) in eMMC mode

tISU Input setup time HS fpp =50 MHz 4 - -

ns
tIH Input hold time HS fpp =50 MHz 3 - -

CMD, D outputs (referenced to CK) in eMMC mode

tOV Output valid time HS fpp =50 MHz - 11 15.5

ns
tOH Output hold time HS fpp =50 MHz 9.5 - -
1. Guaranteed by characterization results.
2. Cload = 20 pF.

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433 ) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

7.2 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

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Figure 81. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

Table 126. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

A1(12) 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570

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Table 126. LQFP100 - Mechanical data (continued)

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

b(9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11) 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
(11)
c1 0.09 - 0.16 0.0035 - 0.0063
D(4) 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
(4)
E 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
(13)
N 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 82. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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7.3 TFBGA100 package information (A08Q)

This TFBGA is 100 - ball, 8X8 mm, 0.8 mm pitch fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 83. TFBGA100 - Outline(13)

E1
e SE

K
J
H
G e
SD F
E D1
D
C
B
A

A1 ball pad
corner 1 2 3 4 5 6 7 8 9 10
Øb (N balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C
ccc C
ddd C

Seating
7
plane
A
C
A1 A2
SIDE VIEW

B E A

8 A1 ball pad
corner
(DATUM A)

(DATUM B)

(4x)
aaa C
TOP VIEW
A08Q_UFBGA100_ME_V2

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Table 127. TFBGA100 - Mechanical data

millimeters(1) inches(12)
Symbol
Min Typ Max Min Typ Max

A(2)(3) - - 1.20 - - 0.0472

(4)
A1 0.15 - - 0.0059 - -
A2 - 0.74 - - 0.0291 -
(5)
b 0.35 0.40 0.45 0.0138 0.0157 0.0177
(6)
D 8.00 BSC 0.3150 BSC
D1 7.20 BSC 0.2835 BSC
E 8.00 BSC 0.3150 BSC
E1 7.20 BSC 0.2835 BSC
(9)
e 0.80 BSC 0.0315 BSC
N(11) 100
SD(12) 0.40 BSC 0.0157 BSC
SE(12) 0.40 BSC 0.0157 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.10 0.0039
eee 0.15 0.0059
fff 0.08 0.0031

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2018.
2. TFBGA stands for thin profile fine pitch ball grid array: 1.00 mm < A ≤ 1.20 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 84. TFBGA100 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 128. TFBGA100 - Example of PCB design rules (0.8 mm pitch BGA)
Dimension Values

Pitch 0.8
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

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7.4 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 85. LQFP144 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE

0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x

(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C

D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING

1
2
3 E 1/4

(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)

E1 E b1 BASE METAL
(11)

SECTION B-B

A A
(Section A-A)

TOP VIEW
1A_LQFP144_ME_V2

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Table 129. LQFP144 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 86. LQFP144 - Footprint example

108 73
1.35

109 0.35 72

0.50

19.90 17.85
22.60

144 37

1 36

19.90
22.60
1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

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7.5 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
Note: See list of notes in the notes section.

Figure 87. LQFP176 - Outline(15)

ș2 ș1

(2) R1

H R2

B(See SECTION B-B)

(6) GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
(1) (11)
bbb H A-B D
aaa C A-B D

BOTTOM VIEW SECTION A-A

A2 0.05
(N-4) x e 
C
A
A1 (12) ddd C A-BD ccc C
b

SIDE VIEW

D (4)
(2) (5) D1
D  (9) (11)
(10) N
(4) b WITH PLATING

E1/4

(11) c c1 (11)
D1/4 (6) (5)

A B (2)
E1 E b1 BASE METAL
(11)

SECTION A-A
A A
SECTION B-B

TOP VIEW 1T_LQFP176_ME_V2

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Table 130. LQFP176 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1(12) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(9)(11)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(11)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(11) 0.090 - 0.200 0.0035 - 0.0079
(11)
c1 0.090 - 0.160 0.0035 - 0.063
(4)
D 26.000 1.0236
(2)(5)
D1 24.000 0.9449
E(4) 26.000 0.0197
(2)(5)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(1)(11) 1 0.0394 REF
N(13) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(1)
aaa 0.200 0.0079
(1)
bbb 0.200 0.0079
(1)
ccc 0.080 0.0031
ddd(1) 0.080 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

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Figure 88. LQFP176 - Footprint example

1.2
176 133
1 0.5 132

0.3
26.7

21.8

44 89
45 88
1.2

21.8

26.7

1T_FP_V1

1. Dimensions are expressed in millimeters.

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7.6 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package

Figure 89. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C

A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F

D1 D

e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C

A0E7_ME_V10

1. Drawing is not to scale.

Table 131. UFBGA(176+25) - Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031

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Table 131. UFBGA(176+25) - Mechanical data (continued)

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 90. UFBGA(176+25) - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 132. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)
Dimension Values

Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm

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7.7 WLCSP package information

Figure 91. WLCSP 180-bump, 5.5 x 6 mm, 1.27 mm pitch wafer level chip scale
package outline
e1 A1 BALL
D F
LOCATION

DETAIL A

E e2

A1
ORIENTATION
REFERENCE
e

A
e A2
A3

TOP VIEW BOTTOM VIEW SIDE VIEW

BUMP

SEATING PLANE
DETAIL A
ROTATED 90o
A05G_WLCSP180_ME_V1

1. Drawing is not to scale.

Table 133. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.525 0.555 0.585 0.0207 0.0219 0.0230

A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
A3 - 0.025 - - 0.0010 -
(2)
b 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 5.502 5.537 5.572 0.2166 0.2180 0.2194
E 6.060 6.095 6.130 0.2386 0.2400 0.2413

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Table 133. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

e - 0.400 - - 0.0157 -
e1 - 4.800 - - 0.1890 -
e2 - 5.200 - - 0.2047 -
F - 0.368 - - 0.0145 -
G - 0.477 - - 0.0188 -
aaa - 0.110 - - 0.0043 -
bbb - 0.110 - - 0.0043 -
ccc - 0.110 - - 0.0043 -
ddd - 0.050 - - 0.0020 -
eee - 0.050 - - 0.0020 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 92. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint

Dpad

Dsm

A05G_WLCSP180_FP_V1

Table 134. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules
(0.4 mm pitch)
Dimension Recommended values
Pitch 0.4
Dpad 0.225 mm

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Table 134. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules
(0.4 mm pitch) (continued)
Dimension Recommended values
0.290 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.1 mm

WLCSP180 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 93. WLCSP180 top view example

Product identification(1)

Date code Revision code

Y WW

Ball A1identifier

MSv41044V2

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7.8 LQFP208 package information

This LQFP is a 208-pin, 28 x 28 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 94. LQFP208 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1
R2

B
H

B-
N
O
TI
C
SE
B GAUGE PLANE

0.25
D 1/4 (6)
S
B
L
3
(L1) (1) (11)

E 1/4 SECTION A-A

4x N/4 TIPS
aaa C A-B D bbb H A-B D 4x

(N – 4)x e (13)
C
A
A2
b ddd C A-B D
0.05 A1(12) ccc C
D (4)
(2) (5) D1
D (3)
(10) N
(4) (9) (11)
b WITH
1 PLATING
2
3
E 1/4
(11) (11)
c c1

D 1/4 (6)
b1 BASE METAL
(3) A B (3) (11)

E1 E SECTION B-B
(2)
(5)

A A
(Section A-A)

TOP VIEW UH_LQFP208_ME_V2

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Table 135. LQFP208 - Mechanical data

millimeters inches(15)
Symbol
Min Typ Max Min Typ Max

A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 30.00 BSC 1.1732 BSC
(2)(5)
D1 28.00 BSC 1.0945 BSC
E(4) 30.00 BSC 1.1732 BSC
E1(2)(5) 28.00 BSC 1.0945 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 208
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
ccc(1)(7) 0.08 0.0031
(1)(7)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 95. LQFP208 - footprint example

208 157

1 156
0.50 1.25
0.30
28.3
30.7

52 105

53 104 1.2
25.8
30.7
UH_LQFP208_FP_V3

1. Dimensions are expressed in millimeters.

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7.9 TFBGA216 package information (A0L2)

This TFBGA is a 216-ball, 13 x 13 mm, 0.8 mm pitch, fine pitch ball grid array package.

Figure 96. TFBGA216 - Outline

Z Seating plane

ddd Z

A2
A1 A
D1 A1 ball A1 ball X
identifier index area D
e F

A
G

E1 E

e
Y
R
15 1
BOTTOM VIEW Øb (216 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
A0L2_ME_V3

1. Drawing is not to scale.

2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional

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Table 136. TFBGA216 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.200 - - 0.0472
(2)
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
(3)
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 12.850 13.000 13.150 0.5059 0.5118 0.5177
D1 - 11.200 - - 0.4409 -
E 12.850 13.000 13.150 0.5059 0.5118 0.5177
E1 - 11.200 - - 0.4409 -
e - 0.800 - - 0.0315 -
F - 0.900 - - 0.0354 -
G - 0.900 - - 0.0354 -
ddd - - 0.100 - - 0.0039
(4)
eee - - 0.150 - - 0.0059
(5)
fff - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
3. Initial ball equal 0.350 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.

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Figure 97. TFBGA216 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

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Table 137. TFBGA216 - Example of PCB design rules (0.8 mm pitch)

Dimension Values

Pitch 0.8 mm
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm

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7.10 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = ∑ (VOL × IOL) + ∑((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 138. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

43
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
36.2
TFBGA100 - 8 × 8 mm / 0.8 mm pitch
Thermal resistance junction-ambient
30
WLCSP180 - 0.4 mm pitch
Thermal resistance junction-ambient
40
LQFP144 - 20 × 20 mm / 0.5 mm pitch
ΘJA °C/W
Thermal resistance junction-ambient
38
LQFP176 - 24 × 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
19
LQFP208 - 28 × 28 mm / 0.5 mm pitch
Thermal resistance junction-ambient
39
UFBGA176 - 10× 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
29
TFBGA216 - 13 × 13 mm / 0.8 mm pitch

Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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Ordering information STM32F777xx STM32F778Ax STM32F779xx

8 Ordering information
Table 139. Ordering information scheme
Example: STM32 F 77x V G T 6 xxx

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
F = general-purpose

Device subfamily
777= STM32F777xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT, cryptographic acceleration
778 = STM32F778Ax, USB OTG FS/HS, camera interface,
LCD-TFT and DSI host, WLCSP with internal regulator OFF, cryptographic
acceleration
779= STM32F779xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT and DSI host., cryptographic acceleration

Pin count
V = 100 pins
Z = 144 pins
I = 176 pins
A = 180 pins
B = 208 pins
N = 216 pins

Flash memory size

G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory

Package
T = LQFP
K = UFBGA
H = TFBGA
Y = WLCSP

Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.(1)

Options
xxx = programmed parts
TR = tape and reel
1. Not available for WLCSP packages.

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For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

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Recommendations when using internal reset OFF STM32F777xx STM32F778Ax STM32F779xx

Appendix A Recommendations when using internal reset

OFF

When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• VBAT functionality is no more available and VBAT pin should be connected to VDD
The over-drive mode is not supported

A.1 Operating conditions

Table 140. Limitations depending on the operating power supply range
Maximum
Flash
Operating memory Maximum Flash
Possible Flash
power ADC access memory access
I/O operation memory
supply operation frequency frequency with
operations
range with no wait wait states (1)(2)
states
(fFlashmax)

Conversion 168 MHz with 8 8-bit erase and

VDD =1.7 to – No I/O
time up to 20 MHz wait states and program
2.1 V(3) compensation
1.2 Msps over-drive OFF operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or L1-
cache allows to achieve a performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.18.1: Internal reset ON).

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Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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Revision history STM32F777xx STM32F778Ax STM32F779xx

Revision history

Table 141. Document revision history

Date Revision Changes

21-Mar-2016 1 Initial release.

DFSDM replaced by DFSDM1 in:
Table 2: STM32F765xx, STM32F767xx, STM32F768Ax, and
STM32F769xx pin and ball definitions.
Table 4: STM32F765xx, STM32F767xx, STM32F768Ax, and
STM32F769xx alternate function mapping.
Table 14: STM32F777xx, STM32F778Ax and STM32F779xx
register boundary addresses.
Section 1.3.34: Digital filter for Sigma-Delta Modulators (DFSDM)
26-Apr-2016 2 characteristics.
Updated Table 2: STM32F777xx, STM32F778Ax and
STM32F779xx features and peripheral counts adding DFSDM1
features.
Updated Table 26: Peripheral current consumption adding
DFSDM1 current consumption.
Updated cover in 2 pages.
Updated cover replacing for SPI ‘up to 50 Mbit/s’ by ‘up to 54
Mbit/s’.
Updated Table 2: STM32F777xx, STM32F778Ax and STM32F779xx
features and peripheral counts GPIO number.
06-May-2016 3 Updated Table 4: STM32F765xx, STM32F767xx, STM32F768Ax, and
STM32F769xx alternate function mapping adding CAN3_RX alternate
function on PA8/AF11.
Updated Table 98: Dynamics characteristics: Ethernet MAC signals for
RMII.
Updated Table 72: ADC characteristics sampling rate.
Updated all the notes removing ‘not tested in production’.
Updated Figure 46: SPI timing diagram - slave mode and CPHA = 0 and
Figure 47: SPI timing diagram - slave mode and CPHA = 1(1) with
22-Dec-2016 4
modified NSS timing waveforms (among other changes).
Updated Table 122: LTDC characteristics clock output frequency at 65
MHz.
Updated Section 6.2: Absolute maximum ratings.
Updated Section 7: Package information adding information about other
optional marking or inset/upset marks.

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Table 141. Document revision history (continued)

Date Revision Changes

Updated note 1 below all the package device marking figures.

Updated cover title.
Updated Section 1: Introduction.
Updated Section 3.47: DSI Host (DSIHOST) video mode interface
features.
Added Table 9: DFSDM implementation.
Updated Figure 11: STM32F76xxx LQFP100 pinout pin 43 and pin 44.
09-Aug-2017 5 Updated Table 65: I/O current injection susceptibility note by ‘injection is
not possible’.
Updated Table 122: LTDC characteristics LTDC clock frequency at 83
MHz.
Updated Table 72: ADC characteristics RADC min at 1.5 Kohm.
Updated Figure 40: Recommended NRST pin protection note about the
0.1uF capacitor.
Updated Table 83: DAC characteristics RLOAD feature.
Added TFBGA100 package:
– Updated cover page.
– Updated Table 2: STM32F777xx, STM32F778Ax and STM32F779xx
features and peripheral counts.
– Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability.
– Added Figure 12: STM32F76xxx TFBGA100 pinout.
– Updated Table 11: STM32F765xx, STM32F767xx, STM32F768Ax, and
05-Sep-2017 6 STM32F769xx pin and ball definitions.
– Updated Table 17: General operating conditions.
– Updated Table 63: ESD absolute maximum ratings.
– Updated note below Figure 43: Power supply and reference
decoupling (VREF+ not connected to VDDA).
– Updated note below Figure 44: Power supply and reference
decoupling (VREF+ connected to VDDA).
– Added Section 7.3: TFBGA100 package information.
– Updated Table 7.3: Thermal characteristics.

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Table 141. Document revision history (continued)

Date Revision Changes

Added the sections:

Section 7.1: Device marking
Section 9: Important security notice

Removed sections in:

Section 7: Package information (obsolete content).
Figure 71 NAND controller waveforms for common memory read access
Figure 72 NAND controller waveforms for common memory write access

Updated the following sections:

Section 6.3.5: Reset and power control block characteristics
(PLS[2:0]=101 (falling edge)).
Section : Features (disclaimer).
Section 6.3.17: EMC characteristics (Update of Section Table 62.: EMI
characteristics for fHSE= 8 MHz and fCPU= 200MHz (Setting 2) and
Section Table 61.: EMI characteristics for fHSE= 8 MHz and fCPU=
200MHz (Setting 1)
Section 6.3.7: Supply current characteristics (Update of I/O system
current consumption).
Section Figure 39.: I/O AC characteristics definition (Updated the text in
the image).
Section 6.3.7: Supply current characteristics (Replaced Typical
connection diagram using the ADC by Section Figure 42.: Typical
20-Nov-2023 7 connection diagram when using the ADC with FT/TT pins featuring
analog switch function).
Table 2: STM32F777xx, STM32F778Ax and STM32F779xx features and
peripheral counts (Operating temperatures, GPIO).
Section 8: Ordering information (Addition of a note).
Section 3.40: Random number generator (RNG) (Update of the RNG
section).
Section Table 123.: DFSDM measured timing 1.71-3.6V (DuCyCKOUT).
Section 6.3.9: External clock source characteristics
(High-speed external clock generated from a crystal/ceramic resonator,
Low-speed external clock generated from a crystal/ceramic resonator).
Section Figure 16.: STM32F77xxx UFBGA176 ballout (addition of a
note).
Section 6.3.20: I/O port characteristics (Addition of a note).
Section 3.26: Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S) (SPI2 and SPI3 values).
Table 45: HSI oscillator characteristics (Update of a footnote).
Figure 46: SPI timing diagram - slave mode and CPHA = 0
Figure 47: SPI timing diagram - slave mode and CPHA = 1
Figure 48: SPI timing diagram - master mode
Figure 69: NAND controller waveforms for read access
Figure 70: NAND controller waveforms for write access
Applied minor terminology changes to the whole document.

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