1.
Reduce the following Boolean Expressions to minimum number of literals
2. Determine the minimum SOP form using K map:
3. Simplify and implement using NAND gate:
F(x,y,z)=∑m(1,2,3,4,5,7)
4. Show that a
a. positive logic NAND gate is a negative logic NOR gate
b. Positive OR is Negative AND
5. Design using multiple level NOR gates for
F= CD(B+C)A+(BC’+DE’)
6. For the given F(ABCD)= A’B’+
CD’+ABC+A’B’CD’+ABCD’
a) Plot K map without expanding minterms.
b) Identify PI, EPI .
c) Find SOP in minimal form.
d) Design AND-OR circuit for SOP expression
7. Find all the prime implicants for the following Boolean functions, and
determine EPI . Also find the minimal SOP.
(a) F (w, x, y, z) = ∑ (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
(b) F (A, B, C, D) = ∑ (0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
8. Design using Multi-level NAND gates
F= W(X+Y+Z)+XY
9. Design Verilog HDL to describe structural model with a programming
example.,
10. Design Verilog HDL to describe data flow model with a programming
example.,
11. Design Verilog HDL to describe behavioral model with a programming
example.,
12. Develop a Verilog code using dataflow and behavioral model for the expression
F (A, B, C, D) = (AB’+A’B)(CB+AD’)(AB’C+AC)
Module 2:
1. Implement the design of combinational circuit BCD and Excess3 code
convertor.
2. Implement full adder using 3:8 decoder.
3. Explain the following circuits with Block Diagram, Truth Table, output
Expressions , logic circuit and develop Verilog code for:
a. Half Adder
b. Full Adder
c. Half Subtractor
d. Full Subtractor
4. Design the following decoders with logic diagram and truth table and explain
the operation of :
a. 2:4 decoder
b. 3:8 decoder
5. Differentiate between Combinational and Sequential circuits with
examples.
6. Explain the steps adopted in design procedure of combinational
circuits.
