RG50xQ Series

Hardware Design

5G Module Series

Version: 1.2

Date: 2021-09-29

Status: Released
 5G Module Series

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 5G Module Series

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a) We acknowledge no liability for any injury or damage arising from the reliance upon the information.

b) We shall bear no liability resulting from any inaccuracies or omissions, or from the use of the
information contained herein.

c) While we have made every effort to ensure that the functions and features under development are
free from errors, it is possible that they could contain errors, inaccuracies, and omissions. Unless
otherwise provided by valid agreement, we make no warranties of any kind, either implied or express,
and exclude all liability for any loss or damage suffered in connection with the use of features and
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Copyright © Quectel Wireless Solutions Co., Ltd. 2021. All rights reserved.

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 5G Module Series

Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to
comply with these precautions.

Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.

Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.

Wireless devices may cause interference on sensitive medical equipment, so

please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.

Cellular terminals or mobiles operating over radio signal and cellular network
cannot be guaranteed to connect in certain conditions, such as when the mobile bill
is unpaid or the (U)SIM card is invalid. When emergency help is needed in such
conditions, use emergency call if the device supports it. In order to make or receive
a call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength. In an emergency, the device with emergency call
function cannot be used as the only contact method considering network
connection cannot be guaranteed under all circumstances.

The cellular terminal or mobile contains a transceiver. When it is ON, it receives

and transmits radio frequency signals. RF interference can occur if it is used close
to TV sets, radios, computers or other electric equipment.

In locations with explosive or potentially explosive atmospheres, obey all posted

signs and turn off wireless devices such as mobile phone or other cellular
terminals. Areas with explosive or potentially explosive atmospheres include
fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities,
and areas where the air contains chemicals or particles such as grain, dust or
metal powders.

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 5G Module Series

About the Document

Revision History

Version Date Author Description

Bourne WAN/
1.0 2020-07-10 Initial
Peng GUO
1. Updated the frequency bands in 5G NR NSA and SA
modes of RG500Q-EA/RG502Q-EA (Table 1&39).
LTE-TDD B43 has been fully developed (Table 1).
2. Updated the frequency bands in 5G NR SA mode of
RG500Q-NA* (Table 2).
3. Added bandwidth support status and a note about SCS
of 5G NR features;
Updated the support status of LTE UL 256QAM
modulation as under development;
HPUE has been fully developed (Table 3).
4. Added note 2 about 5G NR uplink 2 × 2 MIMO of
RG50xQ series;
David WANG/ Added note 4 about maximum data transmission rates
1.1 2020-09-28 Bourne WAN/ (Chapter 2.2).
Peng GUO 5. Updated the support status of BT UART and COEX
UART as under development (Table 3&5&Chapter
3.18).
6. Updated the support status of pin UART1_DCD of main
UART interface as under development (Table 5&13).
7. Updated the DC characteristics of PWRKEY (Table
5&8).
8. Updated the description of cellular antenna mapping of
RG50xQ series (Table 5&33&34).
9. Updated the RESET_N internally pulled up to 1.5 V
(Table 5&Chapter 3.8).
10. Updated the support status of function of waking up
host by RI signal with a URC to report as under

RG50xQ_Series_Hardware_Design 4 / 131
 5G Module Series

development (Chapter 3.5.1.1&3.5.1.3).

11. Updated the support status of function of remote
waking up host by USB bus with a URC to report as
under development (Chapter 3.5.1.2).
12. Updated the timing of turning on the module (Figure
13).
13. Updated the timing of turning off the module (Figure
14).
14. Updated the timing of resetting the module and added
note 3 about RESET_N (Figure 17).
15. Updated the current consumption of
RG500Q-EA/RG502Q-EA (Table 43).
16. Updated the note for the standard of 5G NR minimum
RF output power (Table 45).
17. Updated the frequency and 3GPP (SIMO) of n5 of 5G
NR (Table 47).
1. Added RG500Q-CN, RG501Q-EU, RG502Q-EU and
the relevant information;
Deleted RG500Q-NA and the relevant information.
2. Updated RG500Q-EA and RG502Q-EA modules’ 5G
NR NSA UL max. transmission data and added the
relevant note;
Added eSIM feature description;
Added bandwidth configuration of EN-DC;
Added Cat 20/16 description in LTE Features;
Updated the supported USB serial drivers information
(Table 6).
3. Updated the DC characteristics of VDD_WIFI_VM
Zack ZHAO/ (Table 8).
Qiqi WANG/ 4. Updated pin 98 from RESERVED to GPIO_32; added
1.2 2021-09-29
Cathy ZHAO/ the information of time service and repeater function
Jerax KONG (Figure 4–6, Table 8, Chapter 3.25).
5. Updated related RI functions of waking up host
(Chapter 3.4.1.1&3.4.1.3).
6. Updated the decoupling capacitance of the power
supply (Chapter 3.5.2).
7. Added reset chip control description and deleted button
reset reference circuit diagram (Chapter 3.7).
8. Added the module USB trace length (Table 16–18).
9. Deleted Table Logic Levels of Digital I/O and added a
note that the other band rates of the main UART
interface are under development (Chapter 3.10).
10. Updated the function status of the RI behaviors and
quickly flickering of the NET_STATUS (Chapter

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 5G Module Series

3.13&3.15, Table 8&19).

11. Added the module PCIe trace length (Table 28–30).
12. Added a TVS protection to power supply of the SD card
connector; added the module SDC trace length
(Chapter 3.20).
13. Added the module RGMII trace length (Table 42–44).
14. Added RF Connector information (Chapter 5.4.3&
5.4.4).
15. Updated the power consumption and Rx sensitivity
data (Chapter 6.4&6.6).
16. Changed the unspecified dimensional tolerances from
±0.05 mm to ±0.2 mm; updated the top and bottom
views of modules (Chapter 7).
17. Updated the relevant information of module storage,
manufacturing and soldering;
Added module coating and cleaning information;
Updated packaging specification (Chapter 8).

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Contents

Safety Information ....................................................................................................................................... 3

About the Document ................................................................................................................................... 4
Contents ....................................................................................................................................................... 7
Table Index ................................................................................................................................................. 10
Figure Index ............................................................................................................................................... 12

1 Introduction ........................................................................................................................................ 14
1.1. Special Marks .......................................................................................................................... 15

2 Product Overview .............................................................................................................................. 16

2.1. General Description ................................................................................................................. 16
2.2. Key Features ........................................................................................................................... 17
2.3. Functional Diagram ................................................................................................................. 21
2.4. EVB .......................................................................................................................................... 24

3 Application Interfaces ....................................................................................................................... 25

3.1. Pin Assignment ........................................................................................................................ 26
3.2. Pin Description......................................................................................................................... 29
3.3. Operating Modes ..................................................................................................................... 45
3.4. Power Saving........................................................................................................................... 45
3.4.1. Sleep Mode .................................................................................................................... 45
3.4.1.1. UART Application................................................................................................. 46
3.4.1.2. USB Application with USB Remote Wakeup Function ........................................ 47
3.4.1.3. USB Application with USB Suspend/Resume and RI Function .......................... 47
3.4.1.4. USB Application without USB Suspend Function ................................................ 48
3.4.2. Airplane Mode ................................................................................................................ 49
3.5. Power Supply........................................................................................................................... 49
3.5.1. Power Supply Pins ......................................................................................................... 49
3.5.2. Voltage Stability Requirements ...................................................................................... 50
3.5.3. Reference Design for Power Supply .............................................................................. 51
3.5.4. Monitor the Power Supply .............................................................................................. 52
3.6. Turn on and Turn off ................................................................................................................ 52
3.6.1. Turn on ........................................................................................................................... 52
3.6.1.1. Turn on with PWRKEY......................................................................................... 52
3.6.1.2. Turn on with PON_1 ............................................................................................ 54
3.6.2. Turn off ........................................................................................................................... 54
3.6.2.1. Turn off with PWRKEY......................................................................................... 55
3.6.2.2. Turn off with AT Command .................................................................................. 55
3.7. Reset........................................................................................................................................ 55
3.8. (U)SIM Interfaces..................................................................................................................... 57
3.9. USB Interface .......................................................................................................................... 59
3.10. UART Interfaces ...................................................................................................................... 62
3.11. I2S and I2C Interfaces .......................................................................................................... 64

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3.12. ADC Interface .......................................................................................................................... 65

3.13. Network Status Indication ........................................................................................................ 66
3.14. STATUS ................................................................................................................................... 67
3.15. Behaviors of the RI* ................................................................................................................. 68
3.16. PCIe Interface .......................................................................................................................... 68
3.17. WWAN/WLAN Control Interface* ............................................................................................ 71
3.18. Bluetooth Interface* ................................................................................................................. 72
3.19. IPQ807x Status and Err Fatal Interfaces* ............................................................................... 73
3.20. SD Card Interface .................................................................................................................... 74
3.21. Antenna Tuner Control Interface*............................................................................................ 77
3.22. SPI Interface ............................................................................................................................ 77
3.23. USB_BOOT Interface .............................................................................................................. 78
3.24. RGMII Interface ....................................................................................................................... 79
3.25. Time Service and Repeater Interface* .................................................................................... 83

4 GNSS ................................................................................................................................................... 85
4.1. General Description ................................................................................................................. 85
4.2. GNSS Performance ................................................................................................................. 85

5 Antenna Interfaces............................................................................................................................. 87
5.1. Cellular Antenna Interfaces & Frequency Bands .................................................................... 87
5.1.1. Pin Definition .................................................................................................................. 87
5.1.2. Cellular Antenna Mapping .............................................................................................. 90
5.1.3. Operating Frequency ..................................................................................................... 93
5.1.4. Reference Design of Cellular Antenna Interface ........................................................... 95
5.2. GNSS Antenna Interfaces & Frequency Bands ...................................................................... 96
5.3. RF Routing Guidelines ............................................................................................................ 97
5.4. Antenna Installation ................................................................................................................. 99
5.4.1. Antenna Design Requirement ........................................................................................ 99
5.4.2. RF Connector Recommendation ................................................................................. 100
5.4.3. Recommended RF Connector for Installation ............................................................. 101
5.4.3.1. Assemble Coaxial Cable Plug Manually ............................................................ 101
5.4.3.2. Assemble Coaxial Cable Plug with Fixture ........................................................ 102
5.4.4. Recommended Manufacturers of RF Connector and Cable ....................................... 102

6 Reliability, Radio and Electrical Characteristics .......................................................................... 103

6.1. Absolute Maximum Ratings ................................................................................................... 103
6.2. Power Supply Ratings ........................................................................................................... 103
6.3. Operating and Storage Temperatures .................................................................................. 104
6.4. Power Consumption .............................................................................................................. 104
6.5. Tx Power ................................................................................................................................ 112
6.6. Rx Sensitivity ......................................................................................................................... 113
6.7. ESD........................................................................................................................................ 117

7 Mechanical Information ................................................................................................................... 118

7.1. Mechanical Dimensions......................................................................................................... 118

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7.2. Recommended Footprint ....................................................................................................... 120

7.3. Top and Bottom Views .......................................................................................................... 121

8 Storage, Manufacturing and Packaging ........................................................................................ 122

8.1. Storage Conditions ................................................................................................................ 122
8.2. Manufacturing and Soldering ................................................................................................ 123
8.3. Packaging Specification ........................................................................................................ 124
8.3.1. Carrier Tape ................................................................................................................. 124
8.3.2. Plastic Reel .................................................................................................................. 125
8.3.3. Packaging Process ...................................................................................................... 126

9 Appendix References ...................................................................................................................... 127

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Table Index

Table 1: Applicable Modules ...................................................................................................................... 14

Table 2: Special Marks ............................................................................................................................... 15
Table 3: Frequency Bands of RG500Q-EA/RG502Q-EA .......................................................................... 16
Table 4: Frequency Bands of RG500Q-CN ............................................................................................... 16
Table 5: Frequency Bands of RG501Q-EU/RG502Q-EU.......................................................................... 17
Table 6: Key Features of RG50xQ Series Module .................................................................................... 17
Table 7: I/O Parameters Definition ............................................................................................................. 29
Table 8: Pin Description ............................................................................................................................. 29
Table 9: Overview of Operating Modes ..................................................................................................... 45
Table 10: VBAT and GND Pins .................................................................................................................. 50
Table 11: Pin Definition of PWRKEY ......................................................................................................... 52
Table 12: Pin Definition of PON_1 ............................................................................................................. 54
Table 13: Pin Definition of RESET_N ........................................................................................................ 56
Table 14: Pin Definition of (U)SIM Interfaces ............................................................................................ 57
Table 15: Pin Definition of USB Interface .................................................................................................. 59
Table 16: USB Trace Length in RG500Q-CN ............................................................................................ 61
Table 17: USB Trace Length in RG501Q-EU and RG502Q-EU ............................................................... 61
Table 18: USB Trace Length in RG500Q-EA and RG502Q-EA ................................................................ 62
Table 19: Pin Definition of UART Interfaces .............................................................................................. 62
Table 20: Pin Definition of I2S and I2C Interfaces ..................................................................................... 65
Table 21: Pin Definition of ADC Interface .................................................................................................. 66
Table 22: Characteristics of ADC Interface ............................................................................................... 66
Table 23: Pin Definition of Network Connection Status/Activity Indicator ................................................. 66
Table 24: Working State of the Network Connection Status/Activity Indicator .......................................... 66
Table 25: Pin Definition of STATUS........................................................................................................... 67
Table 26: Default Behaviors of the RI ........................................................................................................ 68
Table 27: Pin Definition of PCIe Interface .................................................................................................. 69
Table 28: PCIe Trace Length in RG500Q-CN ........................................................................................... 70
Table 29: PCIe Trace Length in RG501Q-EU and RG502Q-EU............................................................... 70
Table 30: PCIe Trace Length in RG500Q-EA and RG502Q-EA ............................................................... 71
Table 31: Pin Definition of WWAN/WLAN Control Interface...................................................................... 71
Table 32: Pin Definition of the Bluetooth Interface .................................................................................... 73
Table 33: Pin Definition of IPQ807x Status and Err Fatal Interfaces ........................................................ 73
Table 34: Pin Definition of SD Card Interface ............................................................................................ 74
Table 35: SDC Trace Length in RG500Q-CN............................................................................................ 76
Table 36: SDC Trace Length in RG501Q-EU and RG502Q-EU ............................................................... 76
Table 37: SDC Trace Length in RG500Q-EA and RG502Q-EA ............................................................... 77
Table 38: Pin Definition of GRFC Interface Used to Control Antenna Tuner ............................................ 77
Table 39: Pin Definition of SPI Interface .................................................................................................... 77
Table 40: Pin Definition of USB_BOOT Interface ...................................................................................... 78
Table 41: Pin Definition of RGMII Interface ............................................................................................... 79

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Table 42: RGMII Trace Length in RG500Q-CN ......................................................................................... 82

Table 43: RGMII Trace Length in RG501Q-EU and RG502Q-EU ............................................................ 82
Table 44: RGMII Trace Length in RG500Q-EA and RG502Q-EA............................................................. 83
Table 45: Pin Definition of Time Service and Repeater Function.............................................................. 84
Table 46: GNSS Performance ................................................................................................................... 85
Table 47: Pin Definition of Cellular Antenna Interfaces for RG500Q-EA/RG502Q-EA ............................. 87
Table 48: Pin Definition of Cellular Antenna Interfaces for RG500Q-CN .................................................. 88
Table 49: Pin Definition of Cellular Antenna Interfaces for RG501Q-EU/RG502Q-EU ............................ 89
Table 50: RG500Q-EA/RG502Q-EA Cellular Antenna Mapping ............................................................... 90
Table 51: RG500Q-CN Cellular Antenna Mapping .................................................................................... 91
Table 52: RG501Q-EU/RG502Q-EU Cellular Antenna Mapping .............................................................. 92
Table 53: RG500Q-EA/RG502Q-EA Module Operating Frequencies....................................................... 93
Table 54: RG500Q-CN Module Operating Frequencies............................................................................ 94
Table 55: RG501Q-EU/RG502Q-EU Module Operating Frequencies ...................................................... 94
Table 56: Pin Definition of GNSS Antenna Interface ................................................................................. 96
Table 57: GNSS Frequency ....................................................................................................................... 96
Table 58: Antenna Requirements .............................................................................................................. 99
Table 59: Absolute Maximum Ratings ..................................................................................................... 103
Table 60: Module Power Supply Ratings ................................................................................................. 103
Table 61: Operating and Storage Temperatures ..................................................................................... 104
Table 62: RG500Q-EA/RG502Q-EA Current Consumption .................................................................... 104
Table 63: RG500Q-CN Current Consumption ......................................................................................... 107
Table 64: RG501Q-EU/RG502Q-EU Current Consumption.................................................................... 110
Table 65: RF Output Power ..................................................................................................................... 112
Table 66: RG500Q-EA/RG502Q-EA Conducted RF Receiving Sensitivity............................................. 113
Table 67: RG500Q-CN Conducted RF Receiving Sensitivity .................................................................. 114
Table 68: RG501Q-EU/RG502Q-EU Conducted RF Receiving Sensitivity ............................................ 115
Table 69: Electrostatic Discharge Characteristics ................................................................................... 117
Table 70: Recommended Thermal Profile Parameters ........................................................................... 124
Table 71: Carrier Tape Dimension Table (Unit: mm) ............................................................................... 125
Table 72: Plastic Reel Dimension Table (Unit: mm) ................................................................................ 125
Table 73: Related Documents.................................................................................................................. 127
Table 74: Terms and Abbreviations ......................................................................................................... 127

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Figure Index

Figure 1: 8-Antenna Modules Functional Diagram .................................................................................... 22

Figure 2: 4-Antenna Modules Functional Diagram .................................................................................... 23
Figure 3: 6-Antenna Modules Functional Diagram .................................................................................... 24
Figure 4: 8-Antenna Module Pin Assignment (Top View).......................................................................... 26
Figure 5: 4-Antenna Module Pin Assignment (Top View).......................................................................... 27
Figure 6: 6-Antenna Module Pin Assignment (Top View).......................................................................... 28
Figure 7: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 46
Figure 8: Sleep Mode Application via UART ............................................................................................. 46
Figure 9: Sleep Mode Application with USB Remote Wakeup .................................................................. 47
Figure 10: Sleep Mode Application with RI ................................................................................................ 48
Figure 11: Sleep Mode Application without Suspend Function ................................................................. 48
Figure 12: Power Supply Limits during Burst Transmission ...................................................................... 50
Figure 13: Star Structure of Power Supply ................................................................................................ 51
Figure 14: Reference Circuit of Power Supply........................................................................................... 52
Figure 15: Turn on the Module Using Driving Circuit ................................................................................. 53
Figure 16: Turn on the Module Using a Button .......................................................................................... 53
Figure 17: Timing of Turning on the Module .............................................................................................. 54
Figure 18: Timing of Turning off the Module .............................................................................................. 55
Figure 19: Reference Circuit of RESET_N by Using Driving Circuit ......................................................... 56
Figure 20: Timing of Resetting the Module ................................................................................................ 56
Figure 21: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ......................... 58
Figure 22: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector ........................... 58
Figure 23: Reference Circuit of USB Application ....................................................................................... 60
Figure 24: Reference Circuit with Translator Chip ..................................................................................... 63
Figure 25: Reference Circuit with Transistor Circuit .................................................................................. 64
Figure 26: Reference Circuit of I2S Application with Audio Codec ........................................................... 65
Figure 27: Reference Circuit of the Network Indicator ............................................................................... 67
Figure 28: Reference Circuits of STATUS ................................................................................................. 68
Figure 29: RG50xQ Series Module with IPQ807x GPIO Application ........................................................ 74
Figure 30: Reference Circuit of SD Card Application ................................................................................ 75
Figure 31: SPI Interface Reference Circuit with a Level Shifter ................................................................ 78
Figure 32: Reference Circuit of USB_BOOT Interface .............................................................................. 79
Figure 33: Reference Circuit of MAC to PHY Interface ............................................................................. 80
Figure 34: Reference Circuit of MAC to MAC Interface ............................................................................. 81
Figure 35: Reference Circuit of RF Antenna.............................................................................................. 95
Figure 36: Reference Circuit of GNSS Antenna ........................................................................................ 97
Figure 37: Microstrip Line Design on a 2-layer PCB ................................................................................. 98
Figure 38: Coplanar Waveguide Line Design on a 2-layer PCB ............................................................... 98
Figure 39: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) ............ 98
Figure 40: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) ............ 99
Figure 41: Dimensions of the Receptacles (Unit: mm) ............................................................................ 100

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Figure 42: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables (Unit: mm) ........................ 101
Figure 43: Plug in a Coaxial Cable Plug .................................................................................................. 101
Figure 44: Pull out a Coaxial Cable Plug ................................................................................................. 102
Figure 45: Install the Coaxial Cable Plug with Fixture ............................................................................. 102
Figure 46: Module Top and Side Dimensions.......................................................................................... 118
Figure 47: Module Bottom Dimensions (Bottom View) ............................................................................ 119
Figure 48: Recommended Footprint ........................................................................................................ 120
Figure 49: Top and Bottom Views of the Module..................................................................................... 121
Figure 50: Recommended Reflow Soldering Thermal Profile ................................................................. 123
Figure 51: Carrier Tape Dimension Drawing ........................................................................................... 125
Figure 52: Carrier Tape Dimension Drawing ........................................................................................... 125
Figure 53: Packaging Process ................................................................................................................. 126

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 5G Module Series

1 Introduction
This document defines RG50xQ series module and describes its air interface and hardware interfaces
which are connected with your applications.

With this document, you can quickly understand module interface specifications, electrical and
mechanical details, as well as other related information of the module. The document, coupled with
application notes and user guides, makes it easy to design and set up mobile applications with the
module.

Table 1: Applicable Modules

Module Series Module

RG500Q-EA
RG500Q
RG500Q-CN

RG501Q RG501Q-EU

RG502Q-EA
RG502Q
RG502Q-EU

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1.1. Special Marks

Table 2: Special Marks

Mark Definition

Unless otherwise specified, when an asterisk (*) is used after a function, feature, interface,
pin name, AT command or argument, it indicates that the function, feature, interface, pin,
*
AT command, or argument is under development and currently not supported; and the
asterisk (*) after a model indicates that the sample of such model is currently unavailable.
Brackets ([…]) used after a pin enclosing a range of numbers indicate all pin of the same
[…] type. For example, SDC1_DATA_[0:3] refers to all four pins, SDC1_DATA_0,
SDC1_DATA_1, SDC1_DATA_2 and SDC1_DATA_3.

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2 Product Overview
2.1. General Description

RG50xQ series is a 5G NR/LTE-FDD/LTE-TDD/WCDMA wireless communication module, which

provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA,
HSUPA, and WCDMA networks. It also provides GNSS to meet your specific application demands.
RG50xQ series is an industrial-grade module for industrial and commercial applications only.

The following tables show the supported frequency bands of RG500Q-EA, RG502Q-EA, RG500Q-CN,
RG501Q-EU and RG502Q-EU. For CA and EN-DC configurations, see document [1].

Table 3: Frequency Bands of RG500Q-EA/RG502Q-EA

Mode Frequency Bands

5G NR NSA n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n77/n78/n79

5G NR SA n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n77/n78/n79

LTE-FDD B1/B3/B5/B7/B8/B18/B19/B20/B26/B28/B32

LTE-TDD B34/B38/B39/B40/B41/B42/B43

WCDMA B1/B3/B5/B6/B8/B19

GNSS GPS/GLONASS/BeiDou/Galileo/QZSS

Table 4: Frequency Bands of RG500Q-CN

Mode Frequency Bands

5G NR NSA n41/n78/n79

5G NR SA n1/n28/n41/n78/n79

RG50xQ_Series_Hardware_Design 16 / 131
 5G Module Series

LTE-FDD B1/B3/B5/B8

LTE-TDD B34/B38/B39/B40/B41

WCDMA B1/B8

GNSS GPS/GLONASS/BeiDou/Galileo/QZSS

Table 5: Frequency Bands of RG501Q-EU/RG502Q-EU

Mode Frequency Bands

5G NR NSA n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n77/n78

5G NR SA n1/n3/n5/n7/n8/n20/n28/n38/n40/n41/n77/n78

LTE-FDD B1/B3/B5/B7/B8/B20/B28/B32

LTE-TDD B38/B40/B41/B42/B43

WCDMA B1/B5/B8

GNSS GPS/GLONASS/BeiDou/Galileo/QZSS

With a compact profile of 44.0 mm × 41.0 mm × 2.75 mm, the module can meet almost all requirements
for M2M applications such as business router, home gateway, STB, industrial laptop, consumer laptop,
industrial PDA, rugged tablet PC, video surveillance, etc.

RG50xQ series is an SMD type module which can be embedded in applications through its 392 LGA pins.

2.2. Key Features

The following table describes the detailed features of RG50xQ series.

Table 6: Key Features of RG50xQ Series Module

Features Details

⚫ Supply voltage range: 3.3–4.3 V

Power Supply
⚫ Typical supply voltage: 3.8 V
⚫ Class 3 (24 dBm +1/-3 dB) for WCDMA bands
Transmitting Power
⚫ Class 3 (23 dBm ±2 dB) for LTE bands

RG50xQ_Series_Hardware_Design 17 / 131
 5G Module Series

⚫ Class 3 (23 dBm ±2 dB) for 5G NR bands

⚫ Class 2 (26 dBm ±2 dB) for LTE bands:
- RG50xQ-EA: B38/B40/B41/B42/B43 HPUE 1

- RG500Q-CN: LTE HPUE is not supported

- RG50xQ-EU: B42 HPUE 1
⚫ Class 2 (26 dBm +2/-3 dB) for 5G NR bands:
- RG50xQ-EA: n41/n77/n78/n79 HPUE 1
- RG500Q-CN: n41/n78/n79 HPUE 1
- RG50xQ-EU: n41/n77/n78 HPUE 1
⚫ Supports 3GPP Rel-15
⚫ Supported modulations:
Uplink: π/2-BPSK, QPSK, 16QAM, 64QAM and 256QAM
Downlink: QPSK, 16QAM, 64QAM and 256QAM
⚫ Supported MIMO:
Uplink: 2 × 2 MIMO* 2
-
RG50xQ-EA: n41/n77/n78/n79
- RG500Q-CN: n41/n78/n79
- RG50xQ-EU: n41/n77/n78
Downlink: 4 × 4 MIMO
- RG50xQ-EA: n1/n3/n7/n38/n40/n41/n77/n78/n79
- RG500Q-CN: n1/n41/n78/n79
- RG50xQ-EU: n1/n3/n5 3/n7/n20 3/n28 3/n38/n40/n41/n77/n78
⚫ Supports SCS 15 kHz 4 and 30 kHz 4
5G NR Features
⚫ Supports SA and NSA operation modes 5
⚫ Supports Option 3x, 3a, 3 and Option 2
⚫ Max. transmission data rates 6:
RG500Q-EA:
NSA: 2.5 Gbps (DL)/650/600 Mbps 7 (UL)
SA: 2.1 Gbps (DL)/900 Mbps (UL)
RG501Q-EU:
NSA: 3.3 Gbps (DL)/650/600 Mbps 7 (UL)
SA: 2.1 Gbps (DL)/900 Mbps (UL)
RG500Q-CN：
NSA: 2.5 Gbps (DL)/550/525 Mbps 7 (UL)
SA: 2.1 Gbps (DL)/900 Mbps (UL)
RG502Q-EA:
NSA: 5.0 Gbps (DL)/650/600 Mbps 7 (UL)

1 HPUE only supports single carrier.

2 Uplink 2 × 2 MIMO is only supported in 5G SA mode.
3 Optional.
4 5G NR FDD bands only support 15 kHz SCS, and NR TDD bands only support 30 kHz SCS.
5 See document [1] for bandwidth supported by each frequency band in the NSA and SA modes.
6
The maximum rates are theoretical and the actual values refer to the network configuration.
7 650 Mbps/550 Mbps is the theoretical value which is based on simutaneously enabling LTE UL 256QAM & 5G NR UL

256QAM, the LTE UL 256QAM in ENDC is disabled by default as it is not fully tested as well as there are no operators
deploying it; 600 Mbps/525 Mbps is a typical value.

RG50xQ_Series_Hardware_Design 18 / 131
 5G Module Series

SA: 4.2 Gbps (DL)/900 Mbps (UL)

RG502Q-EU:
NSA: 5.0 Gbps (DL)/650/600 Mbps 7 (UL)
SA: 4.2 Gbps (DL)/900 Mbps (UL)
⚫ Supports 3GPP Rel-15
⚫ Supports up to CA Cat 16 for RG500Q Series
Supports up to CA Cat 20 for RG502Q-EA, RG50xQ-EU
⚫ Supported modulations:
Uplink:
- RG50xQ-EA: QPSK, 16QAM, 64QAM and 256QAM
- RG500Q-CN: QPSK, 16QAM, 64QAM and 256QAM*
- RG50xQ-EU: QPSK, 16QAM, 64QAM and 256QAM*
Downlink: QPSK, 16QAM, 64QAM and 256QAM
⚫ Supports 1.4/3/5/10/15/20 MHz RF bandwidth
Supports DL 4 × 4 MIMO
LTE Features - RG50xQ-EA: B1/B3/B7/B32/B34/B38/B39/B40/B41/B42/B43
- RG500Q-CN: B1/B41
- RG50xQ-EU: B1/B3/B5 3/B7/B20 3/B28 3/B32/B38/B40/B41/B42/B43
⚫ Max. transmission data rates 6:
RG500Q-EA:
LTE: 1.0 Gbps (DL)/200 Mbps (UL)
RG502Q-EA:
LTE: 2.0 Gbps (DL)/200 Mbps (UL)
RG50xQ-EU:
LTE: 2.0 Gbps (DL)/200 Mbps (UL)
RG500Q-CN:
LTE: 800 Mbps (DL)/200 Mbps (UL)
⚫ Supports 3GPP Rel-9 DC-HSDPA, HSPA+, HSDPA, HSUPA and
WCDMA
⚫ Supports QPSK, 16QAM and 64QAM modulations
UMTS Features ⚫ Max. transmission data rates 6:
DC-HSDPA: 42 Mbps
HSUPA: 5.76 Mbps
WCDMA: 384 kbps (DL)/384 kbps (UL)
Internet Protocol ⚫ Supports QMI/TCP*/UDP*/FTP*/HTTP*/NTP*/PING*/HTTPS*/SMTP*/
Features MMS*/FTPS*/SMTPS*/SSL* protocols
⚫ Text and PDU modes
⚫ Point-to-point MO and MT
SMS
⚫ SMS cell broadcast
⚫ SMS storage: ME by default

(U)SIM Interfaces ⚫ Supports SIM/USIM cards: 1.8/2.95 V

RG50xQ_Series_Hardware_Design 19 / 131
 5G Module Series

⚫ Supports two digital audio interfaces: PCM* and I2S 8

⚫ WCDMA: AMR/AMR-WB
Audio Features
⚫ LTE: AMR/AMR-WB
⚫ Supports echo cancellation and noise suppression
⚫ Supports 16-bit linear data format
⚫ Supports long frame synchronization and short frame synchronization
PCM Interface*
⚫ Supports master and slave modes, but must be in master mode for long
frame synchronization
⚫ Supports 16-bit linear data format
⚫ I2S is commonly used as a 4-wire DAI (I2S_MCLK is not used in the
design normally) in Hi-Fi, STB and portable devices
⚫ The Tx and Rx lines are used for audio transmission, while the bit clock
I2S Interface 8
and left/right clock synchronize the link
⚫ I2S in either controller or codec state is able to drive (master) the bit clock
and left/right clock lines
⚫ Can be multiplexed into PCM function
⚫ Compliant with USB 3.1 and 2.0 specifications, with maximum
transmission rates up to 10 Gbps on USB 3.1 and 480 Mbps on USB 2.0
⚫ Used for AT command communication, data transmission, GNSS NMEA
USB Interface
sentence output, software debugging and firmware upgrade
⚫ Supported USB serial drivers for: Windows 7/8/8.1/10, Linux 2.6–5.12,
Android 4.x–11.x
⚫ Main UART:
Used for AT command communication
Baud rate: 115200 bps by default
Supports RTS and CTS hardware flow control
⚫ Debug UART:
Used for Linux console and log output
UART Interfaces
Baud rate: 115200 bps
⚫ Bluetooth UART*:
Used for Bluetooth communication
Baud rate: 115200 bps
⚫ COEX UART*:
Used for WWAN/WLAN coexistence mechanism
⚫ Compliant with PCI Express Specification Revision 3.0
PCIe Interface ⚫ Supports 2 lanes, 8 Gbps/lane
⚫ Can be used to connect an external WLAN IC
⚫ RG500Q-EA and RG502Q-EA: Not supported
eSIM
⚫ RG500Q-CN and RG50xQ-EU: Optional
⚫ Supports dual-band GNSS: L1 and L5
GNSS Features ⚫ Protocol: NMEA 0183
⚫ Data update rate: 1 Hz

8 I2S interface is under development, but it is multiplexed into PCM interface by default currently.

RG50xQ_Series_Hardware_Design 20 / 131
 5G Module Series

Antenna Tuner Control

⚫ GRFC interface dedicated for external antenna tuner
Interface
⚫ Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT
AT Commands
commands
⚫ Two pins NET_MODE* and NET_STATUS to indicate network
Network Indication
connectivity status
⚫ Cellular antenna interfaces:
- RG50xQ-EA: eight cellular antenna interfaces (ANT0–ANT7)
- RG500Q-CN: four cellular antenna interfaces (ANT0–ANT3)
Antenna Interfaces - RG50xQ-EU: six cellular antenna interfaces (ANT0–ANT5)
⚫ GNSS antenna interface:
- One GNSS antenna interface (ANT_GNSS)
⚫ Supports 5G NR/LTE/WCDMA Rx-diversity
⚫ Size: (44.0 ±0.15) mm × (41.0 ±0.15) mm × (2.75 ±0.20) mm
Physical
⚫ Package: LGA
Characteristics
⚫ Weight: approx.11 g
⚫ Operating temperature range: -30 to +75 °C 9
Operating
⚫ Extended temperature range: -40 to +85 °C 10
Temperature
⚫ Storage temperature range: -40 to +90 °C

Firmware Upgrade ⚫ Via USB 2.0 or DFOTA

RoHS ⚫ All hardware components are fully compliant with EU RoHS directive

2.3. Functional Diagram

The following figure shows a block diagram of RG50xQ series module and illustrates the major functional
parts.

⚫ Power management
⚫ Baseband
⚫ DDR + NAND flash
⚫ Radio frequency
⚫ Peripheral interfaces

9 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding
passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications.
10 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding

passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish
and maintain functions such as voice, SMS, emergency call, etc., without any unrecoverable malfunction. Radio spectrum
and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value,
exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the
module will meet 3GPP specifications again.

RG50xQ_Series_Hardware_Design 21 / 131
 5G Module Series

ANT_GNSS
ANT4
ANT3

ANT7
ANT5
ANT0

ANT1

ANT2

ANT6
VBAT_RF

QET Tx/Rx Blocks

MIPI&GRFC
GNSS
DRx
PRx
Tx

NAND
Transceiver LPDDR4X
SDRAM
RFCLK
38.4 MHz

QLINK Control

VBAT_BB
PMIC BBCLK(19.2 MHz)
32 kHz
PMU
PWRKEY I2S

RESET_N 38.4 MHz SPI

XO
Baseband VDD_WIFI_VL
ADC SPMI
Sleep CLK(32 kHz) VDD_WIFI_VM
STATUS VDD_WIFI_VH

VDD_EXT USB 2.0/3.1 (U)SIM RGMII PCM PCIe I2C UART SD Card
3.0

Figure 1: 8-Antenna Modules Functional Diagram

RG50xQ_Series_Hardware_Design 22 / 131
 5G Module Series

ANT_GNSS
ANT1

ANT3
ANT0

ANT2
VBAT_RF

QET Tx/Rx Blocks

MIPI&GRFC
GNSS
DRx
PRx
Tx

NAND
Transceiver LPDDR4X
SDRAM
RFCLK
38.4 MHz

QLINK Control

VBAT_BB
PMIC BBCLK(19.2 MHz)
32 kHz
PMU
PWRKEY
I2S

RESET_N 38.4 MHz SPI

XO
Baseband VDD_WIFI_VL
ADC SPMI
Sleep CLK(32 kHz) VDD_WIFI_VM
STATUS VDD_WIFI_VH

eSIM

VDD_EXT USB 2.0/3.1 (U)SIM RGMII PCM PCIe I2C UART SD Card
3.0

Figure 2: 4-Antenna Modules Functional Diagram

RG50xQ_Series_Hardware_Design 23 / 131
 5G Module Series

ANT_GNSS
ANT1

ANT3
ANT0

ANT2
ANT4

ANT5
VBAT_RF

QET Tx/Rx Blocks

MIPI&GRFC
GNSS
DRx
PRx
Tx

NAND
Transceiver LPDDR4X
SDRAM
RFCLK
38.4 MHz

QLINK Control

VBAT_BB
PMIC BBCLK(19.2 MHz)
32 kHz
PMU
PWRKEY
I2S
RESET_N 38.4 MHz SPI
XO
Baseband VDD_WIFI_VL
ADC SPMI
Sleep CLK(32 kHz) VDD_WIFI_VM
STATUS VDD_WIFI_VH

eSIM

VDD_EXT USB 2.0/3.1 (U)SIM RGMII PCM PCIe I2C UART SD Card
3.0

Figure 3: 6-Antenna Modules Functional Diagram

NOTE

1. RG500Q-EA and RG502Q-EA have 8 antenna interfaces.

2. RG500Q-CN has 4 antenna interfaces.
3. RG501Q-EU and RG502Q-EU have 6 antenna interfaces. ANT4 and ANT5 are used for 1A-3A-32A
CA, if there is no need for this CA, ANT4 and ANT5 can be removed.

2.4. EVB

To help you develop applications with the module, Quectel supplies the evaluation board (5G EVB), USB
to RS-232 converter cable, earphone, antenna and other peripherals to control or test the module. For
more details, see document [2].

RG50xQ_Series_Hardware_Design 24 / 131
 5G Module Series

3 Application Interfaces
RG50xQ series module is equipped with 392 LGA pins that can be connected to cellular application
platform. The following interfaces are described in detail in subsequent chapters:

⚫ Power supply
⚫ (U)SIM interfaces
⚫ USB 2.0/3.1 interface
⚫ UART interfaces
⚫ I2S 11 and I2C interfaces
⚫ ADC interface
⚫ Network status indication
⚫ STATUS
⚫ PCIe interface
⚫ WWAN/WLAN control interface*
⚫ Bluetooth interface*
⚫ IPQ807x Status and Err Fatal Interfaces*
⚫ SD card interface
⚫ Antenna Tuner Control Interface*
⚫ SPI interface
⚫ USB_BOOT Interface
⚫ RGMII interface
⚫ Time Service and Repeater Interface*

11 I2S interface is under development, but it is multiplexed into PCM interface by default currently.

RG50xQ_Series_Hardware_Design 25 / 131
 5G Module Series

3.1. Pin Assignment

The following figure shows the pin assignment of the module.

ANT_GNSS
195

193

190

187

184

181

178

175

172

169

166

163

160

157

154

151

148

145

142

139

136

133
ANT7

ANT6

ANT5

ANT4

ANT3

ANT2
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
392

391
GND

GND
194

191

188

185

182

179

176

173

170

167

164

161

158

155

152

149

146

143

140

137

134
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
HST_LAA_TX_EN
HST_WL_TX_EN
WL_SW_CTRL

WL_LAA_AS_EN
WLAN_PA_MUTING
SDR_GRFC14

SDR_GRFC15
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135
GND

GND

GND

GND

GND
196 132
GND GND

197 131
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
298

297

296

295

294

293

292

291

290

289

288

287

286

285

284

283

282
GND GND

199 198 129 130

RESERVED RESERVED GND ANT1

200 128
GND GND

202 201 126 127

GND WL_LAA_RX GND GND

203 125
GND GND

205 204 123 124

GND SPI1_MOSI GND GND

206 299 300 301 302 303 304 305 306 307 122
GND GND GND GND GND GND GND GND GND
GND GND

208 207 120 121

RESERVED SPI1_CS RESERVED ANT0

209 119
GND GND

211 210 117 118

SPI1_CLK RESERVED
GND
308 309 310 311 312 313 314 315 316 GND

GND GND GND GND GND GND GND GND GND

212 116
GND GND

214 213 114 115

GND SPI1_MISO W_DISABLE GND

215 113
GND GND

217 216 317 318 319 320 321 322 323 324 325 111 112
RESERVED WLAN_PWR_EN1 RESERVED VBAT_RF2
GND GND GND GND GND GND GND GND GND

218 110
RESERVED VBAT_RF2

220 219 108 109

RESERVED WLAN_PWR_EN2 DBG_RXD VBAT_RF2

221 107
RESERVED VBAT_RF2
326 327 328 329 330 331 332 333 334
223 222 GND GND GND GND GND GND GND GND GND 105 106
RESERVED WLAN_EN DBG_TXD RESERVED

224 104
GND RESERVED

226 225 102 103

GND WLAN_SLP_CLK SLEEP_IND RESERVED

227 335 336 337 338 339 340 341 342 343 101
GND RESERVED
GND GND GND GND GND GND GND GND GND

229 228 99 100

VBAT_RF1 GND RESERVED UART1_RI

230 98
VBAT_RF1 GPIO_32

232 231 96 97
VBAT_RF1 GND GND RESERVED

233 344 345 346 347 348 349 350 351 352 95
GND GND GND GND GND GND GND GND GND
VBAT_RF1 RESERVED

235 234 93 94
GND RESERVED
VBAT_BB RESERVED

236 92
VBAT_BB RESERVED

238 237 90 91
VBAT_BB
STATUS
353 354 355 356 357 358 359 360 361 GND
USB_SS_TX_P
GND GND GND GND GND GND GND GND GND
239 89
RESERVED USB_SS_TX_M

241 240 87 88
NET_MODE RESERVED
ADC0 USB_SS_RX_P

242 86
PON_1 USB_SS_RX_M

244 243 362 363 364 365 366 367 368 369 370 84 85
NET_STATUS GND GND GND GND GND GND GND GND GND GND
USIM1_RST USB_DM

245 83
USIM1_VDD USB_DP

247 246 81 82
RF_CLK3_WL USB_BOOT
USIM1_CLK USB_VBUS

248 80
USIM1_DATA RESERVED
371 372 373 374 375 376 377 378 379
250 249 GND GND GND GND GND GND GND GND GND 78 79
USIM1_DET I2C1_SDA
USIM2_VDD I2S_MCLK

251 77
USIM2_DATA I2C1_SCL

253 252 75 76
USIM2_DET EXT_RST
USIM2_CLK PCM_OUT

254 380 381 382 383 384 385 386 387 388 74
USIM2_RST PCM_IN
GND GND GND GND GND GND GND GND GND

256 255 72 73
I2S_DOUT UART1_RTS
I2S_SCK PCM_CLK

257 71
I2S_DIN PCM_SYNC

259 258 69 70
UART1_DTR UART1_CTS
I2S_WS UART1_RXD

260 68
RESERVED UART1_TXD

262 261 66 67
SDX_TO_WL_CTI
VDD_WIFI_VM

VDD_WIFI_VH
VDD_WIFI_VL

VDD_WIFI_VL

WL_TO_SDX
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

EXT_INT

UART1_DCD VDD_EXT
265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

RESERVED COEX_UART_TXD

263 65
RESERVED COEX_UART_RXD

264 64
RESERVED BT_EN
RGMII_PWR_EN
RGMII_CTL_RX

PCIE_CLKREQ

SDC1_DATA_2
RGMII_CTL_TX

RGMII_CK_TX

PCIE_WAKE
RESERVED

RESERVED

RESERVED

RESERVED

SDC1_CMD

RESERVED

RESERVED

SDIO_VDD
PCIE_RST
12

15

18

21

24

27

30

33

36

39

42

45

48

51

54

57

60
GND

GND

GND

GND
3

SDC1_PWR_VSET
SDC1_PWR_EN

BT_UART_TXD

BT_UART_CTS
RGMII_MD_CLK

PCIE_REFCLK_M
PCIE_RX0_M

PCIE_RX1_M

SDC1_DATA_1
PCIE_TX1_M

PCIE_TX0_M
RGMII_RX_1

RGMII_RX_3

RGMII_TX_0

RGMII_TX_2
RESERVED

RESERVED

SDC1_CLK
RGMII_INT
RESET_N

11

14

17

20

23

26

29

32

35

38

41

44

47

50

53

56

59

62
GND
2

RGMII_PWR_IN

BT_UART_RXD
PCIE_REFCLK_P

SDC1_DATA_3
RGMII_CK_RX

BT_UART_RTS
RGMII_MD_IO

SDC1_DATA_0
PCIE_RX0_P

PCIE_RX1_P
RGMII_RX_0

RGMII_RX_2

PCIE_TX1_P

PCIE_TX0_P
RGMII_TX_1

RGMII_TX_3

390
RESERVED

RESERVED

RESERVED
RGMII_RST

SDC1_DET

389
PWRKEY

GND
10

13

16

19

22

25

28

31

34

37

40

43

46

49

52

55

58

61

63
1

GND

Power Pins GND Pins GPIO Pins RESERVED Pins I2C Pins
PCIe Pins PCM Pins (U)SIM Pins USB Pins JTAG Pins

ADC Pins UART Pins SPI Pins ANT Pins SDIO Pins
CTL Pins RGMII Pins GRFC&RFFE I2S Pins Wi-Fi Pins

Figure 4: 8-Antenna Module Pin Assignment (Top View)

RG50xQ_Series_Hardware_Design 26 / 131
 5G Module Series

RESERVED

RESERVED

RESERVED
ANT_GNSS
195

193

190

187

184

181

178

175

172

169

166

163

160

157

154

151

148

145

142

139

136

133
ANT3

ANT2

ANT1
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
392

391
GND

GND
194

191

188

185

182

179

176

173

170

167

164

161

158

155

152

149

146

143

140

137

134
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
HST_LAA_TX_EN
HST_WL_TX_EN
WL_SW_CTRL

WL_LAA_AS_EN
WLAN_PA_MUTING
SDR_GRFC14

SDR_GRFC15
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135
GND

GND

GND

GND

GND
196 132
GND GND

197 131

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
298

297

296

295

294

293

292

291

290

289

288

287

286

285

284

283

282
GND GND

199 198 129 130

RESERVED RESERVED GND ANT0

200 128
GND GND

202 201 126 127

GND WL_LAA_RX GND GND

203 125
GND GND

205 204 123 124

GND SPI1_MOSI GND GND

206 299 300 301 302 303 304 305 306 307 122
GND GND GND GND GND GND GND GND GND
GND GND

208 207 120 121

RESERVED SPI1_CS RESERVED RESERVED

209 119
GND GND

211 210 117 118

SPI1_CLK RESERVED
GND
308 309 310 311 312 313 314 315 316 GND

GND GND GND GND GND GND GND GND GND

212 116
GND GND

214 213 114 115

GND SPI1_MISO W_DISABLE GND

215 113
GND GND

217 216 317 318 319 320 321 322 323 324 325 111 112
RESERVED WLAN_PWR_EN1 RESERVED VBAT_RF2
GND GND GND GND GND GND GND GND GND

218 110
RESERVED VBAT_RF2

220 219 108 109

RESERVED WLAN_PWR_EN2 DBG_RXD VBAT_RF2

221 107
RESERVED VBAT_RF2
326 327 328 329 330 331 332 333 334
223 222 GND GND GND GND GND GND GND GND GND 105 106
RESERVED WLAN_EN DBG_TXD RESERVED

224 104
GND RESERVED

226 225 102 103

GND WLAN_SLP_CLK SLEEP_IND RESERVED

227 335 336 337 338 339 340 341 342 343 101
GND RESERVED
GND GND GND GND GND GND GND GND GND

229 228 99 100

VBAT_RF1 GND RESERVED UART1_RI

230 98
VBAT_RF1 GPIO_32

232 231 96 97
VBAT_RF1 GND GND RESERVED

233 344 345 346 347 348 349 350 351 352 95
GND GND GND GND GND GND GND GND GND
VBAT_RF1 RESERVED

235 234 93 94
GND RESERVED
VBAT_BB RESERVED

236 92
VBAT_BB RESERVED

238 237 90 91
VBAT_BB
STATUS
353 354 355 356 357 358 359 360 361 GND
USB_SS_TX_P
GND GND GND GND GND GND GND GND GND
239 89
RESERVED USB_SS_TX_M

241 240 87 88
NET_MODE RESERVED
ADC0 USB_SS_RX_P

242 86
PON_1 USB_SS_RX_M

244 243 362 363 364 365 366 367 368 369 370 84 85
NET_STATUS GND GND GND GND GND GND GND GND GND GND
USIM1_RST USB_DM

245 83
USIM1_VDD USB_DP

247 246 81 82
RF_CLK3_WL USB_BOOT
USIM1_CLK USB_VBUS

248 80
USIM1_DATA RESERVED
371 372 373 374 375 376 377 378 379
250 249 GND GND GND GND GND GND GND GND GND 78 79
USIM1_DET I2C1_SDA
USIM2_VDD I2S_MCLK

251 77
USIM2_DATA I2C1_SCL

253 252 75 76
USIM2_DET EXT_RST
USIM2_CLK PCM_OUT

254 380 381 382 383 384 385 386 387 388 74
USIM2_RST PCM_IN
GND GND GND GND GND GND GND GND GND

256 255 72 73
I2S_DOUT UART1_RTS
I2S_SCK PCM_CLK

257 71
I2S_DIN PCM_SYNC

259 258 69 70
UART1_DTR UART1_CTS
I2S_WS UART1_RXD

260 68
RESERVED UART1_TXD

262 261 66 67
SDX_TO_WL_CTI
VDD_WIFI_VM

VDD_WIFI_VH
VDD_WIFI_VL

VDD_WIFI_VL

WL_TO_SDX
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

EXT_INT

UART1_DCD VDD_EXT
265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

RESERVED COEX_UART_TXD

263 65
RESERVED COEX_UART_RXD

264 64
RESERVED BT_EN
RGMII_PWR_EN
RGMII_CTL_RX

PCIE_CLKREQ

SDC1_DATA_2
RGMII_CTL_TX

RGMII_CK_TX

PCIE_WAKE
RESERVED

RESERVED

RESERVED

RESERVED

SDC1_CMD

RESERVED

RESERVED

SDIO_VDD
PCIE_RST
12

15

18

21

24

27

30

33

36

39

42

45

48

51

54

57

60
GND

GND

GND

GND
3

SDC1_PWR_VSET
SDC1_PWR_EN

BT_UART_TXD

BT_UART_CTS
RGMII_MD_CLK

PCIE_REFCLK_M
PCIE_RX0_M

PCIE_RX1_M

SDC1_DATA_1
PCIE_TX1_M

PCIE_TX0_M
RGMII_RX_1

RGMII_RX_3

RGMII_TX_0

RGMII_TX_2
RESERVED

RESERVED

SDC1_CLK
RGMII_INT
RESET_N

11

14

17

20

23

26

29

32

35

38

41

44

47

50

53

56

59

62
GND
2

RGMII_PWR_IN

BT_UART_RXD
PCIE_REFCLK_P

SDC1_DATA_3
RGMII_CK_RX

BT_UART_RTS
RGMII_MD_IO

SDC1_DATA_0
PCIE_RX0_P

PCIE_RX1_P
RGMII_RX_0

RGMII_RX_2

PCIE_TX1_P

PCIE_TX0_P
RGMII_TX_1

RGMII_TX_3

390
RESERVED

RESERVED

RESERVED
RGMII_RST

SDC1_DET

389
PWRKEY

GND
10

13

16

19

22

25

28

31

34

37

40

43

46

49

52

55

58

61

63
1

GND

Power Pins GND Pins GPIO Pins RESERVED Pins I2C Pins
PCIe Pins PCM Pins (U)SIM Pins USB Pins JTAG Pins

ADC Pins UART Pins SPI Pins ANT Pins SDIO Pins
CTL Pins RGMII Pins GRFC&RFFE I2S Pins Wi-Fi Pins

Figure 5: 4-Antenna Module Pin Assignment (Top View)

RG50xQ_Series_Hardware_Design 27 / 131
 5G Module Series

RESERVED

RESERVED
ANT_GNSS
195

193

190

187

184

181

178

175

172

169

166

163

160

157

154

151

148

145

142

139

136

133
ANT3

ANT5

ANT2

ANT1
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
392

391
GND

GND
194

191

188

185

182

179

176

173

170

167

164

161

158

155

152

149

146

143

140

137

134
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
HST_LAA_TX_EN
HST_WL_TX_EN
WL_SW_CTRL

WL_LAA_AS_EN
WLAN_PA_MUTING
SDR_GRFC14

SDR_GRFC15
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
192

189

186

183

180

177

174

171

168

165

162

159

156

153

150

147

144

141

138

135
GND

GND

GND

GND

GND
196 132
GND GND

197 131

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED
298

297

296

295

294

293

292

291

290

289

288

287

286

285

284

283

282
GND GND

199 198 129 130

RESERVED RESERVED GND ANT0

200 128
GND GND

202 201 126 127

GND WL_LAA_RX GND GND

203 125
GND GND

205 204 123 124

GND SPI1_MOSI GND GND

206 299 300 301 302 303 304 305 306 307 122
GND GND GND GND GND GND GND GND GND
GND GND

208 207 120 121

RESERVED SPI1_CS RESERVED ANT4

209 119
GND GND

211 210 117 118

SPI1_CLK RESERVED
GND
308 309 310 311 312 313 314 315 316 GND

GND GND GND GND GND GND GND GND GND

212 116
GND GND

214 213 114 115

GND SPI1_MISO W_DISABLE GND

215 113
GND GND

217 216 317 318 319 320 321 322 323 324 325 111 112
RESERVED WLAN_PWR_EN1 RESERVED VBAT_RF2
GND GND GND GND GND GND GND GND GND

218 110
RESERVED VBAT_RF2

220 219 108 109

RESERVED WLAN_PWR_EN2 DBG_RXD VBAT_RF2

221 107
RESERVED VBAT_RF2
326 327 328 329 330 331 332 333 334
223 222 GND GND GND GND GND GND GND GND GND 105 106
RESERVED WLAN_EN DBG_TXD RESERVED

224 104
GND RESERVED

226 225 102 103

GND WLAN_SLP_CLK SLEEP_IND RESERVED

227 335 336 337 338 339 340 341 342 343 101
GND RESERVED
GND GND GND GND GND GND GND GND GND

229 228 99 100

VBAT_RF1 GND RESERVED UART1_RI

230 98
VBAT_RF1 GPIO_32

232 231 96 97
VBAT_RF1 GND GND RESERVED

233 344 345 346 347 348 349 350 351 352 95
GND GND GND GND GND GND GND GND GND
VBAT_RF1 RESERVED

235 234 93 94
GND RESERVED
VBAT_BB RESERVED

236 92
VBAT_BB RESERVED

238 237 90 91
VBAT_BB
STATUS
353 354 355 356 357 358 359 360 361 GND
USB_SS_TX_P
GND GND GND GND GND GND GND GND GND
239 89
RESERVED USB_SS_TX_M

241 240 87 88
NET_MODE RESERVED
ADC0 USB_SS_RX_P

242 86
PON_1 USB_SS_RX_M

244 243 362 363 364 365 366 367 368 369 370 84 85
NET_STATUS GND GND GND GND GND GND GND GND GND GND
USIM1_RST USB_DM

245 83
USIM1_VDD USB_DP

247 246 81 82
RF_CLK3_WL USB_BOOT
USIM1_CLK USB_VBUS

248 80
USIM1_DATA RESERVED
371 372 373 374 375 376 377 378 379
250 249 GND GND GND GND GND GND GND GND GND 78 79
USIM1_DET I2C1_SDA
USIM2_VDD I2S_MCLK

251 77
USIM2_DATA I2C1_SCL

253 252 75 76
USIM2_DET EXT_RST
USIM2_CLK PCM_OUT

254 380 381 382 383 384 385 386 387 388 74
USIM2_RST PCM_IN
GND GND GND GND GND GND GND GND GND

256 255 72 73
I2S_DOUT UART1_RTS
I2S_SCK PCM_CLK

257 71
I2S_DIN PCM_SYNC

259 258 69 70
UART1_DTR UART1_CTS
I2S_WS UART1_RXD

260 68
RESERVED UART1_TXD

262 261 66 67
SDX_TO_WL_CTI
VDD_WIFI_VM

VDD_WIFI_VH
VDD_WIFI_VL

VDD_WIFI_VL

WL_TO_SDX
RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

EXT_INT

UART1_DCD VDD_EXT
265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

RESERVED COEX_UART_TXD

263 65
RESERVED COEX_UART_RXD

264 64
RESERVED BT_EN
RGMII_PWR_EN
RGMII_CTL_RX

PCIE_CLKREQ

SDC1_DATA_2
RGMII_CTL_TX

RGMII_CK_TX

PCIE_WAKE
RESERVED

RESERVED

RESERVED

RESERVED

SDC1_CMD

RESERVED

RESERVED

SDIO_VDD
PCIE_RST
12

15

18

21

24

27

30

33

36

39

42

45

48

51

54

57

60
GND

GND

GND

GND
3

SDC1_PWR_VSET
SDC1_PWR_EN

BT_UART_TXD

BT_UART_CTS
RGMII_MD_CLK

PCIE_REFCLK_M
PCIE_RX0_M

PCIE_RX1_M

SDC1_DATA_1
PCIE_TX1_M

PCIE_TX0_M
RGMII_RX_1

RGMII_RX_3

RGMII_TX_0

RGMII_TX_2
RESERVED

RESERVED

SDC1_CLK
RGMII_INT
RESET_N

11

14

17

20

23

26

29

32

35

38

41

44

47

50

53

56

59

62
GND
2

RGMII_PWR_IN

BT_UART_RXD
PCIE_REFCLK_P

SDC1_DATA_3
RGMII_CK_RX

BT_UART_RTS
RGMII_MD_IO

SDC1_DATA_0
PCIE_RX0_P

PCIE_RX1_P
RGMII_RX_0

RGMII_RX_2

PCIE_TX1_P

PCIE_TX0_P
RGMII_TX_1

RGMII_TX_3

390
RESERVED

RESERVED

RESERVED
RGMII_RST

SDC1_DET

389
PWRKEY

GND
10

13

16

19

22

25

28

31

34

37

40

43

46

49

52

55

58

61

63
1

GND

Power Pins GND Pins GPIO Pins RESERVED Pins I2C Pins
PCIe Pins PCM Pins (U)SIM Pins USB Pins JTAG Pins

ADC Pins UART Pins SPI Pins ANT Pins SDIO Pins
CTL Pins RGMII Pins GRFC&RFFE I2S Pins Wi-Fi Pins

Figure 6: 6-Antenna Module Pin Assignment (Top View)

NOTE

1. Keep all RESERVED or unused pins unconnected (except pin 242: PON_1).
2. All GND pins should be connected to ground.

RG50xQ_Series_Hardware_Design 28 / 131
 5G Module Series

3. RG500Q-EA and RG502Q-EA have 8 antenna interfaces.

4. RG500Q-CN has 4 antenna interfaces.
5. RG501Q-EU and RG502Q-EU have 6 antenna interfaces.

3.2. Pin Description

The following tables show the pin definition and description of RG50xQ series module.

Table 7: I/O Parameters Definition

Type Description

AI Analog Input

AO Analog Output

AIO Analog Input/Output

DI Digital Input

DO Digital Output

DIO Digital Input/Output

OD Open Drain

PI Power Input

PO Power Output

Table 8: Pin Description

Power Supply

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Power supply for Vmax = 4.3 V
235, 236,
VBAT_BB PI the module’s Vmin = 3.3 V
238
baseband part Vnom = 3.8 V
Power supply for Vmax = 4.3 V
229, 230,
VBAT_RF1 PI the module’s RF Vmin = 3.3 V
232, 233
part Vnom = 3.8 V

RG50xQ_Series_Hardware_Design 29 / 131
 5G Module Series

VBAT_RF2 is only
used to connect
decoupling
Power supply for Vmax = 4.3 V
107, 109, capacitors and
VBAT_RF2 PI the module’s RF Vmin = 3.3 V
110, 112 there is no need to
part Vnom = 3.8 V
connect it to the
external power
supply.
Power supply for
Provides 1.8 V for Vnom = 1.8 V
VDD_EXT 66 PO external GPIO’s
external circuits IOmax = 50 mA
pull-up circuits.
Provides 0.95 V
Vnom = 0.95 V
VDD_WIFI_VL 266, 267 PO for Wi-Fi/Bluetooth
IOmax = 1.7 A
modules
Provides 1.28 V Vmax = 1.35 V Power supply for
VDD_WIFI_VM 268 PO for Wi-Fi/Bluetooth Vnom = 1.28 V Wi-Fi/Bluetooth
modules IOmax = 400 mA modules.
Provides 1.95 V
Vnom = 1.95 V
VDD_WIFI_VH 269 PO for Wi-Fi/Bluetooth
IOmax = 400 mA
modules

GND

Pin Name Pin No.

12, 18, 26, 33, 42, 84, 90, 96, 113, 115, 116, 118, 119, 122–129, 131–134, 136,
137, 140–147, 149, 151, 152, 154–156, 158, 160, 161, 163, 164, 167–170, 172,
GND
173, 176, 178, 179, 181, 182, 185, 187, 188, 190, 191, 194–197, 200, 202, 203,
205, 206, 209, 211, 212, 214, 215, 224, 226, 227, 228, 231, 234, 299–392

Turn on/off

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Turns on/off the Internally pulled
PWRKEY 7 DI 1.0 V high level
module up.
Pull it up to
1.8–4.3 V.
LOW to HIGH
PON_1 242 DI If unused, pull it
indicates power on
down to GND with
a 10 kΩ resistor.
VIHmax = 2.0 V
Internally pulled
RESET_N 8 DI Resets the module VIHmin = 1.2 V
up to 1.5 V.
VILmax = 0.6 V

Status Indication

RG50xQ_Series_Hardware_Design 30 / 131
 5G Module Series

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Indicates the
STATUS 237 DO module’s
operation status
Indicates the
NET_MODE* 240 DO module’s network
VOLmax = 0.45 V
registration mode 1.8 V power
VOHmin = 1.35 V
Indicates the domain.
VOHmax = 1.8 V
NET_STATUS 243 DO module’s network
activity status
Indicates the
SLEEP_IND 102 DO module’s sleep
mode

USB Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
For USB
Vmax = 5.25 V
USB connection connection
USB_VBUS 82 AI Vmin = 3.3 V
detect detection only, not
Vnom = 5.0 V
power supply.
USB differential Requires
USB_DP 83 AIO
data (+) differential
impedance of
USB differential 90 Ω.
USB_DM 85 AIO
data (-) USB 2.0
compliant.
USB 3.1
USB_SS_TX_P 91 AO super-speed
transmit (+)
USB 3.1 Requires
USB_SS_TX_M 89 AO super-speed differential
transmit (-) impedance of
USB 3.1 85 Ω.
USB_SS_RX_P 88 AI super-speed USB 3.1 Gen2
receive (+) compliant.
USB 3.1
USB_SS_RX_M 86 AI super-speed
receive (-)

(U)SIM Interfaces

RG50xQ_Series_Hardware_Design 31 / 131
 5G Module Series

DC
Pin Name Pin No. I/O Description Comment
Characteristics
IOmax = 50 mA

For 1.8 V (U)SIM:

Either 1.8 V or
Vmax = 1.9 V
2.95 V is
(U)SIM1 card Vmin = 1.7 V
USIM1_VDD 245 PO supported by the
power supply
module
For 2.95 V
automatically.
(U)SIM:
Vmax = 3.0 V
Vmin = 2.75 V
For 1.8 V (U)SIM：
VOLmax = 0.4 V
VOHmin = 1.45 V
VILmax = 0.4 V
VIHmin = 1.45 V

USIM1_DATA 248 DIO (U)SIM1 card data

For 2.95 V
(U)SIM：
VOLmax = 0.4 V
VOHmin = 2.3 V
VILmax = 0.4 V
VIHmin = 2.3 V
(U)SIM1 card For 1.8 V (U)SIM:
USIM1_CLK 247 DO
clock VOLmax = 0.4 V
VOHmin = 1.45 V

For 2.95 V
USIM1_RST 244 DO (U)SIM1 card reset
(U)SIM:
VOLmax = 0.4 V
VOHmin = 2.3 V
VILmin = -0.3 V 1.8 V power
(U)SIM1 card VILmax = 0.6 V domain.
USIM1_DET 249 DI
hot-plug detect VIHmin = 1.2 V If unused, keep it
VIHmax = 2.0 V open.

RG50xQ_Series_Hardware_Design 32 / 131
 5G Module Series

IOmax = 50 mA

For 1.8 V (U)SIM:

Either 1.8 V or
Vmax = 1.9 V
2.95 V is
(U)SIM2 card Vmin = 1.7 V
USIM2_VDD 250 PO supported by the
power supply
module
For 2.95 V
automatically.
(U)SIM:
Vmax = 3.0 V
Vmin = 2.75 V
For 1.8 V (U)SIM：
VOLmax = 0.4 V
VOHmin = 1.45 V
VILmax = 0.4 V
VIHmin = 1.45 V

USIM2_DATA 251 DIO (U)SIM2 card data

For 2.95 V
(U)SIM：
VOLmax = 0.4 V
VOHmin = 2.3 V
VILmax = 0.4 V
VIHmin = 2.3 V
(U)SIM2 card For 1.8 V (U)SIM:
USIM2_CLK 253 DO
clock VOLmax = 0.4 V
VOHmin = 1.45 V

For 2.95 V
USIM2_RST 254 DO (U)SIM2 card reset
(U)SIM:
VOLmax = 0.4 V
VOHmin = 2.3 V
VILmin = -0.3 V 1.8 V power
(U)SIM2 card VILmax = 0.6 V domain.
USIM2_DET 252 DI
hot-plug detect VIHmin = 1.2 V If unused, keep it
VIHmax = 2.0 V open.

Main UART Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
1.8 V power
VOLmax = 0.45 V
DTE clear to send domain;
UART1_CTS 69 DO VOHmin = 1.35 V
signal from DCE connect to DTE’s
VOHmax = 1.8 V
CTS.

RG50xQ_Series_Hardware_Design 33 / 131
 5G Module Series

1.8 V power
DTE request to VILmax = 0.6 V
domain;
UART1_RTS 72 DI send signal to VIHmin = 1.2 V
connect to DTE’s
DCE VIHmax = 2.0 V
RTS.
VOLmax = 0.45 V
UART1_TXD 68 DO UART1 transmit VOHmin = 1.35 V
VOHmax = 1.8 V
VILmax = 0.6 V
UART1_RXD 70 DI UART1 receive VIHmin = 1.2 V
VIHmax = 2.0 V
VOLmax = 0.45 V
UART1 ring 1.8 V power
UART1_RI* 100 DO VOHmin = 1.35 V
indication domain.
VOHmax = 1.8 V
UART1 data VILmax = 0.6 V
UART1_DTR 258 DI terminal ready, VIHmin = 1.2 V
sleep mode control VIHmax = 2.0 V
VOLmax = 0.45 V
UART1 data
UART1_DCD* 261 DO VOHmin = 1.35 V
carrier detect
VOHmax = 1.8 V

Bluetooth UART Interface*

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VOLmax = 0.45 V 1.8 V power
Bluetooth UART
BT_UART_TXD 59 DO VOHmin = 1.35 V domain.
transmit
VOHmax = 1.8 V Can be
multiplexed into
one IPQ807x
VILmax = 0.6 V status interface*
Bluetooth UART
BT_UART_RXD 63 DI VIHmin = 1.2 V and one err fatal
receive
VIHmax = 2.0 V interface*. For
details, see
Chapter 3.19.
Connect to DTE’s
RTS; 1.8 V power
domain.
Can be
DTE request to VILmax = 0.6 V multiplexed into
BT_UART_RTS 61 DI send signal to VIHmin = 1.2 V one IPQ807x
DCE VIHmax = 2.0 V status interface*
and one err fatal
interface*. For
details, see
Chapter 3.19.

RG50xQ_Series_Hardware_Design 34 / 131
 5G Module Series

Connect to DTE’s
CTS; 1.8 V power
domain.
Can be
VOLmax = 0.45 V multiplexed into
DTE clear to send
BT_UART_CTS 62 DO VOHmin = 1.35 V one IPQ807x
signal from DCE
VOHmax = 1.8 V status interface*
and one err fatal
interface*. For
details, see
Chapter 3.19.

Debug UART Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VILmax = 0.6 V
Debug UART
DBG_RXD 108 DI VIHmin = 1.2 V
receive
VIHmax = 2.0 V 1.8 V power
VOLmax = 0.45 V domain.
Debug UART
DBG_TXD 105 DO VOHmin = 1.35 V
transmit
VOHmax = 1.8 V

I2C Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

I2C1_SCL 77 OD I2C serial clock Pull each of them

up to VDD_EXT
VOLmax = 0.45 V
with an external
VOHmin = 1.35 V
4.7 kΩ resistor. If
I2C1_SDA 78 OD I2C serial data VOHmax = 1.8 V
unused, keep
them open.
12
I2S Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
In master mode, it
VILmax = 0.6 V is an output
VIHmin = 1.2 V signal.
I2S word select VIHmax = 2.0 V In slave mode, it is
I2S_WS 259 DIO
(L/R) VOLmax = 0.45 V an input signal.
VOHmin = 1.35 V Can be
VOHmax = 1.8 V multiplexed into
PCM_SYNC.

12 I2S interface is under development, but it is available to be multiplexed into PCM interface by default currently.

RG50xQ_Series_Hardware_Design 35 / 131
 5G Module Series

In master mode, it
is an output
signal.
In slave mode, it is
I2S_SCK 256 DIO I2S clock
an input signal.
Can be
multiplexed into
PCM_CLK.
VILmax = 0.6 V Can be
I2S_DIN 257 DI I2S data input VIHmin = 1.2 V multiplexed into
VIHmax = 2.0 V PCM_IN.
VOLmax = 0.45 V Can be
I2S_DOUT 255 DO I2S data output VOHmin = 1.35 V multiplexed into
VOHmax = 1.8 V PCM_OUT.
Provides digital
VOLmax = 0.45 V
clock output for If unused, keep it
I2S_MCLK 79 DO VOHmin = 1.35 V
external audio open.
VOHmax = 1.8 V
codec

PCM Interface*

DC
Pin Name Pin No. I/O Description Comment
Characteristics
In master mode, it
is an output
PCM data frame
PCM_SYNC 71 DIO VILmax = 0.6 V signal.
sync
VIHmin = 1.2 V In slave mode, it is
VIHmax = 2.0 V an input signal.
VOLmax = 0.45 V In master mode, it
VOHmin = 1.35 V is an output
PCM_CLK 73 DIO PCM clock VOHmax = 1.8 V signal.
In slave mode, it is
an input signal.
VILmax = 0.6 V
If unused, keep it
PCM_IN 74 DI PCM data input VIHmin = 1.2 V
open.
VIHmax = 2.0 V
VOLmax = 0.45 V
If unused, keep it
PCM_OUT 76 DO PCM data output VOHmin = 1.35 V
open.
VOHmax = 1.8 V

PCIe Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
PCIe reference Requires
PCIE_REFCLK_P 40 AIO
clock (+) differential

RG50xQ_Series_Hardware_Design 36 / 131
 5G Module Series

PCIe reference impedance of

PCIE_REFCLK_M 38 AIO
clock (-) 85 Ω.
PCIe Gen3
PCIE_TX0_M 44 AO PCIe transmit 0 (-)
compliant.
PCIE_TX0_P 46 AO PCIe transmit 0 (+)

PCIE_TX1_M 41 AO PCIe transmit 1 (-)

PCIE_TX1_P 43 AO PCIe transmit 1 (+)

PCIE_RX0_M 32 AI PCIe receive 0 (-)

PCIE_RX0_P 34 AI PCIe receive 0 (+)

PCIE_RX1_M 35 AI PCIe receive 1 (-)

PCIE_RX1_P 37 AI PCIe receive 1 (+)

1.8 V power
domain.
VOLmax = 0.45 V
In master mode, it
PCIE_CLKREQ 36 OD PCIe clock request VOHmin = 1.35 V
is an input signal.
VOHmax = 1.8 V
In slave mode, it is
an output signal.
1.8 V power
VILmax = 0.6 V
domain.
VIHmin = 1.2 V
In master mode, it
VIHmax = 2.0 V
PCIE_RST 39 DIO PCIe reset is an output
VOLmax = 0.45 V
signal.
VOHmin = 1.35 V
In slave mode, it is
VOHmax = 1.8 V
an input signal.
1.8 V power
domain.
VOLmax = 0.45 V
In master mode, it
PCIE_WAKE 30 OD PCIe wake up VOHmin = 1.35 V
is an input signal.
VOHmax = 1.8 V
In slave mode, it is
an output signal.

RGMII Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
RGMII The power domain Single-ended
RGMII_MD_IO 10 OD management data of RGMII I/O pins impedance of
input/output depends on 50 Ω.

RG50xQ_Series_Hardware_Design 37 / 131
 5G Module Series

RGMII RGMII_PWR_IN,
RGMII_MD_CLK 11 DO management data which is 1.8 V or
clock 2.5 V typically.
RGMII receive
RGMII_RX_0 13 DI
data bit 0
RGMII receive
RGMII_RX_1 14 DI
data bit 1
RGMII receive
RGMII_CTL_RX 15 DI
control
RGMII receive
RGMII_RX_2 16 DI
data bit 2
RGMII receive
RGMII_RX_3 17 DI
data bit 3
RGMII receive
RGMII_CK_RX 19 DI
clock
RGMII transmit
RGMII_TX_0 20 DO
data bit 0
RGMII transmit
RGMII_CTL_TX 21 DO
control
RGMII transmit
RGMII_TX_1 22 DO
data bit 1
RGMII transmit
RGMII_TX_2 23 DO
data bit 2
RGMII transmit
RGMII_CK_TX 24 DO
clock
RGMII transmit
RGMII_TX_3 25 DO
data bit 3
RGMII power
enable control. VOLmax = 0.45 V
1.8 V power
RGMII_PWR_EN 27 DO Controls external VOHmin = 1.35 V
domain.
LDO to supply VOHmax = 1.8 V
1.8 V or 2.5 V.
1.8 V or 2.5 V.
Power supply for
RGMII_PWR_IN 28 PI If unused, connect
RGMII I/O pins
it to VDD_EXT.
VILmax = 0.6 V
PHY interrupt
RGMII_INT 29 DI VIHmin = 1.2 V
output
VIHmax = 2.0 V 1.8 V power
Resets PHY VOLmax = 0.45 V domain.
RGMII_RST 31 DO chipset after VOHmin = 1.35 V
power-on VOHmax = 1.8 V

WWAN/WLAN Control Interface*

RG50xQ_Series_Hardware_Design 38 / 131
 5G Module Series

DC
Pin Name Pin No. I/O Description Comment
Characteristics
VILmax = 0.6 V
COEX_UART_ Coexistence Signal interface
65 DI VIHmin = 1.2 V
RXD UART receive used for
VIHmax = 2.0 V
WWAN/WLAN
VOLmax = 0.45 V
COEX_UART_ Coexistence coexistence
67 DO VOHmin = 1.35 V
TXD UART transmit mechanism.
VOHmax = 1.8 V
Notifies LAA/n79
VOLmax = 0.45 V
transmission from 1.8 V power
HST_LAA_TX_EN 135 DO VOHmin = 1.35 V
SDR transceiver to domain.
VOHmax = 1.8 V
WLAN
Notifies WLAN
VILmax = 0.6 V
transmission from 1.8 V power
HST_WL_TX_EN 138 DI VIHmin = 1.2 V
WLAN to SDR domain.
VIHmax = 2.0 V
transceiver
Controls WLAN
WLAN_PWR_EN1 216 DO
PA power
Controls WLAN
WLAN_PWR_EN2 219 DO other power VOLmax = 0.45 V
1.8 V power
(3.3 V or 1.8 V) VOHmin = 1.35 V
domain.
VOHmax = 1.8 V
BT_EN 64 DO Bluetooth enable

WLAN_EN 222 DO WLAN enable

VILmax = 0.6 V
38.4 MHz system 1.8 V power
WL_SW_CTRL 180 DI VIHmin = 1.2 V
clock request domain.
VIHmax = 2.0 V
VOLmax = 0.45 V
32.768 kHz sleep 1.8 V power
WLAN_SLP_CLK 225 AO VOHmin = 1.35 V
clock output domain.
VOHmax = 1.8 V
Vmax = 1.3 V
38.4 MHz system
RF_CLK3_WL 246 AO Vnom = 1.25 V
clock output
Vmin = 1.2 V
VOLmax = 0.45 V Not used by
SDX_TO_WL_CTI 276 DO - VOHmin = 1.35 V default.
VOHmax = 1.8 V Keep it open.
VOLmax = 0.45 V
WLAN_PA_ GPIO from SDX to 1.8 V power
162 DO VOHmin = 1.35 V
MUTING disable WLAN PA domain.
VOHmax = 1.8 V

RG50xQ_Series_Hardware_Design 39 / 131
 5G Module Series

GPIO to allow
WWAN to power
on WLAN 0.8 V
AON domain,
when WLAN is
sleeping or
VOLmax = 0.45 V
disabled. 1.8 V power
WL_LAA_AS_EN 159 DO VOHmin = 1.35 V
Additionally, the domain.
VOHmax = 1.8 V
control logic in
WLAN AON
domain allows
SDR to control 5G
WLAN xLNA (LNA
in FEMs)
SoC signal to set
5G xLNA to high
gains or high
isolation when
both chains VOLmax = 0.45 V
1.8 V power
WL_LAA_RX 201 DO (LAA/n79 and 5G VOHmin = 1.35 V
domain.
WLAN) are active VOHmax = 1.8 V
simultaneously.
No individual
control for each
chain
VILmax = 0.6 V Not used by
WL_TO_SDX 275 DI - VIHmin = 1.2 V default.
VIHmax = 2.0 V Keep it open.

SD Card Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
1.8/2.95 V
SDIO power configurable input.
SDIO_VDD 60 PI
supply If unused, connect
it to VDD_EXT.

SDC1_DATA_0 49 DIO SDIO data bit 0

The power domain
SDC1_DATA_1 50 DIO SDIO data bit 1
of SD I/O pins If unused, keep
depends on them open.
SDC1_DATA_2 51 DIO SDIO data bit 2
SDIO_VDD.
SDC1_DATA_3 52 DIO SDIO data bit 3

RG50xQ_Series_Hardware_Design 40 / 131
 5G Module Series

SDC1_CMD 48 DIO SDIO command

SDC1_CLK 47 DO SDIO clock

SDIO power
SDC1_PWR_EN 53 DO VOLmax = 0.45 V
supply enable If unused, keep
VOHmin = 1.35 V
SDC1_PWR_ SDIO power them open.
56 DO VOHmax = 1.8 V
VSET domain set
Pull it up to
VILmax = 0.6 V VDD_EXT with a
SD card hot-plug
SDC1_DET 55 DI VIHmin = 1.2 V 470 kΩ resistor.
detect
VIHmax = 2.0 V If unused, keep it
open.

Antenna Interfaces for RG500Q-EA/RG502Q-EA

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41 TRX1 & n79 DRX1
ANT0 121 AIO 50 Ω impedance
- LTE: LMHB_TRX
- WCDMA: LMHB_TRX
Antenna 1 interface:
- 5G NR: n41 DRX1 & n79 TRX1
ANT1 130 AIO 50 Ω impedance
- LTE: LB_TRX & LMHB_DRX
- WCDMA: LMHB_DRX
Antenna 2 interface:
ANT2 139 AI 50 Ω impedance
- 5G NR: n79 DRX0
Antenna 3 interface:
ANT3 148 AIO 50 Ω impedance
- 5G NR: n79 TRX0
Antenna 4 interface:
- 5G NR: n77/78 TRX0
ANT4 157 AIO 50 Ω impedance
- LTE: MHB_PRX MIMO &
UHB_TRX
Antenna 5 interface:
ANT5 166 AIO - 5G NR: n41 TRX0 & n77/78 TRX1 50 Ω impedance
- LTE: UHB_PRX MIMO
Antenna 6 interface:
- 5G NR: n41/n77/n78 DRX0
ANT6 175 AI 50 Ω impedance
- LTE: MHB_DRX MIMO &
UHB_DRX
Antenna 7 interface:
- 5G NR: n77/78 DRX1
ANT7 184 AIO 50 Ω impedance
- LTE: MHB_TRX1 & UHB_DRX
MIMO

RG50xQ_Series_Hardware_Design 41 / 131
 5G Module Series

ANT_GNSS 193 AI GNSS antenna interface 50 Ω impedance

Antenna Interfaces for RG500Q-CN

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41/n78/n79 TRX1
ANT0 130 AIO 50 Ω impedance
- LTE: LMHB_TRX
- WCDMA: LMB_TRX
Antenna 1 interface:
- 5G NR: n41 DRX1 & n78/n79 DRX0
ANT1 157 AI 50 Ω impedance
- LTE: LMHB_DRX
- WCDMA: LMB_DRX
Antenna 2 interface:
- 5G NR: n41 DRX0 & n78/n79 DRX1
ANT2 166 AI 50 Ω impedance
- LTE: MB_PRX MIMO & HB_DRX
MIMO
Antenna 3 interface:
- 5G NR: n41/n78/n79 TRX0
ANT3 184 AIO 50 Ω impedance
- LTE: MB_DRX MIMO & HB_PRX
MIMO

ANT_GNSS 193 AI GNSS antenna interface 50 Ω impedance

Antenna Interfaces for RG501Q-EU/RG502Q-EU

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41/n77/n78 TRX1
ANT0 130 AIO - LTE: LMHB_TRX & UHB_PRX 50 Ω impedance
MIMO
- WCDMA: LMHB_TRX
Antenna 1 interface:
- 5G NR: n41 DRX1 & n77/n78 DRX1
ANT1 157 AI - LTE: LMHB_DRX & UHB_DRX 50 Ω impedance
MIMO
- WCDMA: LMHB_DRX
Antenna 2 interface:
- 5G NR: n41 DRX0 & n77/n78 DRX0
ANT2 166 AI 50 Ω impedance
- LTE: LMHB_DRX MIMO &
UHB_DRX

RG50xQ_Series_Hardware_Design 42 / 131
 5G Module Series

Antenna 3 interface:
- 5G NR: n41/n77/n78 TRX0
ANT3 184 AIO 50 Ω impedance
- LTE: LMHB_PRX MIMO &
UHB_TRX & LMHB_TRX1
Antenna 4 interface:
ANT4 121 AI 50 Ω impedance
- LTE: B32_PRX (optional)
Antenna 5 interface:
ANT5 175 AI 50 Ω impedance
- LTE: B32_PRX MIMO (optional)

ANT_GNSS 193 AI GNSS antenna interface 50 Ω impedance

Antenna Tuner Control Interface*

DC
Pin Name Pin No. I/O Description Comment
Characteristics

SDR_GRFC15 171 DO GRFC interface

VOLmax = 0.45 V
dedicated for If unused, keep
VOHmin = 1.35 V
external antenna them open.
SDR_GRFC14 174 DO VOHmax = 1.8 V
tuner control

SPI Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics

SPI1_CLK 210 DO SPI1 clock VOLmax = 0.45 V

VOHmin = 1.35 V
SPI1_CS 207 DO SPI1 chip select VOHmax = 1.8 V
1.8 V power
VILmax = 0.6 V domain.
SPI1 master-in
SPI1_MISO 213 DI VIHmin = 1.2 V Only master mode
slave-out
VIHmax = 2.0 V is supported.
VOLmax = 0.45 V
SPI1 master-out
SPI1_MOSI 204 DO VOHmin = 1.35 V
slave-in
VOHmax = 1.8 V

ADC Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
General-purpose Voltage range:
ADC0 241 AI
ADC interface 0–1.875 V

Time Service and Repeater Interface*

DC
Pin Name Pin No. I/O Description Comment
Characteristics

RG50xQ_Series_Hardware_Design 43 / 131
 5G Module Series

Supports time
service and
repeater functions; VOLmax = 0.45 V
1.8 V power
GPIO_32 98 DO supports 1PPS VOHmin = 1.35 V
domain
pulse output and VOHmax = 1.8 V
frame
synchronization

Other Interface Pins

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Forces the module VILmax = 0.6 V
USB_BOOT 81 DI into emergency VIHmin = 1.2 V
download mode VIHmax = 2.0 V
VOLmax = 0.45 V
Used for audio
EXT_RST 75 DO VOHmin = 1.35 V 1.8 V power
reset
VOHmax = 1.8 V domain
Interrupts input
EXT_INT* 281 DI VILmax = 0.6 V
from audio chipset
VIHmin = 1.2 V
Airplane mode
W_DISABLE 114 DI VIHmax = 2.0 V
control

RESERVED Pins for RG500Q-EA/RG502Q-EA

Pin Name Pin No. Comment

1–6, 9, 45, 54, 57, 58, 80, 87, 92–95, 97, 99, 101, 103, 104,
106, 111, 117, 120, 150, 153, 165, 177, 183, 186, 189, 192, Keep these pins
RESERVED
198, 199, 208, 217, 218, 220, 221, 223, 239, 260, 262–265, unconnected.
270–274, 277–280, 282–298

RESERVED Pins for RG500Q-CN

Pin Name Pin No. Comment

1~6, 9, 45, 54, 57, 58, 80, 87, 92~95, 97, 99, 101, 103, 104,
106, 111, 117, 120, 121, 139, 148, 150, 153, 165, 175, 177, Keep these pins
RESERVED
183, 186, 189, 192, 198, 199, 208, 217, 218, 220, 221, 223, unconnected.
239, 260, 262~265, 270~274, 277~280, 282~298

RESERVED Pins for RG501Q-EU/RG502Q-EU

Pin Name Pin No. Comment

1–6, 9, 45, 54, 57, 58, 80, 87, 92–95, 97, 99, 101, 103, 104,
106, 111, 117, 120, 139, 148, 150, 153, 165, 177, 183, 186, Keep these pins
RESERVED
189, 192, 198, 199, 208, 217, 218, 220, 221, 223, 239, 260, unconnected.
262–265, 270–274, 277–280, 282–298

RG50xQ_Series_Hardware_Design 44 / 131
 5G Module Series

3.3. Operating Modes

Table 9: Overview of Operating Modes

Mode Details

Software is active. The module has registered on the network, and it is

Idle
Normal ready to send and receive data.
Operation Network connection is ongoing. In this mode, the power consumption is
Talk/Data
decided by network setting and data transfer rate.
Minimum
AT+CFUN=0 can set the module to a minimum functionality mode without removing
Functionality
the power supply. In this case, both RF function and (U)SIM card are invalid.
Mode
AT+CFUN=4 or W_DISABLE pin can set the module to airplane mode. In this case,
Airplane Mode
RF function is invalid.
In this mode, the current consumption of the module is reduced to the minimal level.
Sleep Mode During this mode, the module can still receive paging message, SMS, voice call and
TCP/UDP data from the network normally.
In this mode, the power management unit shuts down the power supply. Software is
Power Down
not active. The serial interfaces are not accessible. Operating voltage (connected to
Mode
VBAT_RF1 and VBAT_BB) remains applied.

NOTE

For more details about AT command, see document [3].

3.4. Power Saving

3.4.1. Sleep Mode

DRX on RG50xQ series module is able to reduce the current consumption to a minimum value during
sleep mode, and DRX cycle index values are broadcast by the wireless network. The figure below shows
the relationship between the DRX run time and the current consumption in sleep mode. The longer the
DRX runs, the lower the current consumption is.

RG50xQ_Series_Hardware_Design 45 / 131
 5G Module Series

Current Consumption

DRX OFF ON OFF ON OFF ON OFF ON OFF

Run Time

Figure 7: DRX Run Time and Current Consumption in Sleep Mode

The following section describes power saving procedures of RG50xQ series module.

3.4.1.1. UART Application

If the host communicates with the module via UART interface, the following preconditions can make the
module enter sleep mode.

⚫ Execute AT+QSCLK=1 to enable sleep mode.

⚫ Drive UART1_DTR high.

The following figure shows the connection between the module and the host.

Module Host
UART1_RXD TXD

UART1_TXD RXD

UART1_RI EINT

UART1_DTR GPIO

GND GND

Figure 8: Sleep Mode Application via UART

⚫ You can wake up the module by driving UART1_DTR low with the host.
⚫ When the module has a URC to report, RI signal wakes up the host. See Chapter 3.15 for details
about RI behaviors.

RG50xQ_Series_Hardware_Design 46 / 131
 5G Module Series

3.4.1.2. USB Application with USB Remote Wakeup Function

If the host supports USB suspend/resume and remote wakeup function, the following three preconditions
can make the module enter the sleep mode.

⚫ Execute AT+QSCLK=1 to enable sleep mode.

⚫ Ensure the UART1_DTR is held at high level or keep it open.
⚫ Ensure the host’s USB bus, which is connected with the module’s USB interface, enters suspend
state.

The following figure shows the connection between the module and the host.

Module Host
USB_VBUS VDD

USB_DP USB_DP

USB_DM USB_DM

GND GND

Figure 9: Sleep Mode Application with USB Remote Wakeup

You can wake up the module by sending data to it through USB.

⚫NOTE
When the module has a URC to report, the module sends remote wake-up signals to wake up the host
through the USB bus, which is under development.

3.4.1.3. USB Application with USB Suspend/Resume and RI Function

If the host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is
needed to wake up the host.

In this case, the following three preconditions can make the module enter the sleep mode.

⚫ Execute AT+QSCLK=1 to enable sleep mode.

⚫ Ensure the UART1_DTR is held at a high level or keep it open.
⚫ Ensure the host’s USB bus, which is connected with the module’s USB interface, enters suspend
state.

RG50xQ_Series_Hardware_Design 47 / 131
 5G Module Series

The following figure shows the connection between the module and the host.

Module Host
USB_VBUS VDD

USB_DP USB_DP

USB_DM USB_DM

UART1_RI EINT

GND GND

Figure 10: Sleep Mode Application with RI

⚫ You can wake up the module by sending data to it through USB.

⚫ When the module has a URC to report, RI signal wakes up the host.

3.4.1.4. USB Application without USB Suspend Function

If the host does not support USB suspend function, disconnect USB_VBUS with an external control circuit
to make the module enter sleep mode.

⚫ Execute AT+QSCLK=1 to enable sleep mode.

⚫ Ensure the UART1_DTR is held at high level or keep it open.
⚫ Disconnect USB_VBUS.

The following figure shows the connection between the module and the host.

Module Host
GPIO

Power
USB_VBUS Switch VDD

USB_DP USB_DP

USB_DM USB_DM

UART1_RI EINT

GND GND

Figure 11: Sleep Mode Application without Suspend Function

RG50xQ_Series_Hardware_Design 48 / 131
 5G Module Series

You can wake up the module by switching on the power switch to supply power to USB_VBUS.

NOTE

Pay attention to the level match shown in dotted line between the module and the host.

3.4.2. Airplane Mode

When the module enters airplane mode, the RF function does not work and all AT commands related to
the RF function are inaccessible. You can set this mode via the following ways.

Hardware:

The W_DISABLE pin is pulled up by default. Driving it low makes the module enter airplane mode.

Software:

AT+CFUN=<fun> provides the choice of functionality level by setting <fun> into 0, 1 or 4.

⚫ AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
⚫ AT+CFUN=1: Full functionality mode (by default).
⚫ AT+CFUN=4: Airplane mode. RF function is disabled.

NOTE

The execution of AT+CFUN does not affect GNSS function.

3.5. Power Supply

3.5.1. Power Supply Pins

RG50xQ series module provides 7 VBAT pins dedicated for connection with the external power supply.
There are two separate voltage domains for VBAT.

⚫ Four VBAT_RF1 pins for module’s RF part

⚫ Three VBAT_BB pins for module’s baseband part

RG50xQ_Series_Hardware_Design 49 / 131
 5G Module Series

Table 10: VBAT and GND Pins

Pin Name Pin No. Description Min. Typ. Max. Unit

Power supply for the

VBAT_RF1 229, 230, 232, 233 3.3 3.8 4.3 V
module’s RF part
Power supply for the
VBAT_BB 235, 236, 238 module’s baseband 3.3 3.8 4.3 V
part
12, 18, 26, 33, 42, 84, 90, 96, 113,
115, 116, 118, 119, 122–129,
131–134, 136, 137, 140–147, 149,
151, 152, 154–156, 158, 160, 161,
163, 164, 167–170, 172, 173, 176,
GND Ground - 0 - V
178, 179, 181, 182, 185, 187, 188,
190, 191, 194–197, 200, 202, 203,
205, 206, 209, 211, 212, 214, 215,
224, 226, 227, 228, 231, 234,
299–392

3.5.2. Voltage Stability Requirements

The power supply range of the module is from 3.3 V to 4.3 V. Make sure the input voltage never drops
below 3.3 V. The following figure shows the voltage drop during burst transmission.

Burst Burst
Transmission Transmission

VCC Ripple
Drop

Figure 12: Power Supply Limits during Burst Transmission

To decrease the voltage drop, use a bypass capacitor of about 100 μF with low ESR and reserve a
multi-layer ceramic chip (MLCC) capacitor array due to its ultra-low ESR. Use seven ceramic capacitors
(100 nF, 6.8 nF, 220 pF, 68 pF, 15 pF, 9.1 pF, 4.7 pF) to compose the MLCC array, and place these
capacitors close to VBAT pins. The main power supply from an external application has to be a single
voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace
should be no less than 1.2 mm, and the width of VBAT_RF trace should be no less than 2.0 mm. In

RG50xQ_Series_Hardware_Design 50 / 131
 5G Module Series

principle, the longer the VBAT trace is, the wider it should be.

In addition, to avoid the surge, use a TVS diode of which the reverse working voltage should be 5.1 V.
The following figure shows the star structure of the power supply.

C1 C2 C3 C4 C5
VBAT
100 μF 100 nF 6.8 nF 220 pF 68 pF
R1 0R
VBAT_BB
R2 0R
VBAT_RF1

100 μF 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF

D1

C6 C7 C8 C9 C10 C11 C12

VBAT_RF2

100 μF 100 nF 220 pF 68 pF 15 pF 9.1 pF 4.7 pF

C13 C14 C15 C16 C17 C18 C19

Module

Figure 13: Star Structure of Power Supply

3.5.3. Reference Design for Power Supply

Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply of RG50xQ series module should be able to provide sufficient current of
3 A at least. If the voltage drop between the input and output is not too high, use an LDO to supply power
to the module. If there is a big voltage difference between the input source and the desired output (VBAT),
use a buck converter as the power supply.

The following figure shows a reference design for +5 V input power source. The designed output of the
power supply is about 3.8 V and the maximum rated current is 5 A.

RG50xQ_Series_Hardware_Design 51 / 131
 5G Module Series

U1
L1 2.2 μH

PGND SW
PGND SW R4 DC_3V8
AGND SW 100K R5
PVIN VOS
75K
VCC_5 V R3 PVIN PG
51K PVIN FB C4 C5
D1 22 μF 100 nF
C1 C2 C3 EN FSW
470 μF 10 μF 100 nF SS/TR DEF R6
GND
20K
Q1
R1 4.7K C6
3V8_EN
3.3 nF
R2 47K

Figure 14: Reference Circuit of Power Supply

NOTE
To avoid damaging internal flash, do not switch off the power supply when the module works normally.
Only after shutting down the module with PWRKEY or AT command can you cut off the power supply.

3.5.4. Monitor the Power Supply

You can use AT+CBC to monitor the VBAT_BB voltage value. For more details, see document [3].

3.6. Turn on and Turn off

3.6.1. Turn on

3.6.1.1. Turn on with PWRKEY

Table 11: Pin Definition of PWRKEY

Pin Name Pin No. Description DC Characteristics Comment

PWRKEY 7 Turns on/off the module 1.0 V high level Internally pulled up

When the module is in power down mode, you can turn it on to normal mode by driving the PWRKEY pin
low for at least 500 ms. It is recommended to use an open drain/collector driver to control the PWRKEY.
After STATUS pin outputs a high level, the PWRKEY pin can be released. A simple reference circuit is
illustrated in the following figure.

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 5G Module Series

PWRKEY

≥ 500 ms
4.7K

Turn-on pulse

47K

Figure 15: Turn on the Module Using Driving Circuit

Another way to control the PWRKEY is using a button directly. When you are pressing the key,
electrostatic strike may be generated from finger. Therefore, you must place a TVS component nearby
the button for ESD protection. A reference circuit is shown in the following figure.

S1
PWRKEY

TVS

Close to S1

Figure 16: Turn on the Module Using a Button

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 5G Module Series

The power-on scenario is illustrated in the following figure.

NOTE

VBA T 500 ms

PWRKEY

RESET_N
TBD
STATUS
TBD

UART Active

TBD

USB Act ive

Figure 17: Timing of Turning on the Module

NOTE

Make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the time
difference between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.

3.6.1.2. Turn on with PON_1

Table 12: Pin Definition of PON_1

Pin Name Pin No. Description Comment

Pull it up to 1.8–4.3 V. If unused, pull it

PON_1 242 LOW to HIGH indicates power on
down to GND with a 10 kΩ resistor.

3.6.2. Turn off

You can use the following ways to turn off the module:

⚫ Use the PWRKEY pin.

⚫ Use AT+QPOWD.

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3.6.2.1. Turn off with PWRKEY

Drive the PWRKEY pin low for at least 800 ms and then release PWRKEY. After this, the module
executes power-down procedure.

The power-down scenario is illustrated in the following figure.

VBA T

800 ms 15 s

PWRKEY

STATUS

Module Running Power-down procedure OFF

Status

Figure 18: Timing of Turning off the Module

3.6.2.2. Turn off with AT Command

It is also a safe way to use AT+QPOWD to turn off the module, which is similar to turning off the module
via the PWRKEY pin.

See document [3] for details about AT+QPOWD.

NOTE

1. To avoid damaging internal flash, do not switch off the power supply when the module works
normally. Only after shutting down the module with PWRKEY or AT command can you cut off the
power supply.
2. When turning off module with the AT command, keep PWRKEY at high level after execution of the
power-off command. Otherwise, the module will be turned on again after successful power-off.

3.7. Reset

You can reset the module by driving RESET_N low for 250–550 ms.

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Table 13: Pin Definition of RESET_N

Pin Name Pin No. Description DC Characteristics Comment

VIHmax = 2.0 V
RESET_N 8 Resets the module VIHmin = 1.2 V Internally pulled up to 1.5 V.
VILmax = 0.6 V

The recommended circuit is similar to the PWRKEY control circuit. You can use an open drain/collector
driver or button to control RESET_N. Due to the strict requirement of RESET_N control timing sequence,
if you want to use the button for control, please refer to document [10] and use the reset chip to achieve
reset control. The reset chip low pulse time of reset chip output should be between 250–550 ms.

RESET_N

250–550 ms
4.7K

Reset pulse

47K

Figure 19: Reference Circuit of RESET_N by Using Driving Circuit

The reset scenario is illustrated in the following figure.

VBAT
≤ 550 ms
≥ 250 ms
RESET_N

Module Running Resetting Restart

Status

Figure 20: Timing of Resetting the Module

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 5G Module Series

NOTE

1. Use RESET_N only when you fail to turn off the module with the AT+QPOWD and PWRKEY.
2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.
3. If RESET_N remains low for more than 550 ms, there is a risk of power-off. It is recommended to
control it according to the RESET_N timing sequence.

3.8. (U)SIM Interfaces

The (U)SIM interfaces circuitry meets ETSI and IMT-2000 requirements. Either 1.8 V or 2.95 V (U)SIM
card is supported.

Table 14: Pin Definition of (U)SIM Interfaces

Pin Name Pin No. I/O Description Comment

Either 1.8 V or 2.95 V is

USIM1_VDD 245 PO (U)SIM1 card power supply supported by the module
automatically.

USIM1_DATA 248 DIO (U)SIM1 card data

USIM1_CLK 247 DO (U)SIM1 card clock

USIM1_RST 244 DO (U)SIM1 card reset

1.8 V power domain.

USIM1_DET 249 DI (U)SIM1 card hot-plug detect
If unused, keep it open.
Either 1.8 V or 2.95 V is
USIM2_VDD 250 PO (U)SIM2 card power supply supported by the module
automatically.

USIM2_DATA 251 DIO (U)SIM2 card data

USIM2_CLK 253 DO (U)SIM2 card clock

USIM2_RST 254 DO (U)SIM2 card reset

1.8 V power domain.

USIM2_DET 252 DI (U)SIM2 card hot-plug detect
If unused, keep it open.

RG50xQ series module supports (U)SIM card hot-plug via the USIM_DET pin. The function supports low
level and high level detections. It is disabled by default and you can configure it via AT+QSIMDET. See
document [3] for more details about the command.

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The following figure shows a reference design for (U)SIM card interface with an 8-pin (U)SIM card
connector.

VDD_EXT USIM_VDD

470K 20K
10 pF 100 nF (U)SIM Card Connector

USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK Switch
CLK IO
USIM_DET 0R
CD1 CD2
USIM_DATA 0R

GND
10 pF 10 pF 10 pF

GND

Figure 21: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector

If the function of (U)SIM card hot-plug is not needed, keep USIM_DET disconnected. A reference circuit
for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.

USIM_VDD

20K
10 pF 100 nF (U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
0R
USIM_DATA 0R

10 pF 10 pF 10 pF

GND

Figure 22: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector

To enhance the reliability and availability of the (U)SIM card in applications, follow the criteria below in the
(U)SIM circuit design:

⚫ Place the (U)SIM card connector as close to the module as possible. Keep the trace length as less

RG50xQ_Series_Hardware_Design 58 / 131
 5G Module Series

than 200 mm as possible.

⚫ Keep (U)SIM card signals away from RF and VBAT traces.
⚫ Make sure the ground between the module and the (U)SIM card connector is short and wide. Keep
the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric
potential.
⚫ To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
⚫ To offer good ESD protection, add a TVS diode array of which the parasitic capacitance should be
less than 26 pF. Add 0 Ω resistors in series between the module and the (U)SIM card to facilitate
debugging. Additionally, keep the (U)SIM peripheral circuit close to the (U)SIM card connector.
⚫ For USIM_DATA, a 20 kΩ pull-up resistor must be added near the (U)SIM card connector.
⚫ (U)SIM card hot-plug is disabled by default.

3.9. USB Interface

RG50xQ series module provides one integrated Universal Serial Bus (USB) interface which complies with
the USB 3.1/2.0 specifications and supports super speed (10 Gbps) on USB 3.1, high speed (480 Mbps)
and full speed (12 Mbps) modes on USB 2.0. The USB interface is used for AT command communication,
data transmission, GNSS NMEA sentence output, software debugging and firmware upgrade.

Table 15: Pin Definition of USB Interface

DC
Pin Name Pin No. I/O Description Comment
Characteristics
Vmax = 5.25 V For USB connection
USB connection
USB_VBUS 82 AI Vmin = 3.3 V detection only, not
detect
Vnom = 5.0 V power supply.
USB differential
USB_DP 83 AIO Requires differential
data bus (+)
impedance of 90 Ω.
USB differential
USB_DM 85 AIO USB 2.0 compliant.
data bus (-)
USB 3.1
USB_SS_TX_P 91 AO super-speed
transmit (+)
Requires differential
USB 3.1
impedance of 85 Ω.
USB_SS_TX_M 89 AO super-speed
USB 3.1 Gen2
transmit (-)
compliant.
USB 3.1
USB_SS_RX_P 88 AI super-speed
receive (+)

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 5G Module Series

USB 3.1
USB_SS_RX_M 86 AI super-speed
receive (-)

For more details about the USB 2.0 & 3.1 specifications, visit http://www.usb.org/home.

Reserve the USB 2.0 interface for firmware upgrade in your design. The following figure shows a
reference circuit of USB 2.0 & USB 3.1 interface.

Test Points
Minimize these stubs

Module R3 NM_0R
Host

VDD R4 NM_0R

USB_VBUS ESD Array

R1 0R USB_DM
USB_DM
R2 0R
USB_DP USB_DP

Close to Module
C1 220 nF USB_SS_RX_P
USB_SS_TX_P

USB_SS_TX_M C2 220 nF USB_SS_RX_M

220 nF C3
USB_SS_RX_P USB_SS_TX_P
220 nF C4
USB_SS_RX_M USB_SS_TX_M

GND GND

Figure 23: Reference Circuit of USB Application

To ensure the signal integrity of USB data lines, you must place R1, R2, R3, R4, C1 and C2 close to the
module, C3 and C4 close to the host, and keep these resistors close to each other. Keep the extra stubs
of trace as short as possible.

When designing the USB interface, you should follow the following principles to meet USB 2.0 & USB 3.1
specifications.

⚫ Route the USB signal traces as differential pairs with ground surrounded. The impedance of USB 2.0
differential trace is 90 Ω. The impedance of USB 3.1 differential trace is 85 Ω.
⚫ For USB 2.0 signal traces, the trace length should be less than 250 mm, and the differential data pair
matching should be less than 2 mm. For USB 3.1 signal traces, length matching of each differential
data pair (Tx/Rx) should be less than 0.7 mm, while the matching between Tx and Rx should be less
than 10 mm.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces.

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Route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on
that layer and with ground planes above and below.
⚫ Junction capacitance of the ESD protection device might cause influences on USB data lines, so you
should pay attention to the selection of the device. Typically, the stray capacitance should be less
than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1.
⚫ Keep the ESD protection devices as close to the USB connector as possible.
⚫ If possible, reserve a 0 Ω resistor on USB_DP and USB_DM lines respectively.

Table 16: USB Trace Length in RG500Q-CN

Pin No. Pin Name Length (mm) Length difference (P-M)

83 USB_DP 26.15
-0.65
85 USB_DM 26.80

91 USB_SS_TX_P 26.22
-0.08
89 USB_SS_TX_M 26.30

88 USB_SS_RX_P 26.54
0.22
86 USB_SS_RX_M 26.32

Table 17: USB Trace Length in RG501Q-EU and RG502Q-EU

Pin No. Pin Name Length (mm) Length difference (P-M)

83 USB_DP 25.64
0
85 USB_DM 25.64

91 USB_SS_TX_P 26.60
0.03
89 USB_SS_TX_M 26.57

88 USB_SS_RX_P 25.59
0.01
86 USB_SS_RX_M 25.58

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Table 18: USB Trace Length in RG500Q-EA and RG502Q-EA

Pin No. Pin Name Length (mm) Length difference (P-M)

83 USB_DP 21.75
0
85 USB_DM 21.75

91 USB_SS_TX_P 24.78
0.02
89 USB_SS_TX_M 24.76

88 USB_SS_RX_P 23.55
0.18
86 USB_SS_RX_M 23.37

NOTE

1. Currently, only USB 2.0 interface supports firmware upgrade.

2. Both USB 3.1 interface and PCIe Gen3 interface support data transmission, and USB 3.1 interface is
used by default. If you want to use PCIe interface for data communication, set it with AT+QCFG via
USB 2.0. For more details about AT command, see document [3].

3.10. UART Interfaces

The module provides four UART interfaces: one main UART interface (UART1), one debug UART
interface, one Bluetooth UART interface*, and one COEX UART interface*.

⚫ Main UART interface supports 115200 bps baud rate by default. This interface is used for AT
command communication. It supports RTS and CTS hardware flow control.
⚫ Debug UART interface supports 115200 bps baud rate. It is used for Linux console and log output.
⚫ Bluetooth UART interface supports 115200 bps baud rate. It is used for Bluetooth communication.
⚫ COEX UART interface is used for WWAN/WLAN coexistence mechanism.

Table 19: Pin Definition of UART Interfaces

Pin Name Pin No. I/O Description Comment

DTE clear to send signal 1.8 V power domain;

UART1_CTS 69 DO
from DCE connect to DTE’s CTS.
DTE request to send signal 1.8 V power domain;
UART1_RTS 72 DI
to DCE connect to DTE’s RTS.

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UART1_RXD 70 DI UART1 receive

UART1_DCD* 261 DO UART1 data carrier detect

UART1_TXD 68 DO UART1 transmit 1.8 V power domain.

UART1_RI* 100 DO UART1 ring indication

UART1 data terminal ready,

UART1_DTR 258 DI
sleep mode control

DBG_RXD 108 DI Debug UART receive

1.8 V power domain
DBG_TXD 105 DO Debug UART transmit

BT_UART_TXD* 59 DO Bluetooth UART transmit

1.8 V power domain
BT_UART_RXD* 63 DI Bluetooth UART receive

DTE request to send signal

BT_UART_RTS* 61 DI Connect to DTE’s RTS
to DCE
DTE clear to send signal
BT_UART_CTS* 62 DO Connect to DTE’s CTS
from DCE

COEX_UART_RXD* 65 DI Coexistence UART receive Signal interface used for

WWAN/WLAN coexistence
COEX_UART_TXD* 67 DO Coexistence UART transmit mechanism

The module provides 1.8 V UART interfaces. Use a level shifter if the application is equipped with a 3.3 V
UART interface. A level shifter TXS0108EPWR provided by Texas Instruments is recommended. The
following figure shows a reference design.

VDD_EXT VCCA VCCB VDD_MCU

0.1 μF 0.1 μF
10K
VDD_EXT OE GND
120K A1 B1 RI_MCU
UART1_RI
UART1_DCD A2 B2 DCD_MCU
UART1_CTS A3 Translator B3 CTS_MCU
UART1_RTS A4 B4 RTS_MCU
UART1_DTR A5 B5 DTR_MCU
UART1_TXD A6 B6 RXD_MCU
UART1_RXD A7 B7 TXD_MCU
51K 51K
A8 B8

Figure 24: Reference Circuit with Translator Chip

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Visit http://www.ti.com for more information.

Another example with transistor circuit is shown as below. For the design of circuits shown in dotted lines,
see that shown in solid lines, but pay attention to the direction of connection.

4.7K
VDD_EXT VDD_EXT
1 nF
MCU/ARM Module
10K

TXD UART1_RXD
RXD UART1_TXD
1 nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS UART1_RTS
CTS UART1_CTS
GPIO UART1_DTR
EINT UART1_RI
GPIO UART1_DCD
GND GND

Figure 25: Reference Circuit with Transistor Circuit

NOTE

1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps.
2. Please note that the module CTS is connected to the host CTS, and the module RTS is connected to
the host RTS.
3. Other baud rates of the main UART are under development.

13
3.11. I2S and I2C Interfaces

RG50xQ series module supports audio communication via one I2S digital interface and one I2C control
interface. And the I2S interface can be multiplexed into PCM function.

13 I2S interface is under development, but it is multiplexed into PCM interface by default currently.

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Table 20: Pin Definition of I2S and I2C Interfaces

Pin Name Pin No. I/O Description Comment

In master mode, it is an output signal.

I2S_WS 259 DIO I2S word select (L/R) In slave mode, it is an input signal.
Can be multiplexed into PCM_SYNC.
In master mode, it is an output signal.
I2S_SCK 256 DIO I2S clock In slave mode, it is an input signal.
Can be multiplexed into PCM_CLK.

I2S_DIN 257 DI I2S data input Can be multiplexed into PCM_IN.

I2S_DOUT 255 DO I2S data output Can be multiplexed into PCM_OUT.

Provides digital clock output

I2S_MCLK 79 DO If unused, keep it open.
for external audio codec

I2C1_SDA 78 OD I2C serial data Pull each of them up to VDD_EXT with

an external 4.7 kΩ resistor. If unused,
I2C1_SCL 77 OD I2C serial clock keep them open.

The following figure shows a reference design of I2S interface with an external codec IC.

MICBIAS

I2S_WS INP
BIAS
I2S_WS
INN
I2S_SCK I2S_SCK
I2S_DOUT I2S_DIN
I2S_DIN I2S_DOUT

LOUTP
I2C1_SCL SCL
I2C1_SDA SDA LOUTN
4.7K

4.7K

Module Codec

VDD_EXT

Figure 26: Reference Circuit of I2S Application with Audio Codec

3.12. ADC Interface

The module provides one Analog-to-Digital Converter (ADC) interface. To improve the accuracy of ADC,
surround the trace of ADC with ground.

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Table 21: Pin Definition of ADC Interface

Pin Name Pin No. I/O Description Comment

Voltage range:
ADC0 241 AI General-purpose ADC interface
0–1.875 V

Table 22: Characteristics of ADC Interface

Parameter Min. Typ. Max. Unit

ADC0 Voltage Range 0 - 1.875 V

NOTE

1. The input voltage of ADC should not exceed 1.875 V.

2. It is prohibited to supply any voltage to ADC pin when VBAT is removed.

3.13. Network Status Indication

The network indication pins NET_MODE* and NET_STATUS can drive the network status indicators. The
following tables describe the pin definition and logic level changes in different network status.

Table 23: Pin Definition of Network Connection Status/Activity Indicator

Pin Name Pin No. I/O Description Comment

Indicates the module’s network

NET_MODE* 240 DO 1.8 V power domain
registration mode
Indicates the module’s network
NET_STATUS 243 DO 1.8 V power domain
activity status

Table 24: Working State of the Network Connection Status/Activity Indicator

Pin Name Status Description

Always High Registered on 5G network

NET_MODE*
Always Low Others

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 5G Module Series

Flicker slowly (200 ms High/1800 ms Low) Network searching

Flicker slowly (1800 ms High/200 ms Low) Idle

NET_STATUS
Flicker quickly* (125 ms High/125 ms Low) Data transfer is ongoing

Always High Voice calling

A reference circuit is shown in the following figure.

Module VBAT

2.2K

Network 4.7K
Indicator
47K

Figure 27: Reference Circuit of the Network Indicator

3.14. STATUS

The STATUS pin indicates the module’s operation status. It outputs high level when the module is
powered on successfully.

Table 25: Pin Definition of STATUS

Pin Name Pin No. I/O Description Comment

STATUS 237 DO Indicates the module’s operation status 1.8 V power domain

A reference circuit is shown as below.

RG50xQ_Series_Hardware_Design 67 / 131
 5G Module Series

VBAT

Module

2.2K

4.7K
STATUS
47K

Figure 28: Reference Circuits of STATUS

3.15. Behaviors of the RI*

You can configure RI behaviors flexibly. The default behavior of the RI is shown as below.

Table 26: Default Behaviors of the RI

State Response

Idle RI keeps at a high level.

URC RI outputs 120 ms low pulse when a new URC returns.

3.16. PCIe Interface

RG50xQ series module includes one PCIe interface which is in compliance with PCI Express
Specification Revision 3.0. The key features of the PCIe interface are as below:

⚫ PCI Express Specification Revision 3.0 compliant

⚫ Data rate at 8 Gbps/lane
⚫ Can be used to connect to an external WLAN IC

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Table 27: Pin Definition of PCIe Interface

Pin Name Pin No. I/O Description Comment

PCIe reference clock

PCIE_REFCLK_P 40 AIO
(+)
PCIe reference clock
PCIE_REFCLK_M 38 AIO
(-)

PCIE_TX0_M 44 AO PCIe transmit 0 (-)

PCIE_TX0_P 46 AO PCIe transmit 0 (+)

Requires differential impedance of
PCIE_TX1_M 41 AO PCIe transmit 1 (-)
85 Ω.
PCIE_TX1_P 43 AO PCIe transmit 1 (+) PCIe Gen3 compliant.

PCIE_RX0_M 32 AI PCIe receive 0 (-)

PCIE_RX0_P 34 AI PCIe receive 0 (+)

PCIE_RX1_M 35 AI PCIe receive 1 (-)

PCIE_RX1_P 37 AI PCIe receive 1 (+)

1.8 V power domain.

PCIE_CLKREQ 36 OD PCIe clock request In master mode, it is an input signal.
In slave mode, it is an output signal.
1.8 V power domain.
In master mode, it is an output
PCIE_RST 39 DIO PCIe reset
signal.
In slave mode, it is an input signal.
1.8 V power domain.
PCIE_WAKE 30 OD PCIe wake up In master mode, it is an input signal.
In slave mode, it is an output signal.

To enhance the reliability and availability in applications, follow the criteria below in the PCIe interface
circuit design:

⚫ Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
and 19.2 MHz clock signals.
⚫ Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫ Keep the maximum trace length less than 300 mm.
⚫ Keep the length matching of each differential data pair (Tx/Rx/REFCLK) less than 0.7 mm for PCIe
routing traces.
⚫ Keep the differential impedance of PCIe data trace as 85 Ω ±10 %.
⚫ You must not route PCIe data traces under components or cross them with other traces.

RG50xQ_Series_Hardware_Design 69 / 131
 5G Module Series

Table 28: PCIe Trace Length in RG500Q-CN

Pin No. Pin Name Length (mm) Length Difference (P-M)

40 PCIE_REFCLK_P 4.30
0.32
38 PCIE_REFCLK_M 3.98

46 PCIE_TX0_P 7.69
0.05
44 PCIE_TX0_M 7.64

43 PCIE_TX1_P 5.36
0.23
41 PCIE_TX1_M 5.13

34 PCIE_RX0_P 2.05
0.33
32 PCIE_RX0_M 1.72

37 PCIE_RX1_P 2.96
0.39
35 PCIE_RX1_M 2.57

Table 29: PCIe Trace Length in RG501Q-EU and RG502Q-EU

Pin No. Pin Name Length (mm) Length Difference (P-M)

40 PCIE_REFCLK_P 4.30
0.32
38 PCIE_REFCLK_M 3.98

46 PCIE_TX0_P 7.69
0.05
44 PCIE_TX0_M 7.64

43 PCIE_TX1_P 5.36
0.23
41 PCIE_TX1_M 5.13

34 PCIE_RX0_P 2.06
0.24
32 PCIE_RX0_M 1.70

37 PCIE_RX1_P 2.96
0.39
35 PCIE_RX1_M 2.57

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 5G Module Series

Table 30: PCIe Trace Length in RG500Q-EA and RG502Q-EA

Pin No. Pin Name Length (mm) Length Difference (P-M)

40 PCIE_REFCLK_P 6.55
0
38 PCIE_REFCLK_M 6.55

46 PCIE_TX0_P 9.59
0.01
44 PCIE_TX0_M 9.58

43 PCIE_TX1_P 8.83
0
41 PCIE_TX1_M 8.83

34 PCIE_RX0_P 3.34
0.01
32 PCIE_RX0_M 3.33

37 PCIE_RX1_P 4.00
0.02
35 PCIE_RX1_M 3.98

3.17. WWAN/WLAN Control Interface*

RG50xQ series module provides a WWAN/WLAN control interface for WLAN design. The following table
shows the pin definition.

Table 31: Pin Definition of WWAN/WLAN Control Interface

Pin Name Pin No. I/O Description Comment

COEX_UART_RXD 65 DI Coexistence UART receive Signal interface used

for WWAN/WLAN
coexistence
COEX_UART_TXD 67 DO Coexistence UART transmit
mechanism.
Notifies LAA/n79 transmission
HST_LAA_TX_EN 135 DO
from SDR transceiver to WLAN
1.8 V power domain.
Notifies WLAN transmission from
HST_WL_TX_EN 138 DI
WLAN to SDR transceiver

WLAN_PWR_EN1 216 DO Controls WLAN PA power 1.8 V power domain.

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 5G Module Series

Controls WLAN other power

WLAN_PWR_EN2 219 DO
(3.3 V or 1.8 V)

WLAN_EN 222 DO WLAN enable

WL_SW_CTRL 180 DI 38.4 MHz system clock request

1.8 V power domain.
WLAN_SLP_CLK 225 AO 32.768 kHz sleep clock output

RF_CLK3_WL 246 AO 38.4 MHz system clock output

Not used by default.

SDX_TO_WL_CTI 276 DO -
Keep it open.
GPIO from SDX to disable WLAN
WLAN_PA_MUTING 162 DO 1.8 V power domain.
PA
GPIO to allow WWAN to power on
WLAN 0.8 V AON domain, when
WLAN is sleeping or disabled.
WL_LAA_AS_EN 159 DO Additionally, the control logic in 1.8 V power domain.
WLAN AON domain allows SDR
to control 5G WLAN xLNA (LNA in
FEMs)
SoC signal to set 5G xLNA to high
gains or high isolation when both
WL_LAA_RX 201 DO chains (LAA/n79 and 5G WLAN) 1.8 V power domain.
are active simultaneously. No
individual control for each chain
Not used by default.
WL_TO_SDX 275 DI -
Keep it open.
Provides 0.95 V for
VDD_WIFI_VL 266, 267 PO
Wi-Fi/Bluetooth modules
Power supply for
Provides 1.35 V for
VDD_WIFI_VM 268 PO Wi-Fi/Bluetooth
Wi-Fi/Bluetooth modules
modules.
Provides 1.95 V for
VDD_WIFI_VH 269 PO
Wi-Fi/Bluetooth modules
Power supply for for
Provides 1.8 V for the
VDD_EXT 66 PO the Wi-Fi/Bluetooth
Wi-Fi/Bluetooth module’s I/O pins
module’s I/O pins.

3.18. Bluetooth Interface*

RG50xQ series module provides one Bluetooth interface. The following table shows the pin definition.

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Table 32: Pin Definition of the Bluetooth Interface

Pin Name Pin No. I/O Description Comment

Bluetooth enable
BT_EN 64 DO 1.8 V power domain.
control
In master mode, it is an output signal.
PCM_SYNC 71 DIO PCM data frame sync
In slave mode, it is an input signal.
In master mode, it is an output signal.
PCM_CLK 73 DIO PCM clock
In slave mode, it is an input signal.

PCM_IN 74 DI PCM data input If unused, keep it open.

PCM_OUT 76 DO PCM data output If unused, keep it open.

Bluetooth UART
BT_UART_TXD 59 DO
transmit
1.8 V power domain.
Bluetooth UART
BT_UART_RXD 63 DI
receive
DTE request to send Connect to DTE’s RTS; 1.8 V power
BT_UART_RTS 61 DI
signal to DCE domain.
DTE clear to send Connect to DTE’s CTS; 1.8 V power
BT_UART_CTS 62 DO
signal from DCE domain.

3.19. IPQ807x Status and Err Fatal Interfaces*

IPQ807x is an application processor. RG50xQ series module provides one IPQ807x status interface and
one Err Fatal interface multiplexed from Bluetooth UART to indicate the connection status and errors
between IPQ807x and the module.

Table 33: Pin Definition of IPQ807x Status and Err Fatal Interfaces

Pin Name Pin No. I/O Description Comment

BT_UART_TXD 59 DO module to AP status GPIO_63 of BB IC

BT_UART_RXD 63 DI AP to module status GPIO_64 of BB IC

BT_UART_RTS 61 DI AP to module err fatal GPIO_65 of BB IC

BT_UART_CTS 62 DO module to AP err fatal GPIO_66 of BB IC

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The following figure shows a reference design of RG50xQ series module with IPQ807x GPIO.

BT_UART_CTS SDX2AP_ERR_FATAL GPIO_33

BT_UART_RTS AP2SDX_ERR_FATAL GPIO_27

Module IPQ807x
BT_UART_TXD SDX2AP_STATUS GPIO_25

BT_UART_RXD AP2SDX_STATUS GPIO_26

Figure 29: RG50xQ Series Module with IPQ807x GPIO Application

NOTE

SDX2AP/AP2SDX_ERR_FATAL are not mandatory, and can be reserved.

3.20. SD Card Interface

RG50xQ series module provides one SD card interface which supports SD 3.0 protocol. The following
table shows the pin definition.

Table 34: Pin Definition of SD Card Interface

Pin Name Pin No. I/O Description Comment

1.8/2.95 V configurable
input.
SDIO_VDD 60 PI SDIO power supply
If unused, connect it to
VDD_EXT.

SDC1_DATA_0 49 DIO SDIO data bit 0

The power domain of SD
SDC1_DATA_1 50 DIO SDIO data bit 1
I/O pins depends on
SDIO_VDD.
SDC1_DATA_2 51 DIO SDIO data bit 2
If unused, keep them open.
SDC1_DATA_3 52 DIO SDIO data bit 3

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SDC1_CMD 48 DIO SDIO command

SDC1_CLK 47 DO SDIO clock

SDC1_PWR_EN 53 DO SDIO power supply enable

If unused, keep them open.
SDC1_PWR_
56 DO SDIO power domain set
VSET
Pull it up to VDD_EXT with
SDC1_DET 55 DI SD card hot-plug detect a 470 kΩ resistor.
If unused, keep it open.

The following figure shows a reference design of SD card interface.

VDD_2V95
SDIO_VDD_DUAL
SDC1_PWR_EN SDC1_PWR_EN LDO
LDO
SDC1_PWR_VSET

Module VDD_EXT SD Card Connector

SDIO_VDD VDD
C9 C8 C7 D8
R7 R8 R9 R10 R11 R12
1.0 μF 33 pF 10 pF
100K 100K 100K 100K 100K 470K
R1 0R
SDC1_DATA3 DATA3
R2 0R
SDC1_DATA2 DATA2
R3 0R
SDC1_DATA1 DATA1
R4 0R
SDC1_DATA0 DATA0
R5 0R
SDC1_CLK CLK
R6 0R
SDC1_CMD CMD

SDC1_DET DETECT
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 D7 C6 D6
NM NM NM NM NM NM VSS

Figure 30: Reference Circuit of SD Card Application

Follow the principles below in the SD card circuit design:

⚫ SDIO_VDD_DUAL is the external power supply for SDIO and can be used for SDIO pull-up, while
SDIO_VDD is the module’s power input pin for SDIO. The voltage range of VDD_2V95, power supply
for the SD card, is 2.7–3.6 V and it should provide a sufficient current of up to 0.8 A.
⚫ To avoid jitter of bus, pull up SDC1_CMD and SDC1_DATA_[0:3] to SDIO_VDD_DUAL with resistors
R7 to R11 respectively. Value range of these resistors should be 10–100 kΩ and the recommended
value is 100 kΩ.
⚫ To improve signal quality, add 0 Ω resistors R1 to R6 in series between the module and the SD card
connector. The bypass capacitors C1 to C6 are reserved and not mounted by default. Place all
resistors and bypass capacitors close to the SD card connector.
⚫ For good ESD protection, add a TVS diode on each SD card pin. The parasitic capacitance of ESD

RG50xQ_Series_Hardware_Design 75 / 131
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components should be smaller than 1.2 pF.

⚫ The load capacitance of SDIO bus should be less than 5.0 pF for SDR104 mode and less than 10 pF
for other speed modes.
⚫ Route the SDIO signal traces with ground surrounded. The impedance of SDIO data trace is 50 Ω
(±10 %).
⚫ Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DC-DC signals, etc.
⚫ Keep the trace length difference between SDC1_CLK and SDC1_DATA_[0:3]/ SDC1_CMD less than
2 mm and the total routing length less than 50 mm for SDR104 mode. For other speed modes, the
trace length difference between SDC1_CLK and SDC1_DATA_[0:3]/ SDC1_CMD should be less
than 6 mm and the total trace routing length less than 150 mm.
⚫ You must connect the DETECT pin of the SD card connector to the module if you want to use the SD
card function.

Table 35: SDC Trace Length in RG500Q-CN

Pin No. Pin Name Length (mm)

49 SDC1_DATA_0 17.56

50 SDC1_DATA_1 17.39

51 SDC1_DATA_2 17.67

52 SDC1_DATA_3 17.57

48 SDC1_CMD 17.71

47 SDC1_CLK 17.82

Table 36: SDC Trace Length in RG501Q-EU and RG502Q-EU

Pin No. Pin Name Length (mm)

49 SDC1_DATA_0 13.55

50 SDC1_DATA_1 13.55

51 SDC1_DATA_2 13.53

52 SDC1_DATA_3 13.57

48 SDC1_CMD 13.55

47 SDC1_CLK 13.56

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Table 37: SDC Trace Length in RG500Q-EA and RG502Q-EA

Pin No. Pin Name Length (mm)

49 SDC1_DATA_0 12.06

50 SDC1_DATA_1 11.91

51 SDC1_DATA_2 12.01

52 SDC1_DATA_3 12.13

48 SDC1_CMD 12.00

47 SDC1_CLK 12.01

3.21. Antenna Tuner Control Interface*

The module controls the external antenna tuner through GRFC signals. The following table shows the pin
definition of the interface.

Table 38: Pin Definition of GRFC Interface Used to Control Antenna Tuner

Pin Name Pin No. I/O Description Comment

SDR_GRFC15 171 DO
GRFC interface dedicated for If unused, keep them
external antenna tuner control open.
SDR_GRFC14 174 DO

3.22. SPI Interface

RG50xQ series module provides one SPI interface which only supports master mode with a maximum
clock frequency of up to 50 MHz.

Table 39: Pin Definition of SPI Interface

Pin Name Pin No. I/O Description Comment

SPI1_CLK 210 DO SPI1 clock 1.8 V power domain.

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SPI1_CS 207 DO SPI1 chip select Only master mode is

supported.
SPI1_MISO 213 DI SPI1 master-in slave-out

SPI1_MOSI 204 DO SPI1 master-out slave-in

The module provides a 1.8 V SPI interface. Use a level shifter between the module and the host if the
application is equipped with a 3.3 V processor or device interface. The following figure shows a reference
design.

VDD_EXT VCCA VCCB VDD_MCU

0.1 μF
0.1 μF
OE GND

SPI1_CS A1 B1 SPI_CS_N_MCU
Translator
SPI1_CLK A2 B2 SPI_CLK_MCU
SPI1_MOSI A3 B3 SPI_MOSI_MCU
SPI1_MISO A4 B4 SPI_MISO_MCU
NC NC

Figure 31: SPI Interface Reference Circuit with a Level Shifter

3.23. USB_BOOT Interface

RG50xQ series module provides a USB_BOOT pin. You can make the module enter emergency
download mode after power-on by pulling up USB_BOOT to VDD_EXT before powering on the module.
In this mode, the module supports firmware upgrade over USB 2.0 interface.

Table 40: Pin Definition of USB_BOOT Interface

Pin Name Pin No. I/O Description Comment

Forces the module into emergency

USB_BOOT 81 DI 1.8 V power domain.
download mode

The following figure shows a reference circuit of USB_BOOT interface.

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 5G Module Series

Module

VDD_EXT
Test points
10K
USB_BOOT

TVS TVS

Figure 32: Reference Circuit of USB_BOOT Interface

3.24. RGMII Interface

RG50xQ series module provides one RGMII interface, which can be connected with a PHY or MAC. The
following are the pin definition of RGMII interface and layout guidelines.

Table 41: Pin Definition of RGMII Interface

Pin Name Pin No. I/O Description Comment

RGMII management data

RGMII_MD_IO 10 OD
input/output

RGMII_MD_CLK 11 DO RGMII management data clock

RGMII_RX_0 13 DI RGMII receive data bit 0

RGMII_RX_1 14 DI RGMII receive data bit 1 The power domain of

RGMII I/O pins depends on
RGMII_CTL_RX 15 DI RGMII receive control RGMII_PWR_IN, which is
1.8 V or 2.5 V typically.
RGMII_RX_2 16 DI RGMII receive data bit 2
Single-ended impedance of
RGMII_RX_3 17 DI RGMII receive data bit 3 50 Ω.

RGMII_CK_RX 19 DI RGMII receive clock

RGMII_TX_0 20 DO RGMII transmit data bit 0

RGMII_CTL_TX 21 DO RGMII transmit control

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 5G Module Series

RGMII_TX_1 22 DO RGMII transmit data bit 1

RGMII_TX_2 23 DO RGMII transmit data bit 2

RGMII_CK_TX 24 DO RGMII transmit clock

RGMII_TX_3 25 DO RGMII transmit data bit 3

RGMII power enable control.

RGMII_PWR_EN 27 DO Controls external LDO to supply 1.8 V power domain.
1.8 V or 2.5 V
1.8 V or 2.5 V. If unused,
RGMII_PWR_IN 28 PI Power supply for RGMII I/O pins
connect it to VDD_EXT.

RGMII_INT 29 DI PHY interrupt output 1.8 V power domain.

Resets PHY chipset after

RGMII_RST 31 DO 1.8 V power domain.
power-on

The following figure shows a reference circuit of RGMII MAC to PHY interface.

VREG_RGMII
3.3 V
RGMII_PWR_EN
DC-DC 1.8 V or 2.5 V

4.7K
RGMII_PWR_IN VDDIO

MDIO
MDC

RGMII_TX_[0:3]
M
A
RGMII_CK_TX
Module C RGMII_CTL_TX PHY
RGMII_RX_[0:3]
RGMII_CK_RX
RGMII_CTL_RX
RGMII_INT
RGMII_RST

Figure 33: Reference Circuit of MAC to PHY Interface

The following figure shows a reference circuit of RGMII MAC to MAC interface.

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 5G Module Series

VREG_RGMII
3.3 V
DC-DC 1.8 V or 2.5 V
RGMII_PWR_EN

RGMII_PWR_IN VDDIO

RGMII_TX_[0:3]
RGMII_CK_TX
M RGMII_CTL_TX
A
Module C RGMII_RX_[0:3] MAC
RGMII_CK_RX
RGMII_CTL_RX

Figure 34: Reference Circuit of MAC to MAC Interface

Follow the principles below in the RGMII circuit design:

⚫ Keep RGMII signals away from sensitive circuits and signals, such as RF, audio, and clock signals.
⚫ Add resistors in series on Tx/Rx traces to ensure signal integrity. Place the resistors at the source of
signal.
⚫ Keep the trace length as short as possible. The length matching within Tx signals (RGMII_CK_TX to
RGMII_CTL_TX, RGMII_TX_[0:3]) or Rx signals (RGMII_CK_RX to RGMII_CTL_RX,
RGMII_RX_[0:3]) should be less than 2 mm.
⚫ The RGMII signal impedance should be 50 Ω ±10 %.
⚫ The spacing within Tx bus (RGMII_CK_TX to RGMII_CTL_TX, RGMII_TX_[0:3]) or Rx bus
(RGMII_CK_RX to RGMII_CTL_RX, RGMII_RX_[0:3]) should be at least 2.0 times the line width.
Spacing between Tx bus and Rx bus should be at least 2.5 times the line width. Spacing to all other
signals should be at least 3.0 times the line width. Meanwhile, each signal should be surrounded with
ground if the PCB space is sufficient.
⚫ To avoid electromagnetic interference, it is recommended to route the signal traces on inner layers
and make vias as few as possible.
⚫ The RGMII interface supports power input of 1.8 V or 2.5 V through RGMII_PWR_IN. Before using
this interface, enable it and configure its operating voltage through AT+QETH according to the actual
power input. For more details, see document [3] and [4].

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 5G Module Series

Table 42: RGMII Trace Length in RG500Q-CN

Pin No. Pin Name Length (mm)

13 RGMII_RX_0 10.65

14 RGMII_RX_1 10.23

15 RGMII_CTL_RX 10.37

16 RGMII_RX_2 10.10

17 RGMII_RX_3 10.59

19 RGMII_CK_RX 10.35

20 RGMII_TX_0 6.88

21 RGMII_CTL_TX 7.55

22 RGMII_TX_1 6.81

23 RGMII_TX_2 6.62

24 RGMII_CK_TX 7.10

25 RGMII_TX_3 6.66

Table 43: RGMII Trace Length in RG501Q-EU and RG502Q-EU

Pin No. Pin Name Length (mm)

13 RGMII_RX_0 10.65

14 RGMII_RX_1 10.18

15 RGMII_CTL_RX 10.37

16 RGMII_RX_2 10.10

17 RGMII_RX_3 10.59

19 RGMII_CK_RX 10.35

20 RGMII_TX_0 6.88

21 RGMII_CTL_TX 7.55

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 5G Module Series

22 RGMII_TX_1 6.81

23 RGMII_TX_2 6.62

24 RGMII_CK_TX 7.10

25 RGMII_TX_3 6.66

Table 44: RGMII Trace Length in RG500Q-EA and RG502Q-EA

Pin No. Pin Name Length (mm)

13 RGMII_RX_0 11.95

14 RGMII_RX_1 12.12

15 RGMII_CTL_RX 11.85

16 RGMII_RX_2 11.99

17 RGMII_RX_3 8.15

19 RGMII_CK_RX 11.72

20 RGMII_TX_0 9.31

21 RGMII_CTL_TX 9.57

22 RGMII_TX_1 9.45

23 RGMII_TX_2 9.46

24 RGMII_CK_TX 9.59

25 RGMII_TX_3 9.41

3.25. Time Service and Repeater Interface*

Time service provides time information for other devices or systems through standard or customized
interfaces and protocols. Its basic channels are shortwave, TV signals, cables, networks, satellites, base
stations, etc.

Repeater is a kind of wireless signal relay device, which amplifies the base station signal and then
transmits it to areas with weak signal coverage, expanding the network coverage.

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 5G Module Series

With GNSS time service and repeater functions, RG50xQ series can provide 1PPS pulse output, and can
execute time service through AT commands based on baseline SIB9 system messages. For more details,
see document [5] and [6].

Table 45: Pin Definition of Time Service and Repeater Function

Pin Name Pin No. I/O Description Comment

Supports time service and repeater

GPIO_32 98 DO functions and supports 1PPS pulse 1.8 V power domain.
output and frame synchronization

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 5G Module Series

4 GNSS
4.1. General Description

RG50xQ series module includes a fully integrated global navigation satellite system solution. It supports
dual-band GNSS. For details, see Chapter 5.2.

The module supports standard NMEA-0183 protocol, and outputs NMEA sentence at 1 Hz data update
rate via USB interface by default.

The GNSS engine of the module is switched off by default and can only be switched on via AT command.
For more details about GNSS engine technology and configurations, see document [7].

4.2. GNSS Performance

Table 46: GNSS Performance

Parameter Description Conditions Typ. Unit

Cold start Autonomous -146 dBm

Sensitivity
Reacquisition Autonomous -157 dBm
(GNSS)
Tracking Autonomous -158 dBm

Cold start
Autonomous 35 s
@ open sky
TTFF Warm start
Autonomous 28 s
(GNSS) @ open sky
Hot start
Autonomous 1.3 s
@ open sky
Accuracy Autonomous
CEP-50 2.5 m
(GNSS) @ open sky

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 5G Module Series

NOTE

1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep
positioning for at least 3 minutes continuously).
2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock
within 3 minutes after loss of lock.
3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position
successfully within 3 minutes after executing cold start command.

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 5G Module Series

5 Antenna Interfaces
RG50xQ series module includes eight, six or four cellular antenna interfaces, and one GNSS antenna interface. The impedance of antenna port is 50 Ω.

5.1. Cellular Antenna Interfaces & Frequency Bands

5.1.1. Pin Definition

Table 47: Pin Definition of Cellular Antenna Interfaces for RG500Q-EA/RG502Q-EA

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41 TRX1 & n79 DRX1
ANT0 121 AIO 50 Ω impedance
- LTE: LMHB_TRX
- WCDMA: LMHB_TRX
Antenna 1 interface:
- 5G NR: n41 DRX1 & n79 TRX1
ANT1 130 AIO 50 Ω impedance
- LTE: LB_TRX & LMHB_DRX
- WCDMA: LMHB_DRX

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 5G Module Series

Antenna 2 interface:
ANT2 139 AI 50 Ω impedance
- 5G NR: n79 DRX0
Antenna 3 interface:
ANT3 148 AIO 50 Ω impedance
- 5G NR: n79 TRX0
Antenna 4 interface:
ANT4 157 AIO - 5G NR: n77/78 TRX0 50 Ω impedance
- LTE: MHB_PRX MIMO & UHB_TRX
Antenna 5 interface:
ANT5 166 AIO - 5G NR: n41 TRX0 & n77/78 TRX1 50 Ω impedance
- LTE: UHB_PRX MIMO
Antenna 6 interface:
ANT6 175 AI - 5G NR: n41/n77/n78 DRX0 50 Ω impedance
- LTE: MHB_DRX MIMO & UHB_DRX
Antenna 7 interface:
ANT7 184 AIO - 5G NR: n77/78 DRX1 50 Ω impedance
- LTE: MHB_TRX1 & UHB_DRX MIMO

Table 48: Pin Definition of Cellular Antenna Interfaces for RG500Q-CN

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41/n78/n79 TRX1
ANT0 130 AIO 50 Ω impedance
- LTE: LMHB_TRX
- WCDMA: LMB_TRX

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 5G Module Series

Antenna 1 interface:
- 5G NR: n41 DRX1 & n78/n79 DRX0
ANT1 157 AI 50 Ω impedance
- LTE: LMHB_DRX
- WCDMA: LMB_DRX
Antenna 2 interface:
ANT2 166 AI - 5G NR: n41 DRX0 & n78/n79 DRX1 50 Ω impedance
- LTE: MB_PRX MIMO & HB_DRX MIMO
Antenna 3 interface:
ANT3 184 AIO - 5G NR: n41/n78/n79 TRX0 50 Ω impedance
- LTE: MB_DRX MIMO & HB_PRX MIMO

Table 49: Pin Definition of Cellular Antenna Interfaces for RG501Q-EU/RG502Q-EU

Pin Name Pin No. I/O Description Comment

Antenna 0 interface:
- 5G NR: n41/n77/n78 TRX1
ANT0 130 AIO 50 Ω impedance
- LTE: LMHB_TRX & UHB_PRX MIMO
- WCDMA: LMHB_TRX
Antenna 1 interface:
- 5G NR: n41 DRX1 & n77/n78 DRX1
ANT1 157 AI 50 Ω impedance
- LTE: LMHB_DRX & UHB_DRX MIMO
- WCDMA: LMHB_DRX
Antenna 2 interface:
ANT2 166 AI - 5G NR: n41 DRX0 & n77/n78 DRX0 50 Ω impedance
- LTE: LMHB_DRX MIMO & UHB_DRX

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 5G Module Series

Antenna 3 interface:
ANT3 184 AIO - 5G NR: n41/n77/n78 TRX0 50 Ω impedance
- LTE: LMHB_PRX MIMO & UHB_TRX & LMHB_TRX1
Antenna 4 interface:
ANT4 121 AI 50 Ω impedance
- LTE: B32_PRX (optional)
Antenna 5 interface:
ANT5 175 AI 50 Ω impedance
- LTE: B32_PRX MIMO (optional)

5.1.2. Cellular Antenna Mapping

Table 50: RG500Q-EA/RG502Q-EA Cellular Antenna Mapping

5G NR
MHB n77/78
Antenna WCDMA LTE LB (MHz) n79 (MHz) Pin No.
(MHz) (MHz)
Refarmed n41 n77/78/79

ANT0 LMHB_TRX LMHB_TRX LMHB_TRX TRX1 14 n79 DRX1 617–960 1452–2690 - 4400–5000 121

LMHB_DRX,
ANT1 LMHB_DRX LMHB_DRX DRX1 14 n79 TRX1 617–960 1452–2690 - 4400–5000 130
LB_TRX 15

ANT2 - - - - n79 DRX0 - - - 4400–5000 139

ANT3 - - - - n79 TRX0 - - - 4400–5000 148

MHB_PRX MIMO, MHB_PRX

ANT4 - - n77/78 TRX0 - 1452–2690 3300–4200 - 157
UHB 16_TRX MIMO

14 NR TRX1 = TX MIMO + PRX MIMO, NR DRX1 = DRX MIMO.

15 LTE LB_TRX is activated when 5G NR FDD low bands are supported in NSA mode.
16 LTE UHB frequency range: 3400–3800 MHz.

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 5G Module Series

ANT5 - UHB_PRX MIMO - TRX0 n77/78 TRX1 - 2496–2690 3300–4200 - 166

MHB_DRX MIMO, MHB_DRX

ANT6 - DRX0 n77/78 DRX0 - 1452–2690 3300–4200 - 175
UHB_DRX MIMO
MHB_TRX 17,
ANT7 - - - n77/78 DRX1 - 1710–2690 3300–4200 - 184
UHB_DRX MIMO

Table 51: RG500Q-CN Cellular Antenna Mapping

5G NR
LB MHB n78 n79
Antenna WCDMA LTE Pin No.
(MHz) (MHz) (MHz) (MHz)
Refarmed n41 n78/79

ANT0 LMB_TRX LMHB_TRX LMB_TRX TRX1 TRX1 703–960 1710–2690 3300–3800 4400–5000 130

ANT1 LMB_DRX LMHB_DRX LMB_DRX DRX1 DRX0 703–960 1710–2690 3300–3800 4400–5000 157

MB_PRX MIMO, MB_PRX

ANT2 - DRX0 DRX1 - 1710–2690 3300–3800 4400–5000 166
HB_DRX MIMO MIMO
MB_DRX MIMO, MB_DRX
ANT3 - TRX0 TRX0 - 1710–2690 3300–3800 4400–5000 184
HB_PRX MIMO MIMO

17 LTE MHB_TRX is activated when 5G NR FDD middle/high bands are supported in NSA mode.

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Table 52: RG501Q-EU/RG502Q-EU Cellular Antenna Mapping

5G NR
LB MHB
Antenna WCDMA LTE n77/78 (MHz) Pin No.
(MHz) (MHz)
Refarmed n41 n77/78

LMHB_TRX,
ANT0 LMHB_TRX UHB 18_PRX LMHB_TRX TRX1 TRX1 617–960 1452–2690 3300–4200 130
MIMO
LMHB_DRX,
ANT1 LMHB_DRX UHB 18_DRX LMHB_DRX DRX1 DRX1 617–960 1452–2690 3300–4200 157
MIMO
LMHB_DRX
LMHB_DRX
ANT2 - MIMO 19, DRX0 DRX0 617–960 1452–2690 3300–4200 166
MIMO
UHB 18_DRX
LMHB_PRX
MIMO 19, LMHB_PRX
ANT3 - TRX0 TRX0 617–960 1452–2690 3300–4200 184
UHB 18_TRX, MIMO
LMHB 20_TRX1

ANT4 - B32_PRX - - - - 1452–1496 - 121

B32_PRX
ANT5 - - - - - 1452–1496 - 175
MIMO

18 LTE UHB frequency range: 3400–3800 MHz.

19 Mandatory for LB + LB EN-DC & CA, reserved for LB 4 × 4 MIMO.
20 LTE LMHB_TRX1 is activated when 5G NR FDD low/middle/high bands are supported in NSA mode.

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5.1.3. Operating Frequency

Table 53: RG500Q-EA/RG502Q-EA Module Operating Frequencies

Transmit Receive
Band Name LTE-FDD LTE-TDD UMTS 5G NR
(MHz) (MHz)

IMT (2100) 1920–1980 2110–2170 B1 - B1 n1

DCS (1800) 1710–1785 1805–1880 B3 - B3 n3

Cell (850) 824–849 869–894 B5 - B5 n5

JCELL (800) 830–840 875–885 - - B6 -

IMT-E (2600) 2500–2570 2620–2690 B7 - - n7

EGSM (950) 880–915 925–960 B8 - B8 n8

B18 815–830 860–875 B18 - - -

B19 830–845 875–890 B19 - B19 -

EU800 832–862 791–821 B20 - - n20

B26 814–849 859–894 B26 - - -

700 APAC 703–748 758–803 B28 - - n28

L-band - 1452–1496 B32 - - -

B34 2010–2025 2010–2025 - B34 - -

B38 2570–2620 2570–2620 - B38 - n38

B39 1880–1920 1880–1920 - B39 - -

B40 2300–2400 2300–2400 - B40 - n40

B41/B41-XGP 2496–2690 2496–2690 - B41 - n41

B42 3400–3600 3400–3600 - B42 - -

B43 3600–3800 3600–3800 - B43 - -

n77 3300–4200 3300–4200 - - - n77

n78 3300–3800 3300–3800 - - - n78

n79 4400–5000 4400–5000 - - - n79

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Table 54: RG500Q-CN Module Operating Frequencies

Transmit Receive
Band Name LTE-FDD LTE-TDD UMTS 5G NR
(MHz) (MHz)

IMT (2100) 1920~1980 2110~2170 B1 - B1 n1

DCS (1800) 1710~1785 1805~1880 B3 - - -

Cell (850) 824~849 869~894 B5 -

EGSM (950) 880~915 925~960 B8 - B8

700 APAC 703~748 758~803 - - n28

B34 2010~2025 2010~2025 - B34 - -

B38 2570~2620 2570~2620 - B38 -

B39 1880~1920 1880~1920 - B39 - -

B40 2300~2400 2300~2400 - B40 -

B41/B41-XGP 2496~2690 2496~2690 - B41 - n41

n78 3300~3800 3300~3800 - - - n78

n79 4400~5000 4400~5000 - - - n79

Table 55: RG501Q-EU/RG502Q-EU Module Operating Frequencies

Transmit Receive
Band Name LTE-FDD LTE-TDD UMTS 5G NR
(MHz) (MHz)

IMT (2100) 1920–1980 2110–2170 B1 - B1 n1

DCS (1800) 1710–1785 1805–1880 B3 - B3 n3

Cell (850) 824–849 869–894 B5 - B5 n5

IMT-E (2600) 2500–2570 2620–2690 B7 - - n7

EGSM (950) 880–915 925–960 B8 - B8 n8

EU800 832–862 791–821 B20 - - n20

700 APAC 703–748 758–803 B28 - - n28

L-band - 1452–1496 B32 - - -

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B38 2570–2620 2570–2620 - B38 - n38

B40 2300–2400 2300–2400 - B40 - n40

B41/B41-XGP 2496–2690 2496–2690 - B41 - n41

B42 3400–3600 3400–3600 - B42 - -

B43 3600–3800 3600–3800 - B43 - -

n77 3300–4200 3300–4200 - - - n77

n78 3300–3800 3300–3800 - - - n78

5.1.4. Reference Design of Cellular Antenna Interface

A reference design of cellular antenna pad is shown as below. Reserve a π-type matching circuit for
better cellular performance. The capacitors are not mounted by default.

Module

R1 0R
ANT0
C1 C2
NM NM
……
……

R7 0R
ANT7
C13 C14
NM NM

Figure 35: Reference Circuit of RF Antenna

NOTE

1. Use a π-type circuit for all the antenna circuits to facilitate future debugging.
2. Keep the impedance of the cellular antennas (ANT0–ANT7) traces as 50 Ω when routing.
3. Keep at least 15 dB isolation between RF antennas to improve the receiving sensitivity, and at least
20 dB isolation between 5G NR UL MIMO antennas.
4. Keep 75 dB isolation between each two antenna traces.

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5. Keep digital circuits such as switch mode power supply, (U)SIM card, USB interface, camera module,
display connector and SD card away from the antenna traces.

5.2. GNSS Antenna Interfaces & Frequency Bands

Table 56: Pin Definition of GNSS Antenna Interface

Pin Name Pin No. I/O Description Comment

ANT_GNSS 193 AI GNSS antenna interface 50 Ω impedance

Table 57: GNSS Frequency

Type Frequency Unit

1575.42 ±1.023 (L1)

GPS/Galileo/QZSS MHz
1176.45 ±10.23 (L5)
1575.42 ±2.046 (E1)
Galileo MHz
1176.45 ±10.23 (E5a)
1575.42 (L1)
QZSS MHz
1176.45 (L5)

GLONASS 1597.5–1605.8 MHz

BeiDou 1561.098 ±2.046 MHz

A reference design of GNSS antenna is shown as below.

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VDD
GNSS
Antenna

0.1 μF
10R
Module
47 nH

0R 100 pF
ANT_GNSS

NM NM

Figure 36: Reference Circuit of GNSS Antenna

NOTE
1. You can select an external LDO for power supply according to the active antenna requirements.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
3. Keep the characteristic impedance for ANT_GNSS trace as 50 Ω.
4. Place the π-type matching components as close to the antenna as possible.
5. Keep digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card
away from the antenna traces.
6. Keep 75 dB isolation between GNSS and cellular antenna traces.
7. Keep 15 dB isolation between GNSS and cellular antennas to improve the receiving sensitivity.

5.3. RF Routing Guidelines

For the PCB, control the characteristic impedance of all RF traces to 50 Ω. The impedance of the RF
traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the
reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip
or coplanar waveguide is typically used in RF layout to control characteristic impedance. The following
are reference designs of microstrip or coplanar waveguide with different PCB structures.

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Figure 37: Microstrip Line Design on a 2-layer PCB

Figure 38: Coplanar Waveguide Line Design on a 2-layer PCB

Figure 39: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)

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Figure 40: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)

To ensure RF performance and reliability, follow the principles below in RF layout design:

⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to
50 Ω.
⚫ The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
⚫ The distance between the RF pins and the RF connector should be as short as possible and all the
right-angle traces should be changed to curved ones. The recommended trace angle is 135°.
⚫ Reserve clearance under the signal pin of the antenna connector or solder joint.
⚫ The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W).
⚫ Keep RF traces away from interference sources, and avoid intersection and paralleling between
traces on adjacent layers.

For more details about RF layout, see document [8].

5.4. Antenna Installation

5.4.1. Antenna Design Requirement

Table 58: Antenna Requirements

Type Requirements

⚫ Frequency range 1: 1559–1606 MHz

⚫ Frequency range 2: 1166–1187 MHz
GNSS ⚫ Polarization: RHCP or linear
⚫ VSWR: < 2 (typ.)
⚫ Passive antenna gain: > 0 dBi

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⚫ VSWR: ≤ 3
⚫ Efficiency: > 30 %
⚫ Input Impedance: 50 Ω
⚫ Cable insertion loss: < 1 dB
WCDMA B5/B6/B8/B19
LTE B5/B8/B12/B13/B14/B17/B18/B19/B20/B26/B28/B29/B71
5G NR n5/n8/n12/n20/n28/n71
WCDMA/LTE/5G NR
⚫ Cable insertion loss: < 1.5 dB
WCDMA B1/B2/B3/B4
LTE B1/B2/B3/B4/B25/B32/B34/B39/B66
5G NR n1/n2/n3/n25/n66
⚫ Cable insertion loss: < 2 dB
LTE B7/B30/B38/B40/B41/B42/B43/B46/B48
5G NR n7/n38/n40/n41/n48/n77/n78/n79

5.4.2. RF Connector Recommendation

The receptacle dimensions are illustrated as below.

Figure 41: Dimensions of the Receptacles (Unit: mm)

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The following figure shows the specifications of mating plugs using Ø0.81 mm coaxial cables.

Figure 42: Specifications of Mating Plugs Using Ø0.81 mm Coaxial Cables (Unit: mm)

5.4.3. Recommended RF Connector for Installation

5.4.3.1. Assemble Coaxial Cable Plug Manually

The illustration for plugging in a coaxial cable plug is shown below, θ = 90°is acceptable, while θ ≠ 90°is
not.

Figure 43: Plug in a Coaxial Cable Plug

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The illustration of pulling out the coaxial cable plug is shown below, θ = 90°is acceptable, while θ ≠ 90°is
not.

Figure 44: Pull out a Coaxial Cable Plug

5.4.3.2. Assemble Coaxial Cable Plug with Fixture

The pictures of installing the coaxial cable plug with a fixture is shown below, θ = 90°is acceptable, while
θ ≠ 90°is not.

Figure 45: Install the Coaxial Cable Plug with Fixture

5.4.4. Recommended Manufacturers of RF Connector and Cable

For more details, visit https://www.i-pex.com.

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6 Reliability, Radio and Electrical

Characteristics

6.1. Absolute Maximum Ratings

Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.

Table 59: Absolute Maximum Ratings

Parameter Min. Max. Unit

VBAT_RF/VBAT_BB -0.5 6.0 V

USB_VBUS -0.3 5.5 V

Peak Current of VBAT_BB - TBD A

Peak Current of VBAT_RF - TBD A

Voltage at Digital Pins -0.5 2.2 V

Voltage at ADC0 -0.5 2.2 V

6.2. Power Supply Ratings

Table 60: Module Power Supply Ratings

Parameter Description Conditions Min. Typ. Max. Unit

VBAT_BB and The actual input voltages must be

VBAT 3.3 3.8 4.3 V
VBAT_RF1 kept between the minimum and

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maximum values.

6.3. Operating and Storage Temperatures

Table 61: Operating and Storage Temperatures

Parameter Temperature Range

21
Operating Temperature Range -30 to +75 °C

22
Extended Temperature Range -40 to +85 °C

Storage Temperature Range -40 to +90 °C

6.4. Power Consumption

Table 62: RG500Q-EA/RG502Q-EA Current Consumption

Description Conditions Typ. Unit

OFF state Power down 45 μA

AT+CFUN=0 (USB disconnected) 1.5 mA

WCDMA PF = 64 (USB disconnected) 4.62 mA

WCDMA PF = 128 (USB disconnected) 4.04 mA

Sleep state
WCDMA PF = 512 (USB disconnected) 3.69 mA

LTE-FDD PF = 32 (USB disconnected) 6.92 mA

LTE-FDD PF = 64 (USB disconnected) 5.10 mA

21 To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding
passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications.
22 To meet this extended temperature range, you need to ensure effective thermal dissipation, for example, by adding

passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module remains the ability to establish
and maintain functions such as voice, SMS, emergency call, etc., without any unrecoverable malfunction. Radio spectrum
and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value,
exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the
module will meet 3GPP specifications again.

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LTE-FDD PF = 128 (USB disconnected) 4.28 mA

LTE-TDD PF = 32 (USB disconnected) 6.99 mA

LTE-TDD PF = 64 (USB disconnected) 5.29 mA

LTE-TDD PF = 128 (USB disconnected) 4.30 mA

SA-FDD PF = 32 (USB disconnected) 12.75 mA

SA-FDD PF = 64 (USB disconnected) 7.04 mA

SA-FDD PF = 128 (USB disconnected) 4.32 mA

SA-FDD PF = 256 (USB disconnected) 3.19 mA

SA-TDD PF = 32 (USB disconnected) 12.59 mA

SA-TDD PF = 64 (USB disconnected) 7.1 mA

SA-TDD PF = 128 (USB disconnected) 4.16 mA

SA-TDD PF = 256 (USB disconnected) 3.13 mA

WCDMA PF = 64 (USB disconnected) 21.59 mA

WCDMA PF = 64 (USB 3.0 connected) 53.86 mA

LTE-FDD PF = 64 (USB disconnected) 23.04 mA

LTE-FDD PF = 64 (USB 3.0 connected) 55.35 mA

LTE-TDD PF = 64 (USB disconnected) 23.25 mA

Idle state
LTE-TDD PF = 64 (USB 3.0 connected) 55.45 mA

SA-FDD PF = 64 (USB disconnected) 24.99 mA

SA-FDD PF = 64 (USB 3.0 connected) 54.18 mA

SA-TDD PF = 64 (USB disconnected) 25.44 mA

SA-TDD PF = 64 (USB 3.0 connected) 54.92 mA

WCDMA B1 HSDPA CH10700 @ 23 dBm 595 mA

WCDMA
WCDMA B1 HSUPA CH10700 @ 23 dBm 550 mA
(GNSS OFF)
WCDMA B3 HSDPA CH1338 @ 23 dBm 630 mA

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WCDMA B3 HSUPA CH1338 @ 23 dBm 630 mA

WCDMA B5 HSDPA CH4407 @ 23 dBm 390 mA

WCDMA B5 HSUPA CH4407 @ 23 dBm 390 mA

WCDMA B6 HSDPA CH4400 @ 23 dBm 385 mA

WCDMA B6 HSUPA CH4400 @ 23 dBm 390 mA

WCDMA B8 HSDPA CH3012 @ 23 dBm 430 mA

WCDMA B8 HSUPA CH3012 @ 23 dBm 420 mA

WCDMA B19 HSDPA CH738 @ 23 dBm 380 mA

WCDMA B19 HSUPA CH738 @ 23 dBm 395 mA

LTE-FDD B1 CH18300 @ 23 dBm 750 mA

LTE-FDD B3 CH19575 @ 23 dBm 955 mA

LTE-FDD B5 CH20525 @ 23 dBm 480 mA

LTE-FDD B7 CH21100 @ 23 dBm 650 mA

LTE-FDD B8 CH21625 @ 23 dBm 525 mA

LTE-FDD B18 CH23925 @ 23 dBm 535 mA

LTE-FDD B19 CH24075 @ 23 dBm 505 mA

LTE-FDD B20 CH24300 @ 23 dBm 505 mA

LTE
(GNSS OFF)
LTE-FDD B26 CH26865 @ 23 dBm 510 mA

LTE-FDD B28 CH27640 @ 23 dBm 510 mA

LTE-TDD B34 CH36275 @ 23 dBm 335 mA

LTE-TDD B38 CH38000 @ 23 dBm 415 mA

LTE-TDD B39 CH38450 @ 23 dBm 365 mA

LTE-TDD B40 CH39150 @ 23 dBm 355 mA

LTE-TDD B41 CH40620 @ 23 dBm 410 mA

LTE-TDD B42 CH42590 @ 23 dBm 430 mA

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LTE-TDD B43 CH44590 @ 23 dBm 385 mA

5G NR FDD n1 CH390000 @ 23 dBm 620 mA

5G NR FDD n3 CH349500 @ 23 dBm 675 mA

5G NR FDD n5 CH167300 @ 23 dBm 460 mA

5G NR FDD n7 CH507000 @ 23 dBm 630 mA

5G NR FDD n8 CH179500 @ 23 dBm 465 mA

5G NR FDD n20 CH169400 @ 23 dBm 435 mA

5G NR SA
5G NR FDD n28 CH145100 @ 23 dBm 425 mA
(GNSS OFF)
5G NR TDD n38 CH519000 @ 23 dBm 280 mA

5G NR TDD n40 CH470000 @ 23 dBm 325 mA

5G NR TDD n41 CH518598 @ 23 dBm 425 mA

5G NR TDD n77 CH650000 @ 23 dBm 465 mA

5G NR TDD n78 CH636666 @ 23 dBm 440 mA

5G NR TDD n79 CH713990 @ 23 dBm 470 mA

WCDMA B1 CH10700 @ 23 dBm 675 mA

WCDMA B3 CH1338 @ 23 dBm 680 mA

WCDMA B5 CH4408 @ 23 dBm 440 mA

WCDMA
voice call
WCDMA B6 CH4175 @ 23 dBm 405 mA

WCDMA B8 CH3012 @ 23 dBm 475 mA

WCDMA B19 CH338 @ 23 dBm 415 mA

Table 63: RG500Q-CN Current Consumption

Description Conditions Typ. Unit

OFF state Power down 45 μA

Sleep state AT+CFUN=0 (USB disconnected) 1.5 mA

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WCDMA PF = 64 (USB disconnected) 3.5 mA

WCDMA PF = 128 (USB disconnected) 2.5 mA

WCDMA PF = 512 (USB disconnected) 2.0 mA

LTE-FDD PF = 32 (USB disconnected) 5.0 mA

LTE-FDD PF = 64 (USB disconnected) 3.2 mA

LTE-FDD PF = 128 (USB disconnected) 2.5 mA

LTE-TDD PF = 32 (USB disconnected) 5.1 mA

LTE-TDD PF = 64 (USB disconnected) 3.5 mA

LTE-TDD PF = 128 (USB disconnected) 2.5 mA

SA-FDD PF = 32 (USB disconnected) 14.5 mA

SA-FDD PF = 64 (USB disconnected) 8.5 mA

SA-FDD PF = 128 (USB disconnected) 5.8 mA

SA-FDD PF = 256 (USB disconnected) 4.5 mA

SA-TDD PF = 32 (USB disconnected) 14.8 mA

SA-TDD PF = 64 (USB disconnected) 8.6 mA

SA-TDD PF = 128 (USB disconnected) 6.2 mA

SA-TDD PF = 256 (USB disconnected) 4.6 mA

WCDMA PF = 64 (USB disconnected) 17.6 mA

WCDMA PF = 64 (USB 3.0 connected) 49.5 mA

LTE-FDD PF = 64 (USB disconnected) 18.3 mA

LTE-FDD PF = 64 (USB 3.0 connected) 50.4 mA

Idle state
LTE-TDD PF = 64 (USB disconnected) 18.4 mA

LTE-TDD PF = 64 (USB 3.0 connected) 50.5 mA

SA-FDD PF = 64 (USB disconnected) 24.6 mA

SA-FDD PF = 64 (USB 3.0 connected) 56.8 mA

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SA-TDD PF = 64 (USB disconnected) 26.2 mA

SA-TDD PF = 64 (USB 3.0 connected) 57.1 mA

WCDMA B1 HSDPA CH10700 @ 23 dBm 580 mA

WCDMA B1 HSUPA CH10700 @ 23 dBm 580 mA

WCDMA
(GNSS OFF)
WCDMA B8 HSDPA CH3012 @ 23 dBm 480 mA

WCDMA B8 HSUPA CH3012 @ 23 dBm 480 mA

LTE-FDD B1 CH300 @ 23 dBm 810 mA

LTE-FDD B3 CH1575 @ 23 dBm 890 mA

LTE-FDD B5 CH2525 @ 23 dBm 610 mA

LTE-FDD B8 CH3625 @ 23 dBm 560 mA

LTE
LTE-FDD B34 CH36275 @ 23 dBm 390 mA
(GNSS OFF)
LTE-TDD B38 CH38000 @ 23 dBm 510 mA

LTE-TDD B39 CH38450 @ 23 dBm 370 mA

LTE-TDD B40 CH39150 @ 23 dBm 530 mA

LTE-TDD B41 CH40620 @ 23 dBm 470 mA

5G NR FDD n1 CH390000 @ 23 dBm 750 mA

5G NR FDD n28 CH145100 @ 23 dBm 600 mA

5G NR SA
5G NR TDD n41 CH518598 @ 26 dBm 620 mA
(GNSS OFF)
5G NR TDD n78 CH636666 @ 26 dBm 570 mA

5G NR TDD n79 CH713990 @ 26 dBm 600 mA

WCDMA B1 CH10700 @ 23 dBm 650 mA

WCDMA
voice call
WCDMA B8 CH3012 @ 23 dBm 500 mA

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Table 64: RG501Q-EU/RG502Q-EU Current Consumption

Description Conditions Typ. Unit

OFF state Power down 45 μA

AT+CFUN=0 (USB disconnected) 1.5 mA

WCDMA PF = 64 (USB disconnected) 3.3 mA

WCDMA PF = 128 (USB disconnected) 2.7 mA

WCDMA PF = 512 (USB disconnected) 2.3 mA

LTE-FDD PF = 32 (USB disconnected) 5.4 mA

LTE-FDD PF = 64 (USB disconnected) 3.9 mA

LTE-FDD PF = 128 (USB disconnected) 2.9 mA

LTE-TDD PF = 32 (USB disconnected) 5.4 mA

Sleep state
LTE-TDD PF = 64 (USB disconnected) 3.8 mA

LTE-TDD PF = 128 (USB disconnected) 2.9 mA

SA-FDD PF = 32 (USB disconnected) 13.1 mA

SA-FDD PF = 64 (USB disconnected) 7.5 mA

SA-FDD PF = 128 (USB disconnected) 4.8 mA

SA-TDD PF = 32 (USB disconnected) 13.2 mA

SA-TDD PF = 64 (USB disconnected) 7.5 mA

SA-TDD PF = 128 (USB disconnected) 4.9 mA

WCDMA PF = 64 (USB disconnected) 18.3 mA

WCDMA PF = 64 (USB 3.0 connected) 49.5 mA

LTE-FDD PF = 64 (USB disconnected) 20.1 mA

Idle state
LTE-FDD PF = 64 (USB 3.0 connected) 50.6 mA

LTE-TDD PF = 64 (USB disconnected) 19.8 mA

LTE-TDD PF = 64 (USB 3.0 connected) 50.4 mA

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SA-FDD PF = 64 (USB disconnected) 23.8 mA

SA-FDD PF = 64 (USB 3.0 connected) 54.1 mA

SA-TDD PF = 64 (USB disconnected) 23.9 mA

SA-TDD PF = 64 (USB 3.0 connected) 54.2 mA

WCDMA B1 HSDPA CH10700 @ 23 dBm 530 mA

WCDMA B1 HSUPA CH10700 @ 23 dBm 539 mA

WCDMA B5 HSDPA CH4407 @ 23 dBm 378 mA

WCDMA
(GNSS OFF)
WCDMA B5 HSUPA CH4407 @ 23 dBm 382 mA

WCDMA B8 HSDPA CH3012 @ 23 dBm 414 mA

WCDMA B8 HSUPA CH3012 @ 23 dBm 418 mA

LTE-FDD B1 CH18300 @ 23 dBm 688 mA

LTE-FDD B3 CH19575 @ 23 dBm 609 mA

LTE-FDD B5 CH20525 @ 23 dBm 475 mA

LTE-FDD B7 CH21100 @ 23 dBm 838 mA

LTE-FDD B8 CH21625 @ 23 dBm 507 mA

LTE-FDD B20 CH24300 @ 23 dBm 548 mA

LTE
(GNSS OFF)
LTE-FDD B28 CH27640 @ 23 dBm 581 mA

LTE-TDD B38 CH38000 @ 23 dBm 379 mA

LTE-TDD B40 CH39150 @ 23 dBm 391 mA

LTE-TDD B41 CH40620 @ 23 dBm 360 mA

LTE-TDD B42 CH42590 @ 23 dBm 462 mA

LTE-TDD B43 CH44590 @ 23 dBm 427 mA

5G NR FDD n1 CH390000 @ 23 dBm 589 mA

5G NR SA
5G NR FDD n3 CH349500 @ 23 dBm 597 mA
(GNSS OFF)
5G NR FDD n5 CH167300 @ 23 dBm 473 mA

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5G NR FDD n7 CH507000 @ 23 dBm 733 mA

5G NR FDD n8 CH179500 @ 23 dBm 450 mA

5G NR FDD n20 CH169400 @ 23 dBm 508 mA

5G NR FDD n28 CH145100 @ 23 dBm 486 mA

5G NR TDD n38 CH519000 @ 23 dBm 286 mA

5G NR TDD n40 CH470000 @ 23 dBm 354 mA

5G NR TDD n41 CH518598 @ 23 dBm 512 mA

5G NR TDD n77 CH650000 @ 23 dBm 508 mA

5G NR TDD n78 CH636666 @ 23 dBm 517 mA

WCDMA B1 CH10700 @ 23 dBm 565 mA

WCDMA
WCDMA B5 CH4408 @ 23 dBm 410 mA
voice call
WCDMA B8 CH3012 @ 23 dBm 464 mA

6.5. Tx Power

Table 65: RF Output Power

Mode Frequency Max. Min.

WCDMA WCDMA bands 24 dBm +1/-3 dB (Class 3) < -50 dBm

LTE bands 23 dBm ±2 dB (Class 3) < -40 dBm

LTE LTE HPUE bands
23
26 dBm ±2 dB (Class 2) < -40 dBm
(B38/B40/B41/B42/B43)

5G NR bands 23 dBm ±2 dB (Class 3) < -40 dBm 24

5G NR 5G NR HPUE bands
26 dBm +2/-3 dB (Class 2) < -40 dBm 24
(n41/n77/n78/n79) 25

23 RG50xQ-EU only supports the HPUE of B42.

24 For 5G NR bands, they have different standards for different channel bandwidth. See the specifications as described in
Clause 6.3.1 of TS 38.101-1 [2].
25 n79 HPUE is not supported by RG50xQ-EU.

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6.6. Rx Sensitivity

Table 66: RG500Q-EA/RG502Q-EA Conducted RF Receiving Sensitivity

26
3GPP
Mode Frequency Primary Diversity SIMO
(SIMO)

WCDMA B1 -109 dBm -109.5 dBm -111 dBm -106.7 dBm

WCDMA B3 -108 dBm -109 dBm -110.5 dBm -103.7 dBm

WCDMA B5 -109.5 dBm -109.5 dBm -111 dBm -104.7 dBm

WCDMA
WCDMA B6 -109.5 dBm -110 dBm -111 dBm -106.7 dBm

WCDMA B8 -110 dBm -110 dBm -111.5 dBm -103.7 dBm

WCDMA B19 -109.5 dBm -110 dBm -111.5 dBm -106.7 dBm

LTE-FDD B1 (10 MHz) -97.5 dBm -97.5 dBm -100 dBm -97.0 dBm

LTE-FDD B3 (10 MHz) -97.0 dBm -97.0 dBm -99.5 dBm -94.0 dBm

LTE-FDD B5 (10 MHz) -99.0 dBm -100 dBm -102.5 dBm -95.0 dBm

LTE-FDD B7 (10 MHz) -97.0 dBm -97.5 dBm -100 dBm -95.0 dBm

LTE-FDD B8 (10 MHz) -99.5 dBm -100.5 dBm -103 dBm -94.0 dBm

LTE-FDD B18 (10 MHz) -99.0 dBm -100.5 dBm -103 dBm -97.0 dBm

LTE-FDD B19 (10 MHz) -99.0 dBm -100.5 dBm -103 dBm -97.0 dBm
LTE
LTE-FDD B20 (10 MHz) -99.5 dBm -100.5 dBm -103 dBm -94.0 dBm

LTE-FDD B26 (10 MHz) -99.5 dBm -100.5 dBm -102 dBm -94.5 dBm

LTE-FDD B28 (10 MHz) -99.0 dBm -100.5 dBm -102 dBm -95.5 dBm

LTE-TDD B34 (10 MHz) -97.0 dBm -97.5 dBm -101 dBm -97.0 dBm

LTE-TDD B38 (10 MHz) -97.0 dBm -97.0 dBm -100 dBm -97.0 dBm

LTE-TDD B39 (10 MHz) -97.0 dBm -98.0 dBm -100.5 dBm -97.0 dBm

LTE-TDD B40 (10 MHz) -96.0 dBm -96.5 dBm -99.0 dBm -97.0 dBm

26 For the SIMO receiving sensitivity, WCDMA and LTE bands are tested with 2 Rx antennas while 5G n41/77/78/79 bands
are tested with 4 Rx antennas.

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LTE-TDD B41 (10 MHz) -96.0 dBm -96.0 dBm -99.0 dBm -95.0 dBm

LTE-TDD B42 (10 MHz) -96.5 dBm -97.5 dBm -99.0 dBm -96.0 dBm

LTE-TDD B43 (10 MHz) TBD TBD TBD -96.0 dBm

5G NR FDD n1 (20 MHz) TBD TBD -94 dBm -93.5 dBm

5G NR FDD n3 (20 MHz) TBD TBD -95 dBm -90.8 dBm

5G NR FDD n5 (20 MHz) TBD TBD -100 dBm -90.8 dBm

5G NR FDD n7 (20 MHz) TBD TBD -95 dBm -91.8 dBm

5G NR FDD n8 (20 MHz) TBD TBD -101 dBm -90.0 dBm

5G NR FDD n20 (20 MHz) TBD TBD -101 dBm -89.8 dBm

5G NR 5G NR FDD n28 (20 MHz) TBD TBD -102 dBm -90.8 dBm

5G NR TDD n38 (20 MHz) TBD TBD -100.5 dBm -93.8 dBm

5G NR TDD n40 (20 MHz) TBD TBD -95 dBm -93.8 dBm

5G NR TDD n41 (100 MHz) TBD TBD -91.0 dBm -87.4 dBm

5G NR TDD n77 (100 MHz) TBD TBD -91.5 dBm -87.8 dBm

5G NR TDD n78 (100 MHz) TBD TBD -92.5 dBm -87.8 dBm

5G NR TDD n79 (100 MHz) TBD TBD -91.5 dBm -87.8 dBm

Table 67: RG500Q-CN Conducted RF Receiving Sensitivity

27
Mode Frequency Primary Diversity SIMO 3GPP (SIMO)

WCDMA B1 -109 -109 -112 -106.7 dBm

WCDMA
WCDMA B8 -109 -109 -112 -103.7 dBm

LTE-FDD B1 (10 MHz) -97 -97.5 -100 -97.0 dBm

LTE LTE-FDD B3 (10 MHz) -97 -98 -100 -94.0 dBm

LTE-FDD B5 (10 MHz) -99 -100 -102 -95.0 dBm

27 For the SIMO receiving sensitivity, WCDMA and LTE bands are tested with 2 Rx antennas while 5G n41/77/78/79 bands
are tested with 4 Rx antennas.

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LTE-FDD B8 (10 MHz) -99 -100 -102 -94.0 dBm

LTE-TDD B34 (10 MHz) -97.5 -99.5 -101 -97.0 dBm

LTE-TDD B38 (10 MHz) -97 -98.5 -99.5 -97.0 dBm

LTE-TDD B39 (10 MHz) -97 -97.5 -100 -97.0 dBm

LTE-TDD B40 (10 MHz) -97 -98 -99.5 -97.0 dBm

LTE-TDD B41 (10 MHz) -95.5 -95.5 -99 -95.0 dBm

5G NR FDD n1 (20 MHz) TBD TBD -96.5 -93.5 dBm

5G NR FDD n28 (20 MHz) TBD TBD TBD -90.8 dBm

5G NR 5G NR TDD n41 (100 MHz) -84 -85 -90 -87.4 dBm

5G NR TDD n78 (100 MHz) -87 -87 -93 -87.8 dBm

5G NR TDD n79 (100 MHz) -87 -87 -93 -87.8 dBm

Table 68: RG501Q-EU/RG502Q-EU Conducted RF Receiving Sensitivity

28
3GPP
Mode Frequency Primary Diversity SIMO
(SIMO)

WCDMA B1 -108.5 -109 -111 -106.7 dBm

WCDMA WCDMA B5 -110 -110 -113 -104.7 dBm

WCDMA B8 -110 -110 -113 -103.7 dBm

LTE-FDD B1 (10 MHz) -95.6 -96 -98.5 -97.0 dBm

LTE-FDD B3 (10 MHz) -97.0 -97.5 -99.5 -94.0 dBm

LTE-FDD B5 (10 MHz) -98.5 -99.0 -100 -95.0 dBm

LTE LTE-FDD B7 (10 MHz) -95.4 -97 -98.2 -95.0 dBm

LTE-FDD B8 (10 MHz) -98.5 -99 -101 -94.0 dBm

LTE-FDD B20 (10 MHz) -98 -99 -100.5 -94.0 dBm

LTE-FDD B28 (10 MHz) -98.2 -98.7 -100.5 -95.5 dBm

28 For the SIMO receiving sensitivity, WCDMA and LTE bands are tested with 2 Rx antennas while 5G n41/77/78/79 bands
are tested with 4 Rx antennas.

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LTE-TDD B38 (10 MHz) -95.6 -97 -98.2 -97.0 dBm

LTE-TDD B40 (10 MHz) -95.4 -97.2 -98.2 -97.0 dBm

LTE-TDD B41 (10 MHz) -95.0 -96.5 -97.9 -95.0 dBm

LTE-TDD B42 (10 MHz) -98 -96 -99.5 -95.0 dBm

LTE-TDD B43 (10 MHz) -98 -96.5 -99.5 -95.0 dBm

5G NR FDD n1 (20 MHz) -92.5 -93 -95 -93.5 dBm

5G NR FDD n3 (20 MHz) -93.5 -93.5 -96.2 -90.8 dBm

5G NR FDD n5 (20 MHz) -95 -96 -97.5 -90.8 dBm

5G NR FDD n7 (20 MHz) -92 -93.5 -95 -91.8 dBm

5G NR FDD n8 (20 MHz) -94.8 -96 -97.5 -90.0 dBm

5G NR FDD n20 (20 MHz) -94.4 -96 -97.5 -89.8 dBm

5G NR
5G NR FDD n28 (20 MHz) -94 -95.5 -97 -90.8 dBm

5G NR TDD n38 (20 MHz) -92 -93.2 -95.5 -93.8 dBm

5G NR TDD n40 (20 MHz) -92 -93.4 -95.5 -93.8 dBm

5G NR TDD n41 (100 MHz) -84 -85.2 -91 -87.4 dBm

5G NR TDD n77 (100 MHz) -85.5 -85.6 -92 -87.8 dBm

5G NR TDD n78 (100 MHz) -85.6 -85.7 -92.2 -87.8 dBm

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6.7. ESD

If the static electricity generated by various ways discharges to the module, the module maybe damaged
to a certain extent. Thus, please take proper ESD countermeasures and handling methods. For example,
wearing anti-static gloves during the development, production, assembly and testing of the module;
adding ESD protective components to the ESD sensitive interfaces and points in the product design.

Table 69: Electrostatic Discharge Characteristics

Tested Interfaces Contact Discharge Air Discharge Unit

VBAT, GND ±5 ±10 kV

Antenna Interfaces ±4 ±8 kV

Other Interfaces ±0.5 ±1 kV

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7 Mechanical Information
This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm,
and the dimensional tolerances are ±0.2 mm unless otherwise specified.

7.1. Mechanical Dimensions

Pin 1

Figure 46: Module Top and Side Dimensions

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Pin 1

Figure 47: Module Bottom Dimensions (Bottom View)

NOTE

The package warpage level of the module conforms to the JEITA ED-7306 standard.

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7.2. Recommended Footprint

Pin 1

Figure 48: Recommended Footprint

NOTE

1. Keep at least 3 mm between the module and other components on the motherboard to improve
soldering quality and maintenance convenience.
2. To keep the reliability of the mounting and soldering, keep the motherboard thickness as at least
1.2 mm.

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7.3. Top and Bottom Views

Figure 49: Top and Bottom Views of the Module

NOTE

Images above are for illustration purpose only and may differ from the actual module. For authentic
appearance and label, please refer to the module received from Quectel.

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 5G Module Series

8 Storage, Manufacturing and

Packaging

8.1. Storage Conditions

The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage
requirements are shown below.

1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity
should be 35–60 %.

2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition.

3. The floor life of the module is 168 hours 29 in a plant where the temperature is 23 ±5 °C and relative
humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be
processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the
module should be stored in an environment where the relative humidity is less than 10 % (e.g. a
drying cabinet).

4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under
the following circumstances:

⚫ The module is not stored in Recommended Storage Condition;

⚫ Violation of the third requirement above occurs;
⚫ Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
⚫ Before module repairing.

5. If needed, the pre-baking should follow the requirements below:

⚫ The module should be baked for 8 hours at 120 ±5 °C;

⚫ All modules must be soldered to PCB within 24 hours after the baking, otherwise they should be

29
This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start
the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to,
or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are
not ready for soldering.

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 5G Module Series

put in a dry environment such as in a drying oven.

NOTE

1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to
the air is forbidden.
2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking.
All modules must be soldered to PCB within 24 hours after the baking, otherwise put them in the
drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure.
3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules.

8.2. Manufacturing and Soldering

Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. Apply proper force on the squeegee to produce a clean
stencil surface on a single pass. To guarantee module soldering quality, the thickness of stencil for the
module is recommended to be 0.15–0.18 mm. For more details, see document [9].

The peak reflow temperature should be 235–246 ºC, with 246 ºC as the absolute maximum reflow
temperature. To avoid damage to the module caused by repeated heating, it is strongly recommended
that the module should be mounted only after reflow soldering for the other side of PCB has been
completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related
parameters are shown below.

Temp. (°C)
Reflow Zone
Max slope: Cooling down slope:
2~3 °C/s C -1.5 ~ -3 °C/s
246
235
217
B D
200
Soak Zone

150 A

100
Max slope: 1~3 °C/s

Figure 50: Recommended Reflow Soldering Thermal Profile

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 5G Module Series

Table 70: Recommended Thermal Profile Parameters

Factor Recommendation

Soak Zone

Max slope 1–3 °C/s

Soak time (between A and B: 150 °C and 200 °C) 70–120 s

Reflow Zone

Max slope 2–3 °C/s

Reflow time (D: over 217 °C) 40–70 s

Max temperature 235 °C to 246 °C

Cooling down slope -1.5 to -3 °C/s

Reflow Cycle

Max reflow cycle 1

NOTE

1. If a conformal coating is necessary for the module, do NOT use any coating material that may
chemically react with the PCB or shielding cover, and prevent the coating material from flowing into
the module.
2. Avoid using ultrasonic technology for module cleaning since it can damage crystals inside the
module.
3. Due to the complexity of the SMT process, please contact Quectel Technical Supports in advance for
any situation that you are not sure about, or any process (e.g. selective soldering, ultrasonic
soldering) that is not mentioned in document [9].

8.3. Packaging Specification

The module adopts carrier tape packaging and details are as follow:

8.3.1. Carrier Tape

Dimension details are as follow:

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 5G Module Series

Figure 51: Carrier Tape Dimension Drawing

Table 71: Carrier Tape Dimension Table (Unit: mm)

W P T A0 B0 K0 K1 F E

72 56 0.4 44.7 41.7 4.2 5.2 34.2 1.75

8.3.2. Plastic Reel

Figure 52: Carrier Tape Dimension Drawing

Table 72: Plastic Reel Dimension Table (Unit: mm)

øD1 øD2 W

380 180 72.5

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 5G Module Series

8.3.3. Packaging Process

Place the module into the carrier tape and use

the cover tape to cover it; then wind the
heat-sealed carrier tape to the plastic reel and
use the protective tape for protection. One
plastic reel can load 200 modules.

Place the packaged plastic reel, humidity

indicator card and desiccant bag into a
vacuum bag, then vacuumize it.

Place the vacuum-packed plastic reel into a

pizza box.

Put 4 pizza boxes into 1 carton and seal it. One

carton can pack 800 modules.

Figure 53: Packaging Process

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 5G Module Series

9 Appendix References
Table 73: Related Documents

Document Name

[1] Quectel_RG50xQ_Series_CA&EN-DC_Features

[2] Quectel_5G_EVB_User_Guide

[3] Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_Manual

[4] Quectel_RG50xQ_Series_RGMII_Interface_Design_Change_Application_Note

[5] Quectel_RG50xQ_Series_Time_Service_Application_Note

[6] Quectel_RG50xQ_Series_Repeater_Application_Note

[7] Quectel_RG50xQ&RM5xxQ_Series_GNSS_Application_Note

[8] Quectel_RF_Layout_Application_Note

[9] Quectel_Module_Secondary_SMT_Application_Note

[10] Quectel_RG50xQ_Series_Reference_Design

Table 74: Terms and Abbreviations

Abbreviation Description

1PPS 1 Pulse Per Second

ADC Analog-to-Digital Converter

AMR-WB Adaptive Multi-Rate Wideband

AON Active Optical Network

AP Application Processor

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 5G Module Series

bps Bits Per Second

BPSK Binary Phase Shift Keying

CA Carrier Aggregation

CTS Clear To Send

DAI Digital Audio Interface

DCE Data Communications Equipment

DC-HSDPA Dual-carrier High Speed Downlink Packet Access

DDR Double Data Rate

DFOTA Delta Firmware Upgrade Over The Air

DL Downlink

DRX Discontinuous Reception

DRX Diversity Receive

DTE Data Terminal Equipment

DTR Data Terminal Ready

ESD Electrostatic Discharge

FDD Frequency Division Duplex

FEM Front-End Module

GLONASS Global Navigation Satellite System (Russia)

GNSS Global Navigation Satellite System

GPS Global Positioning System

GRFC General RF Control

HB High Band

HPUE High Power User Equipment

HSDPA High Speed Downlink Packet Access

HSPA High Speed Packet Access

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 5G Module Series

HSUPA High Speed Uplink Packet Access

IC Integrated Circuit

I2C Inter-Integrated Circuit

I2S Inter-IC Sound

I/O Input/Output

LAA License Assisted Access

LB Low Band

LED Light Emitting Diode

LGA Land Grid Array

LMHB Low/Middle/High Band

LNA Low Noise Amplifier

LTE Long Term Evolution

MAC Media Access Control

MB Middle Band

MHB Middle/High Band

MIMO Multiple Input Multiple Output

MO Mobile Originated

MT Mobile Terminated

NR New Radio

NSA Non-Stand Alone

PA Power Amplifier

PAP Password Authentication Protocol

PC Personal Computer

PCB Printed Circuit Board

PCIe Peripheral Component Interconnect Express

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 5G Module Series

PCM Pulse Code Modulation

PDA Personal Digital Assistant

PDU Protocol Data Unit

PHY Physical Layer

PRX Primary Receive

QAM Quadrature Amplitude Modulation

QPSK Quadrature Phase Shift Keying

QZSS Quasi-Zenith Satellite System

RF Radio Frequency

RGMII Reduced Gigabit Media Independent Interface

RHCP Right Hand Circularly Polarized

Rx Receive

SA Stand Alone

SCS Sub-Carrier Space

SD Secure Digital

SIB System Information Block

SIMO Single Input Multiple Output

SMD Surface Mount Device

SMS Short Message Service

SoC System on a Chip

SPI Serial Peripheral Interface

STB Set Top Box

TDD Time Division Duplexing

TRX Transmit & Receive

Tx Transmit

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 5G Module Series

UART Universal Asynchronous Receiver/Transmitter

UHB Ultra High Band

UL Uplink

UMTS Universal Mobile Telecommunications System

URC Unsolicited Result Code

USB Universal Serial Bus

(U)SIM Universal Subscriber Identity Module

VBAT Voltage at Battery (Pin)

VIHmax Maximum High-level Input Voltage

VIHmin Minimum High-level Input Voltage

VILmax Maximum Low-level Input Voltage

VILmin Minimum Low-level Input Voltage

Vmax Maximum Voltage

Vmin Minimum Voltage

Vnom Nominal Voltage

VOHmax Maximum High-level Output Voltage

VOHmin Minimum High-level Output Voltage

VOLmax Maximum Low-level Output Voltage

VSWR Voltage Standing Wave Ratio

WCDMA Wideband Code Division Multiple Access

WLAN Wireless Local Area Network

WWAN Wireless Wide Area Network

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