Static Timing Analysis (STA)

1. What is Static Timing Analysis (STA):

STA is a method of validating timing performance of a design by checking all possible
paths for timing violations.
2. What is Dynamic Timing Analysis (DTA):
DTA determines the full behavior i.e., timing and functionality of the circuit for a
given set of input test vectors.
3. Difference between DTA and STA:
DTA STA

Checks for both timing and functionality. Checks for only timing.
Dependent on input data (test vectors). Independent of data.
Slower because it also checks the Faster and takes less time.
functionality.

4. Setup time & Hold time:

The minimum amount of time required to stabilize the inputs before the clock edge is
called “Setup Time”.
The minimum amount of time required to stabilize the inputs after the clock edge is
called “Hold Time”.
5. Setup Slack & Hold Slack:
Setup Slack verifies that the data delay is small enough so that the data launched by
launch flop should reach the capture flop within one clock cycle, and the data should
arrive at least one unit time before the data gets captured by the capture clock.
SS = RT-AT
Arrival Time ≤ Required Time
t launch +t ck-q +t comb +t wire ≤ t clk – t su – t un + t capture
Hold Slack verifies that the data already existing at the input of capture flop remains
stable long enough after the clock edge that captures the data for the previous cycle.
HS = AT-RT
Arrival Time ≥ Required Time
t launch +t ck-q +t comb +t wire ≥ t h +t un +t capture
6. Hold Check 1 & Hold Check 2:
The data launched by next launching edge must not capture by current capturing
edge is HS1.
The data launched by current launching edge must not capture by previous capturing
edge is HS2.
7. Single Cycle Behavior:
The data launched should be captured in a single cycle without violating setup and
hold requirements.
8. Skew:
The difference between capture flop latency and launch flop latency is called skew.
Different types of skew are:
• Local Skew
• Global Skew
• Useful Skew
9. Local Skew:
The difference between capture flop latency and launch flop latency of two
communicating flops is called local skew.
Types:
• Positive Skew - Effects hold requirement.
• Negative Skew - Effects setup requirement.
10.Global Skew & Useful Skew:
• Difference between max clock latency and min clock latency in a design is
called Global Skew.
• If we intentionally introduce skew in a timing path to meet setup or hold
requirement, then it is called Useful Skew.
To meet setup - we add delay in capture path
To meet hold - we add delay in launch path
11.Clock Jitter:
The deviation of the clock edge from its actual position is called Clock Jitter.
12.Base Period:
Base period is the least common multiple (LCM) of all clock periods.
13.On Chip Variation (OCV):
In OCV a fixed timing derate factor is applied to the delay of all the cells present in the
design so that in case of process variation affects the delay of any cells during the
fabrication, it will not affect the timing requirements and the chip will not fail after
fabrication. And this OCV is used above 90nm technology.

Fabrication process variations could either increase or decrease the delay of a

cell. So we need to set early and late values while setting the derate factor.

CMD: set_timing_derate -cell_delay-rise -

data -early 0.92

14.Derating Factor:
Timing derate numbers are ratios used to derate(increase/decrease) the delay
numbers you get in your timing reports.
15.Common Path Pessimism Removal (CPPR):
It means the cells sitting in the common clock branch for both launching and
capturing paths.
16.Advanced OCV (AOCV):
In AOCV derate is applied on each cell based on path depth and distance of the cell in
the timing path and it also varies with cell type and drive strength of the cell.
Distance is defined by a bounding box for the net and cells.
• Used above 40nm technology.
 • Distance is the max net length of clock path.
• Path Depth defines the no. of cells in the clock path.
17.Parametric On chip Variation (POCV):
• In POCV instead of applying the specific derate factor to a cell, cell delay is
calculated based on delay variation (σ) of the cell. In POCV it is assumed that
the normal delay value of a cell follows the normal distribution curve.
• POCV uses a nominal delay value (µ) instead of using the min or max value of
delay to model the random variations.
• Timing analysis is done using the nominal delay value (µ) and delay variation (σ).
• Used above 40nm technology.
18.Clock:
The signal which is used to trigger all the sequential elements in the design.
Types,
• Synchronous
• Asynchronous
• Exclusive
19.Synchronous & Asynchronous Clocks:
• Two clocks are synchronous with respect to each other if they share a common
source and have a fixed phase relationship and a common base period(should
have a common multiple).
Ex: time period of two clocks : 2 and 6, here the common base period is 2.
• Two clocks are said to be asynchronous if they do not have a fixed phase
relationship with each other in the design and don’t have a common base
period.
Ex: time period of two clocks : 6 and 7, here there is no common base period.
20.Exclusive Clocks:
• Two clocks are exclusive if they do not interact with each other.
• For example, a circuit might multiplex two different clock signals onto a clock
line, one a fast clock for normal operation and the other a slow clock for low-
power operation.
 • Only one of the two clocks is enabled at any given time, so there is no
interaction between the two clocks.
• You may define "false path" between these mutually exclusive clocks.
21.Virtual Clock:
• A virtual clock has no actual source in the current design, but you can use it for
setting input or output delays.
• You can use virtual clock cmd to define virtual clocks for signals that interface
to external clocked devices (other block).

CMD: create_clock –period 8 –name vclk –waveform {0 4}

22.Create Clocks:
• The crete_clock cmd is used to create a clock at the specified source. A source
can be defined at an input port of the design or an internal pin.
• To create a clock on ports C1 and CK2 with a period of 10, a rising edge at 2,
and falling edge at 4, enter the cmd

CMD: create_clock –period 10 –waveform {2 4} [get_ports {C1 CK2}]

• With this an ideal clock is created that ignores the delay effects of the clock
network.
23.Gated Clock:
A gated clock is a clock signal under the control of gating logic.Tool performs both
setup and hold checks on the gating clock.
24.Generated Clocks:
• A generated Clock is a clock signal generated from another clock signal by a
circuit within the design itself, such as a clock divider.
• The create_generated_clock cmd is used to create generated clocks in which
you can create frequency divided (-divide_by) or frequency multiplied (-
multiply_by) clock.
CMD: create_generated_clock –name dclk\
–source [get_ports CLK] –divide_by 2 [get_ports FF1/Q]

25.Edge detecting Circuits:

The Edge Detector component samples the connected signal and produces a pulse
when the selected edge occurs.
We must select anyone of the edge for detection, Rising Edge, Falling Edge, or Either
Edge.
Rising Edge Detector:
The Edge Detector stores the state of the signal at the last rising clock edge, and
compares it to the current value of the signal. If the state change matches the edge
type selected in the customizer, the det terminal will go high until the next rising
clock edge. This means that the resulting pulse from an edge may be shorter than
one clock cycle, but it will never be longer.

As seen in Figure 2, the det output will go high as soon as a rising edge is detected on
the d input. The det output is cleared on the next rising clock edge.
 Falling Edge Detector:

As seen in Figure 4, the det output will go high as soon as a falling edge is detected
on the d input. The det output is cleared on the next rising clock edge.
26.Timing Path:
Timing path is defined as the path between start point and end point.
• Start Point - CK pin of flop or Input port of the block.
• End Point - D pin of the flop or output port of the block.
27.Types of Paths:
• Reg to Reg
• In to Reg
• Reg to Out
• In to Out
28.Input Delays:
• In order to do the timing analysis in the paths like I2R and I2O, tool needs
information about the arrival times of the signals at the input ports.
• The set_input_delay cmd is used to specify the min and max amount of delay
from a clock edge to the arrival of a signal at a specified input port.
29.Output Delays:
• In order to do the timing analysis in the paths like R2O and I2O, tool needs
information about the timing requirements at the output ports.
 • The set_output_delay cmd is used to specify the min and max amount of delay
between the output port and the external sequential device that captures the
data from that output port is specified at that output port.
30.Recovery and Removal times:
Recovery time is the minimum time that as asynchronous control signal must be
stable before the clock active-edge transition. In other words, this check ensures that
after the asynchronous signal become inactive, there is adequate time to recover so
that the next active clock edge can be effective.

Removal time is the minimum length of time that an asynchronous control must be
stable after the clock active edge transition. This check ensures that the active clock
edge has no effect because the asynchronous control signal remains active until
removal time after the active clock edge.

31.Hand Shaking Communication:

A handshake is a means of synchronization among communicating mechanisms. In its
simplest form it involves two mechanisms connected by a pair of so-called links, one
for sending signals and one for receiving signals.
32.When the circuit gets asynchronous:
The asynchronous circuits do not need a global clock, and the state of the circuit
changes as soon as the inputs change.
 Since asynchronous circuits do not have to wait for a clock pulse to begin processing
inputs, they can operate faster. Their speed is theoretically limited only by
the propagation delays of the logic gates and other elements.

33.Two Stage Synchronizer:

When an asynchronous signal, or a signal from a block clocked by a different clock is
received by a synchronous circuit, it is imperative that it is reliably sampled by the
receiver. Since the signal is asynchronous to the receiver in these cases, a special
circuitry named synchronizer is used to ensure proper sampling and synchornization
with respect to the receiving clock. If the data changes in an unacceptable range of
the clock, metastability occurs as explained previously. This can be avoided by giving
enough time for the meta stable output to settle down. The most common method
used is the two stage synchronizer using flops.
 The two flops should be placed as close to each other as possible so there is no
combinational delay between the flops. This ensures that entire clock cycle is
available for the metastability to resolve. There is a possibility that the input will be
settled into a wrong value, and this wrong input will be propagated to the
subsequent stages. It is important that the input from one domain stays stable for at
least one clock cycle so that the wrong stable data(after a metastability event) is not
propagated. The disadvantage in using these synchronizers are the overhead it adds
in propagation delay, area and power. Special synchronization flops are available in
your libraries which have higher value of MTBF, and is specially designed for reducing
the failure rate.

34.Mean Time Between Failure (MTBF):

Metastability failures are probablisitic in nature. You cannot avoid metstability, but
MTBF or the Mean Time Between Failures gives you a measure to determine the
reliability of the device with respect to metastability failures. It gives the average
time between two failures for the device.
 Logic Synthesis
1. Logic Synthesis:
The process of converting high level abstraction(RTL) to implementable logic gates
(Gate level Netlist) to a targeted technology by meeting design constraints(Timing,
Area, Power).
2. Synthesis Flow:

3. Sanity Checks:
check_design - Netlist check_timing - SDC
• Unresolved References • Sequential clock pin without clock waveform
• Empty Modules • Sequential clock pin with multi clock waveform
• Unloaded Ports • Generated clocks without clock waveform
• Unloaded Sequential Pins • Generated clocks with multi master clocks
• Undriven Leaf pins • Timing exceptions with no effect
• Undriven Ports • Inputs/Outputs without clocked external delay
• Combinational Loops Exceptions with invalid timing start or end points
• Multidriven Port
4. Elaborate:
Elaboration is the process that occurs between parsing and simulation. It binds
modules to module instances, builds the model hierarchy, computes parameter values,
resolves hierarchical names, establishes net connectivity, and prepares all of this for
simulation.
5. Inputs of Synthesis:
▪ .lib
▪ .lef
▪ SDC
▪ RTL
▪ Tech lef
6. Types of libraries:
Slow, Typical and Fast libraries.
Corner Process Voltage Temperature
Slow SS 0.9 125
Typical TT 1 25
Fast FF 1.1 M40

7. Design Rule Violations(DRV):

DRV constraints exist in .lib.
DRV constraints can’t be relaxed. They can be chosen from .lib. These constraints are
imposed upon the design by requirements specified in the target technology library.
These precedence over optimization constraints to realize a functional design.
▪ Max Cap
▪ Max Tran
▪ Max Fan Out
8. Max transition:
If any path having larger transition which are greater than defined max_transition
value, then it reports max transition violation.
9. Max capacitance:
The maximum capacitance(CL) of a cell is the sum of output pin capacitance of
the driver, net capacitance and input pin capacitance of the driven cell.
If any path having larger capacitance which are greater than defined
max_capacitance value, then it reports max capacitance violation.
10.Max fanout:
• The number of loads a pin or port can drive.
• Limits the number of components that can be driven by the input port.
 • It is useful for signals that drive many blocks (e.g. global buses,reset).
• Fanout can be reduced by Cloning (or) Buffering.
11..LEF File(std & macro):
• Metal Layer Info
• Pin Name • Height of the cell
• Pin Location • Width of the cell
• Pin Layer • Pin Width
• Pin Direction • Pin Height
• Site Row
12. Tech LEF File:
• No of Metal Layers
• Via Definition
• Resistance Value of Metals
• Capacitance Value of Metals
• Pitch
• Minimum Spacing
• Layer name
• Metal direction
13..LIB File:
• PVT • Setup and Hold requirements
• Units of flops
• Cell Delay • Power Info
• Input Transition • Functionality of all gates
• Output Load • Area of STD Cells
• Rise &Fall Times • Unatnes
• Wire Load Models
14. Intrapolation:
Interpolation is a method of estimating the value that lies between known data points
and this is done using the known data points.
15. Extrapolation:

16. Clock Uncertainty:

It is the margin which we reserve in clock period for the clock effecting pessimistic
parameters like
• Skew
• Jitter
• OCV
• Crosstalk
17. Wire load Model:
Wire load models (WLM) can be used to calculate interconnect wiring delays
(capacitance (C), resistance (R)) due to interconnect.
The wire load model is also used to estimate the length of a net-based upon the
number of its fanouts.
Types:
• Zero WLM - 0% Uncertainty
• Custom WLM -15% Uncertainty(user defined)
• Auto WLM -Tool calculates based on fanouts.
18. Gate Count:
Gate count refers to the number of logic gates built with transistors and other
electronic devices, that are needed to implement a design.

19. Instance Count:

The instance count is the actual number of standard cells in your design.
20. Synthesis Strategies:
• Top-Down Approach/Flat Design
• Bottom-Up Approach/Hierarchical design
21. Hierarchical Synthesis:
• The entire is divided into different blocks and synthesized separately
• We may or may not have control over logic (less optimization)
• So less run time
• Less memory requirement
• Low end servers (Economical)
• Multiple persons can work on the design
• So design may get ready on time.
22. Flat Design synthesis:
• The whole design is considered as a single identity
• We have control over entire logic (well optimization)
• So Huge run time
• Huge Memory requirement
• High end servers (Expensive)
• Multiple persons won't work on the design, So design may get delayed.
25. Time Budgeting:
Timing budgeting is an important step in achieving timing closure in a physically
hierarchical design. The timing budgeting determines the corresponding timing
boundary constraints for each block in a design. If the timing boundary constraints for
each block are met when they are implemented, the top-level timing constraints are
satisfied.
In the chip designing, while you divide the design into small blocks, you have to
take care about timing between block’s I/O to other block’s I/O, block’s I/O to chip I/O.
If a data is required by a block A for doing some processing and this data is generated
by block B, so Block A should know when it will receive the data from the Block B. Since
at the top level these blocks are Black Box, so during timing budgeting we have to
define the constraint at input of Block A that it will receive the data after X time (this
X we have to estimate correctly on the basic of experience and knowledge of the block,
usually we constraint with X+x amount where x is the margin we are keeping in case
of wrong estimation).

26. set_dont_use:
This cmd is used to specify the std cells, so that the tool don’t use these cells in the
design at the time of optimization.
27. False Path:
A false path is a timing path which is not required to meet its timing constraints for the
design to function properly.
28. Multi Cycle Path:
A Multi-Cycle Path (MCP) is a flop-to-flop path, where the combinational logic delay in
between the flops is permissible to take more than one clock cycle.
35. Min Delay & Max Delay:
A path must match a delay constraint that matches a specific value. It is not an integer
like multicycle path.
36. Design for Testability (DFT):
The process in which we check for failures in the functionality due to manufacturing
faults by inserting test patters in the design.
30. Scan:
Scan diagnosis helps identify the location and classification of a defect based on the
design description, test patterns used to detect the failure, and data from failing
pins/cycles.
31. Scan Stiching:
The process of serially connecting a group of scan flipflops together to form a
scan chain is referred to as 'scan stitching'.
The scan chain stitching is made power aware by placing flip-flops with higher
test combination requirements at the beginning of scan chains, while flip-flops with
lower test combination requirements are put toward the end of scan chains.
32. Scan Chain:
• Scan chains are the elements in scan-based designs that are used to shift-in and
shift-out test data.
• A scan chain is formed by a number of flops connected back to back in a chain
with the output of one flop connected to another.
• The input of first flop is connected to the input pin of the chip (called scan-in)
from where scan data is fed.
• The output of the last flop is connected to the output pin of the chip (called scan-
out) which is used to take the shifted data out.
33. Memory Built In Self Test (MBIST):
MBIST is a self-testing and repair mechanism which tests the memories through
an effective set of algorithms to detect possibly all the faults that could be present
inside a typical memory cell whether it is stuck-at (SAF).
34. Joint Test Action Group (JTAG):
JTAG is a powerful test technology that can be used to test the io pads for all the
possible Manufacturing Defects or Faults.
35. Test Enable:
Input to the scan-flop that controls whether scan_in data or functional data will
propagate to output.
36. Scan Chain Reordering:
• It is the process of reconnecting the scan chains in a design to optimize for
routing by reordering the scan connection which improve timing and
congestion.
• It is done either at pre CTS or post CTS.
• And then the CTS def is sent to DFT team for changing the test vectors for the
reordered scan chain.

37. Power Opt Techniques:

• Clock Gating
• Operand Isolation
• Mixed Vt optimization
• ICG
• Multi VDD
38. Integrated Clock Gating(ICG):
• Clock gating limits the clock from being given to every register or flops in the
processor. It disables the clock of an unused device.
• It is used for reducing DYNAMIC POWER by controlling switching activities on
the clock path.
• Generally gate or latch or flip flop based block gating cells are used for
implementing clock gating.
• We can find these Clock Gating cells in .lib file.
• In load enabled flops, the output of the flops switches only when the enable is
on. But clock switches continuously, increasing the dynamic power
consumption.

• By converting load enable circuits to clock gating circuit dynamic power can be
reduced. Normal clock gating circuit consists of an AND gate in the clock path
with one input as enable. But when enable becomes one in between positive
level of the clock a glitch is obtained.
 • To remove the glitches due to AND gate, integrated clock gate is used. It has a
negative triggered flop and an AND gate.

39. Operand Isoation:

Operand isolation is a technique for minimizing the power consumption associated
with combinational circuit operations by selectively blocking the propagation
of switching activity through the circuit.

40. Mixed Vt optimization:

▪ Generally VT Swapping is used for optimizing both power and timing.
▪ By using this technique for optimization, the area remains unchanged.
For Timing :
• If the design is timing constrained, then we use HVT cells for the design.
• For the timing critical paths we swap,
HVT with SVT
(or)
SVT with LVT
For Power :
• If it is a low power design, then we use LVT cells for the design.
• For high switching cells we swap,
LVT with SVT
(or)
SVT with HVT
41. Why LVT cells are more leaky?
Below the Vt voltage also there will be some amount of current which is known as sub-
threshold current. So for LVT very small amount of voltage will be enough for the sub
threshold current. This sub-threshold current is the major factor for leakage in LVT
cells.
42. Physical Layout estimation(PLE):
• PLE, Only requires Cap Table as an additional input, which will be used to
estimate the net RC from Cap table instead of LEF.
• RC Eliminates WLM's with "Physical Layout Estimation (PLE)" Technique.
• Good timing results at 90nm node and below.
• Area grows about 5-10% more.
43. Spatial Synthesis:
It assumes PLE inputs + DEF (Floorplan). It does some Placement of the block
and thus minimize the net lengths.
Synthesize_to_mapped -spatial
44. Physical Synthesis:
Physical Synthesis begins with a mapped netlist generated by logic synthesis and it
have the capability of PnR. The target of PS is to achieve the minimum area usage at
the required speed for a design.
45. Netlist Unification:
Every module/cell in the design should have an unique name.
CMD:checkUnique

If the netlist is unique, then it results 1, otherwise 0.

46. Incremental Synthesis:
Synthesizing the design without touching the already timing met paths is called
Incremental Synthesis.
47. Logic Equivalence Check(LEC):
It looks at the combinatorial structure of the design to determine if the structure
of two alternative implementations will exhibit the same behavior. It compares the RTL
and Gate Level Netlist and checks for differences in structure of the design.
48. Activity Factor:
The activity factor is the probability that the circuit node transitions from 0 to 1
because that is only the time the circuits consume power. A clock has an activity factor
α = 1 because it rises and falls every cycle. The activity factor is powerful and easy to
use lever for reducing power.