Explain Astable multivibrator using IC-555 with circuit diagram and

capacitor and output wavefrom.

Astable multivibrator is also called as Free Running Multivibrator. It has no stable

states and continuously switches between the two states without application of any
external trigger. The IC 555 can be made to work as an astable multivibrator with
the addition of three external components: two resistors (R 1 and R2) and a
capacitor (C). The schematic of the IC 555 as an astable multivibrator along with
the three external components is shown below

The pins 2 and 6 are connected and hence there is no need for an external trigger
pulse. It will self trigger and act as a free running multivibrator (oscillator). The
rest of the connections are as follows: pin 8 is connected to supply voltage (V CC).
Pin 3 is the output terminal and hence the output is available at this pin. Pin 4 is
the external reset pin. A momentary low on this pin will reset the timer. Hence,
when not in use, pin 4 is usually tied to VCC.
The control voltage applied at pin 5 will change the threshold voltage level. But
for normal use, pin 5 is connected to ground via a capacitor (usually 0.01µF), so
the external noise from the terminal is filtered out. Pin 1 is ground terminal. The
timing circuit that determines the width of the output pulse is made up of R 1,
R2 and C.

Astable Multivibrator Using IC 555 Operation

The following schematic depicts the internal circuit of the IC 555 operating in
astable mode. The RC timing circuit incorporates R1, R2 and C.

Initially, on power-up, the flip-flop is RESET (and hence the output of the timer is
low). As a result, the discharge transistor is driven to saturation (as it is connected
to Q’). The capacitor C of the timing circuit is connected at Pin 7 of the IC 555
and will discharge through the transistor. The output of the timer at this point is
low. The voltage across the capacitor is nothing but the trigger voltage. So, while
discharging, if the capacitor voltage becomes less than 1/3 V CC, which is the
reference voltage to trigger comparator (comparator 2), the output of the
comparator 2 will become high. This will SET the flip-flop and hence the output
of the timer at pin 3 goes to HIGH.
This high output will turn OFF the transistor. As a result, the capacitor C starts
charging through the resistors R1 and R2. Now, the capacitor voltage is same as
the threshold voltage (as pin 6 is connected to the capacitor resistor junction).
While charging, the capacitor voltage increases exponentially towards V CC and the
moment it crosses 2/3 VCC, which is the reference voltage to threshold comparator
(comparator 1), its output becomes high.

As a result, the flip-flop is RESET. The output of the timer falls to LOW. This low
output will once again turn on the transistor which provides a discharge path to the
capacitor. Hence the capacitor C will discharge through the resistor R 2. And hence
the cycle continues.

Thus, when the capacitor is charging, the voltage across the capacitor rises
exponentially and the output voltage at pin 3 is high. Similarly, when the capacitor
is discharging, the voltage across the capacitor falls exponentially and the output
voltage at pin 3 is low. The shape of the output waveform is a train of rectangular
pulses. The waveforms of capacitor voltage and the output in the astable mode are
shown below.
While charging, the capacitor charges through the resistors R 1 and R2. Therefore
the charging time constant is (R 1 + R2) C as the total resistance in the charging
path is R1 + R2. While discharging, the capacitor discharges through the resistor
R2 only. Hence, the discharge time constant is R2C.

Duty Cycle Of Astable Multivibrator

The charging and discharging time constants depends on the values of the resistors
R1 and R2. Generally, the charging time constant is more than the discharging
time constant. Hence the HIGH output remains longer than the LOW output and
therefore the output waveform is not symmetric. Duty cycle is the mathematical
parameter that forms a relation between the high output and the low output. Duty
Cycle is defined as the ratio of time of HIGH output i.e., the ON time to the total
time of a cycle.

If TON is the time for high output and T is the time period of one cycle, then the
duty cycle D is given by:

D = TON/ T

Therefore, percentage Duty Cycle is given by:

%D = (TON / T) * 100

T is sum of TON (charge time) and TOFF (discharge time).

The value of TON or the charge time (for high output) TC is given by:

TON = TC = 0.693 * (R1 + R2) C

The value of TOFF or the discharge time (for low output) TD is given by

TOFF = TD = 0.693 * R2C

Therefore, the time period for one cycle T is given by

T = TON + TOFF = TC + TD

T = 0.693 * (R1 + R2) C + 0.693 * R2C

 T = 0.693 * (R1 + 2R2) C

Therefore, %D = (TON/ T) * 100

%D = (0.693 * (R1 + R2) C)/(0.693 * (R1 + 2R2) C) * 100

%D = ((R1 + R2)/(R1 + 2R2)) * 100

If T = 0.693 * (R1 + 2R2) C, then the frequency f is given by

f = 1 / T = 1 / 0.693 * (R1 + 2R2) C

f = 1.44/( (R1 + 2R2) C) Hz

Selection of R1, R2 and C1

The Selection of values of R1, R2 and C1 for different frequency range are as
follow:

R1 and R2 should be in the range 1KΩ to 1MΩ. It is best to Choose C 1 first

(because capacitors are available in just a few values and are usually not
adjustable, unlike resistors) as per the frequency range from the following table.

Choose R2 to give the frequency (f) you require.

R2 = 0.7 /(f × C1)

Choose R1 to be about a tenth of R2 (1KΩ min.)

Applications of Astable Multivibrator : Square wave generator

C1 R2 = 10KΩ R2 = 100KΩ R2 = 1MΩ

R1 = 1KΩ R1 = 10KΩ R1 = 100KΩ
0.001µF (102) 68 KHz 6.8 KHz 680 Hz

0.01µF (103) 6.8 KHz 680 Hz 68 Hz

0.1µF (104) 680 Hz 68 Hz 6.8 Hz

1µF 68 Hz 6.8 Hz 0.68 Hz
10µF 6.8 Hz 0.68 Hz 0.068 Hz
(41 per min.) (4 per min.)

Q. Explain bistable multivibrator using IC-555 with circuit diagramand

wavefroms.

When an astable multivibrator has no stable states and a monostable multivibrator

has a single stable state, a device with two absolute stable states is possible. A

Bistable multivibrator is a type of circuit which has two stable states (high and
low). It stays in the same state until and unless an external trigger input is applied.

Generally, a bistable multivibrator stays low until a trigger signal is applied and it
stays high until a reset signal is applied. Bistable multi vibrators are also called as
flip-flops or latches. The term flip-flop is used because it ‘flips’ to one state and
stays there until a trigger is applied and once the trigger is applied it ‘flops’ back
to the original state.
A bistable multivibrator is one of the easiest circuits that can be built using a 555
timer. It doesn’t require a capacitor as the RC charging unit is not responsible for
the generation of the output. The generation of high and low outputs is not
dependent on the charging and discharging of the capacitor in the RC unit but
rather it is controlled by the external trigger and reset signals.

The explanation of the bi stable mode of operation of the 555 timer is as follows.
The trigger and reset pins (pins 2 and 4 respectively) are connected to the supply
through two resistors R1 and R2 so that they are always high. In all the previous
cases, the reset pin is not used and in order to avoid any accidental reset, it is
simply connected to VCC.

Two switches are connected between these pins and ground in order to make them
go low momentarily. The switch at the trigger input will act as S (SET) input for
the internal flip-flop. The switch at the reset input will act as reset for the internal
flip-flop.

When the switch S1 is pressed, the voltage from VCC will bypass the trigger
terminal and is shorted to ground through the resistor R1. Hence, the trigger pulse
will momentarily go low and the output of the timer at pin 3 will become HIGH.
The output stays HIGH because there is no input from the threshold pin (pin 6 is
left open or better if connected to ground) and the output of the internal
comparator (comparator 1) will not go high.
When the switch S2 is pressed, the voltage from VCC will bypass the reset
terminal and is shorted to ground through the resistor R2. This pin is internally
connected to the RESET terminal of the flip-flop. When this signal goes low for a
moment, the flip-flop receives the reset signal and RESETs the flip-flop.

Hence, the output will become LOW and stays there until the trigger is applied.
The waveforms of the bistable mode of operation of the 555 timer are shown
below.

R. Explain monostable multivibrator using IC-555 with circuit diagram and

wavefroms.
A monostable multivibrator using a 555 timer is a circuit that generates a single
output pulse of a defined duration in response to an input trigger. This
configuration of the 555 timer is also known as a one-shot multivibrator because it
returns to its stable state after a single pulse. The duration of the output pulse is
determined by an RC (resistor-capacitor) network connected to the timer. These
guides cover everything from the basic principles, circuit diagrams, and practical
assembly tips, to applications of the monostable multivibrator using the 555 timer.

Circuit and Operation

The following figure is the schematic of IC 555 as a Monostable Multivibrator.
This is the basic mode of operation of the IC 555. It requires only two extra
components to make it work as a monostable multivibrator: a resistor and a
capacitor.
As the name specifies, a monostable multivibrator has only one stable state. When
a trigger input is applied, a pulse is produced at the output and returns back to the
stable state after a time interval. The duration of time for which the pulse is high
will depend on the timing circuit that comprises of a resistor (R) and a capacitor
(C).

The details of the connection are as follows. The pins 1 and 8 are connected to
ground and supply (VCC) respectively. Output is taken at pin 3. To avoid
accidental reset of the circuit, pin 4 is connected to the VCC. Pin 5, which is the
control voltage input, should be grounded when not in use. To filter the noise, it is
connected to the ground via a small capacitor of capacitance 0.01µF.

Operation
The monostable mode is also called “one-shot” pulse generator. The sequence of
events starts when a negative going trigger pulse is applied to the trigger
comparator. When this trigger comparator senses the short negative going trigger
pulse to be just below the reference voltage (1/3 VCC), the device triggers and the
output goes HIGH.

The discharge transistor is turned OFF and the capacitor C that is externally
connected to its collector will start charging to the max value through the resistor
R. The HIGH output pulse ends when the charge on the capacitor reaches 2/3
VCC. The internal connection of the IC 555 in monostable mode along with the
RC timing circuit is shown below.

The detailed operation can be explained as follows. Initially, the flip-flop is

RESET. This will allow the discharge transistor to go to saturation. The capacitor
C, which is connected to the open collector (drain in case of CMOS) of the
transistor, is provided with a discharge path. Hence the capacitor discharges
completely and the voltage across it is 0. The output at pin 3 is low (0).

When a negative going trigger pulse input is applied to the trigger comparator
(comparator 2), it is compared with a reference voltage of 1/3 VCC. The output
remains low until the trigger input is greater than the reference voltage. The
moment trigger voltage goes below 1/3 VCC, the output of comparator goes high
and this will SET the flip-flop. Hence the output at pin 3 will become high.

At the same time, the discharge transistor is turned OFF and the capacitor C will
begin to charge and the voltage across it rises exponentially. This is nothing but
the threshold voltage at pin 6. This is given to the comparator 1 along with a
reference voltage of 2/3 VCC. The output at pin 3 will remain HIGH until the
voltage across the capacitor reaches 2/3 VCC.

The instance at which the threshold voltage (which is nothing but the voltage
across the capacitor) becomes more than the reference voltage, the output of the
comparator 1 goes high. This will RESET the flip-flop and hence the output at pin
3 will fall to low (logic 0) i.e. the output returns to its stable state. As the output is
low, the discharge transistor is driven to saturation and the capacitor will
completely discharge.

Hence it can be noted that the output at pin 3 is low at start, when the trigger
becomes less than 1/3 VCC the output at pin 3 goes high and when the threshold
voltage is greater than 2/3 VCC the output becomes low until the occurrence of
next trigger pulse. A rectangular pulse is produced at the output. The time for
which the output stays high or the width of the rectangular pulse is controlled by
the timing circuit i.e. the charging time of the capacitor which depends on the time
constant RC.

Pulse Width Derivation

We know that the voltage across the capacitor C rises exponentially. Hence the
equation for the capacitor voltage VC can be written as

VC = VCC (1 – e-t/RC)

When the capacitor voltage is 2/3 VCC, then

2/3 VCC = VCC (1 – e-t/RC)

2/3 = 1 – e-t/RC

e-t/RC = 1/3

– t/RC = ln (1/3)

– t/RC = -1.098

t = 1.098 RC

∴ t ≈ 1.1 RC

The pulse width of the output rectangular pulse is W = 1.1 RC.

The waveforms of the monostable operation are shown below.

Applications of Monostable Multivibrator

Frequency Divider

Q. Explain IC-555 as Pulse Width Modulation.

The monostable mode of operation of the IC 555 can be turned into a Pulse Width
Modulator by applying a modulating signal as the control voltage at the pin 5. The
circuit for a Pulse Width Modulator using monostable multivibrator is shown
below.
The control signal will modulate the threshold voltage and as a result, the output
pulse width is modulated. As the control voltage varies, the threshold voltage;
which is the input to the comparator 1, also varies. As a result, the time for
charging the capacitor to the threshold voltage level will vary, resulting in a pulse
width modulated wave at the output. The waveforms of the input, output and the
modulating signal are shown below.
Due to the application of the control signal, the upper threshold voltage level for
the capacitor will be different. The new upper threshold level UTL is given by

UTL = 2/3 VCC + VMOD

Where VMOD is the voltage of the modulating signal.

Because of the new threshold level, the pulse width of the output is given by

W = -RC ln (1 – UTL/VCC)

The time period of the output is same as the input.

555 Timer IC – Pin Diagram, Working

Ground It should be connected to the negative/ground pin of the supply.

Trigger It is the negative input of the lower comparator. As soon as the voltage at this
pin drops below 1/3 Vcc, the output of lower comparator switch from ‘LOW’ to
‘HIGH’ which sets the output of S-R flip flop i.e, Q to ‘HIGH’.

Output The output pin can drive any TTL circuit and is capable of sourcing or sinking
up to 200mA of current at an output voltage equal to approximately Vcc – 1.5V so
small speakers, LEDs or motors can be connected directly to the output.

Reset This pin is used to ‘RESET’ the internal flip-flop controlling the state of the
output, pin 3, in spite of any voltage level at S and R pin of S-R flip-flop level. This is
an active-low input and is generally connected to a logic ‘HIGH’ to prevent any
unwanted ‘RESET’ of the output.

Control Voltage This pin controls the timing of the 555 by overriding the 2/3Vcc
level of the voltage divider network. By applying a voltage to this pin the width of the
output signal can be varied independently of the RC timing network. When not used it
is connected to ground via a 10nF capacitor to eliminate any noise.

Threshold It is the positive input to the upper comparator when the voltage at this pin
exceeds 2/3 Vcc, output at pin 3 turns ‘LOW’.

Discharge When the base of discharge transistor turns ‘HIGH’ this transistor is used
to discharge external RC network connected at pin 7 also during discharging output at
pin 3 stays ‘LOW’.

Vcc This is the power supply pin and for general purpose TTL 555 timers are between
4.5V and 15V.
The diagram of a 555 timer is shown in the above figure. A 555 timer has two
comparators, which are basically 2 op-amps), an R-S flip-flop, two transistors and
a resistive network.

 Resistive network consists of three equal resistors and acts as a voltage

divider.
 Comparator 1 compares threshold voltage with a reference voltage + 2/3
VCC volts.
 Comparator 2 compares the trigger voltage with a reference voltage + 1/3
VCC volts.
Output of both the comparators is supplied to the flip-flop. Flip-flop assumes its
state according to the output of the two comparators. One of the two transistors is
a discharge transistor of which collector is connected to pin 7. This transistor
saturates or cuts-off according to the output state of the flip-flop. The saturated
transistor provides a discharge path to a capacitor connected externally. Base of
another transistor is connected to a reset terminal. A pulse applied to this terminal
resets the whole timer irrespective of any input.

Working Principle
Refer Block Diagram of 555 timer IC given above:
The internal resistors act as a voltage divider network, providing (2/3)Vcc at the
non-inverting terminal of the upper comparator and (1/3)Vcc at the inverting
terminal of the lower comparator. In most applications, the control input is not
used, so that the control voltage equals +(2/3) V CC. Upper comparator has a
threshold input (pin 6) and a control input (pin 5). Output of the upper comparator
is applied to set (S) input of the flip-flop. Whenever the threshold voltage exceeds
the control voltage, the upper comparator will set the flip-flop and its output is
high. A high output from the flip-flop when given to the base of the discharge
transistor saturates it and thus discharges the transistor that is connected externally
to the discharge pin 7. The complementary signal out of the flip-flop goes to pin 3,
the output. The output available at pin 3 is low. These conditions will prevail until
lower comparator triggers the flip-flop. Even if the voltage at the threshold input
falls below (2/3) VCC, that is upper comparator cannot cause the flip-flop to
change again. It means that the upper comparator can only force the flip-flop’s
output high.

To change the output of flip-flop to low, the voltage at the trigger input must fall
below + (1/3) Vcc. When this occurs, lower comparator triggers the flip-flop,
forcing its output low. The low output from the flip-flop turns the discharge
transistor off and forces the power amplifier to output a high. These conditions
will continue independent of the voltage on the trigger input. Lower comparator
can only cause the flip-flop to output low.

From the above discussion, it is concluded that for the having low output from the
timer 555, the voltage on the threshold input must exceed the control voltage or +
(2/3) VCC. This also turns the discharge transistor on. To force the output from the
timer high, the voltage on the trigger input must drop below +(1/3) V CC. This turns
the discharge transistor off.
 Operational Amplifier

R. Explain integrator circuit using op-amp with derivation and input ,output
waveforms.
Op-Amp Integrator Definition: An op-amp integrator is a
circuit that uses an operational amplifier and a capacitor to
calculate the integral of an input signal, outputting a
voltage that reflects the cumulative effect of the input
signal over time.
Function: The primary function of an op-amp integrator is
to convert waveforms, such as turning a square wave into a
triangular wave, useful in signal processing and control
systems.
Design Principles: Effective integrator circuit design
requires careful selection of resistance, capacitance, and
op-amp characteristics, ensuring optimal performance
across expected signal frequencies.
Circuit Behavior: At its core, the integrator behaves like a
low-pass filter, better processing low-frequency signals
while reducing the impact of higher frequencies.
Practical Applications: Integrators are essential in
various technologies, including analog-to-digital conversion
and waveform shaping, highlighting their versatility in
electronics design.
What is an Op-Amp Integrator?
An op-amp integrator is a circuit that uses an operational
amplifier (op-amp) and a capacitor to perform the
mathematical operation of integration. Integration is the
process of finding the area under a curve or function over
time. An op-amp integrator produces an output voltage that
is proportional to the negative integral of the input voltage,
meaning that the output voltage changes according to the
duration and amplitude of the input voltage.

An op-amp integrator can be used for various

applications, such as analog-to-digital converters
(ADCs), analog computers, and wave-shaping circuits.
For example, an op-amp integrator can convert a
square wave input into a triangular wave output, or a
sine wave input into a cosine wave output.

An op-amp integrator is based on an inverting amplifier

configuration, where the feedback resistor is replaced by a
capacitor. The capacitor is a frequency-dependent element
that has a reactance (Xc) that varies inversely with the
frequency (f) of the input signal. The reactance of the
capacitor is given by:

where C is the capacitance of the capacitor

The schematic diagram of an op-amp integrator is shown

below:

The input voltage (Vin) is applied to the inverting input

terminal of the op-amp through a resistor (Rin). The non-
inverting input terminal is connected to the ground,
creating a virtual ground at the inverting input terminal as
well. The output voltage (Vout) is taken from the output
terminal of the op-amp, which is connected to the capacitor
© in the feedback loop.
The working principle of an op-amp integrator can be
explained by applying Kirchhoff’s current law (KCL) at node
1, which is the junction of Rin, C, and the inverting input
terminal. Since no current flows into or out of the op-amp
terminals, we can write:

Simplifying and rearranging, we get:

This equation shows that the output voltage is proportional

to the negative derivative of the input voltage. To find the
output voltage as a function of time, we need to integrate
both sides of the equation:

where V0 is the initial output voltage at t = 0.

This equation shows that the output voltage is proportional

to the negative integral of the input voltage plus a constant.
The constant V0 depends on the initial condition of the
capacitor and can be adjusted by using an offset voltage
source or a potentiometer in series with the capacitor.

What are some Characteristics and

Limitations of an Op-Amp Integrator?

An ideal op-amp integrator has infinite gain and bandwidth,

meaning that it can integrate any input signal with any
frequency and amplitude without distortion or attenuation.
However, in reality, there are some factors that limit the
performance and accuracy of an op-amp integrator, such as:

 Op-amp characteristics: The op-amp itself has finite

gain, bandwidth, input impedance, output impedance,
offset voltage, bias current, noise, etc. These
parameters affect the output voltage and introduce
errors and deviations from the ideal behavior.
 Capacitor leakage: The capacitor in the feedback loop
has some leakage resistance that allows a small
current to flow through it, causing it to discharge over
time. This reduces the integration effect and causes a
drift in the output voltage.
 Input bias current: The op-amp has some input bias
current that flows into or out of its terminals,
depending on its type and design. This current creates
a voltage drop across Rin and affects the input voltage
seen by the op-amp. This also introduces an error in
the output voltage.
 Frequency response: The frequency response of an
op-amp integrator depends on the reactance of the
capacitor, which varies with frequency. As frequency
increases, Xc decreases, making the capacitor act like
an open circuit. As frequency decreases, Xc increases,
making the capacitor act like a short circuit. Therefore,
the frequency response of an op-amp integrator is
inversely proportional to the frequency, or:

This equation shows that the voltage gain of an op-amp

integrator decreases by 20 dB per decade (or 6 dB per
octave) as the frequency increases. This means that an op-
amp integrator acts like a low-pass filter that attenuates
high-frequency signals and passes low-frequency signals.

However, this frequency response is not ideal for an

integrator, as it introduces phase shifts and distortion in the
output signal. Moreover, at very low frequencies, the
voltage gain becomes very large and may exceed the op-
amp’s output range, causing saturation or clipping.
Therefore, some modifications are needed to improve the
performance and accuracy of an op-amp integrator.

How to Improve an Op-Amp Integrator?

To optimize an op-amp integrator, consider modifications

like adding a parallel resistor (Rf) with the capacitor. This
adjustment curtails the voltage gain at lower frequencies,
avoiding saturation, enhancing stability, and minimizing
output voltage drift caused by capacitor leakage.

The voltage gain of this circuit is given by:

where Zf is the parallel impedance of Rf and Xc, and ||

denotes a parallel combination.

This equation shows that the voltage gain has a finite value
at DC (f = 0), which is -Rf/Rin. As frequency increases, the
voltage gain decreases by 20 dB per decade (or 6 dB per
octave) until it reaches a corner frequency (fc), where Rf =
Xc. At this frequency, the voltage gain is -Rf/2Rin. Beyond
this frequency, the voltage gain decreases by 40 dB per
decade (or 12 dB per octave) until it reaches the op-amp’s
bandwidth limit.

The corner frequency can be calculated by equating Rf and

Xc:
The corner frequency determines the range of frequencies
over which the circuit behaves like an integrator. Ideally,
this range should be as wide as possible for accurate
integration. Therefore, Rf should be chosen to be as large
as possible without causing saturation or instability.

 Adding a resistor in series with the capacitor: This

resistor (Rs) limits the current through the capacitor
and reduces the effect of input bias current on the
output voltage. It also improves the high-frequency
response of the circuit by creating a zero in
the transfer function. The modified circuit is shown
below:

The voltage gain of this circuit is given by:

where Zf is the series impedance of Rs and Xc.

This equation shows that the voltage gain has a zero at DC

(f = 0), where it is zero. As frequency increases, the voltage
gain increases by 20 dB per decade (or 6 dB per octave)
until it reaches a zero frequency (fz), where Rs = Xc. At this
frequency, the voltage gain is -Rs/Rin. Beyond this
frequency, the voltage gain decreases by 20 dB per decade
(or 6 dB per octave) until it reaches a pole frequency (fp),
where Rs + Xc = Rin. At this frequency, the voltage gain is -
1. Beyond this frequency, the voltage gain decreases by 40
dB per decade (or 12 dB per octave) until it reaches
decreases, making the capacitor act like an open circuit. As
a result, the gain of the op-amp integrator decreases as
frequency increases, following the relation:
This equation shows that the op-amp integrator has a
frequency response that rolls off at -20 dB per decade,
meaning that the output voltage decreases by a factor of 10
for every 10-fold increase in frequency. The frequency
range where the op-amp integrator works effectively
depends on the values of R and C, as well as the
characteristics of the op-amp itself.

How to Design an Op-Amp Integrator?

The design of an op-amp integrator involves choosing

appropriate values for R and C, as well as selecting a
suitable op-amp for the desired application. Some factors to
consider are:

 Integration time constant: The integration time

constant (τ) is the product of R and C, and it
determines how fast the capacitor charges or
discharges in response to the input voltage. A larger τ
means a slower integration, and a smaller τ means a
faster integration. The value of τ should be chosen
according to the expected frequency and duration of
the input signal, as well as the required accuracy and
stability of the output voltage. A general rule of thumb
is to choose τ such that it is much larger than the
period of the input signal, but much smaller than the
duration of interest for integration.
 Output voltage range: The output voltage range of an
op-amp integrator depends on the input voltage range,
the integration time constant, and the supply voltage of
the op-amp. The output voltage cannot exceed the
supply voltage limits of the op-amp, otherwise,
saturation will occur, and distortion will result. To
avoid saturation, the output voltage range should be
kept within a fraction of the supply voltage range,
leaving some margin for error and noise. The output
voltage range can be estimated by multiplying the
input voltage range by τ and dividing it by a safety
factor (such as 10).
 Op-amp characteristics: The op-amp used for an
integrator should have a high open-loop gain, a high
input impedance, a low output impedance, a low offset
voltage, a low bias current, a low noise, and a wide
 bandwidth. These characteristics ensure that the op-
amp can amplify and integrate any input signal with
minimal error and distortion. However, these
characteristics also depend on the frequency and
temperature of operation, so they should be checked
against the datasheet specifications of the op-amp. A
newer op-amp is usually better than an older one in
terms of performance and reliability.

What are some Examples of Op-Amp

Integrators?

Here are some examples of op-amp integrators with

different values of R and C, using a Texas Instruments
TLV9002 op-amp with a supply voltage of ±5 V.

Example 1: R = 10 kΩ, C = 0.1 μF

This op-amp integrator has an integration time constant of τ

= RC = 10 kΩ × 0.1 μF = 1 ms. This means that it can
integrate input signals with frequencies up to about 100 Hz
effectively. The output voltage range is estimated by
multiplying the input voltage range (±5 V) by τ and dividing
by 10, giving ±0.5 V. The frequency response rolls off at -20
dB per decade from about 100 Hz to about 250 kilohertz
(kHz). This is the useful frequency range of integrator
operation, and it is related to the op-amp gain-bandwidth
product (GBW). The GBW is a constant value that indicates
the maximum frequency at which the op-amp can provide a
certain gain. For example, if the GBW of an op-amp is 1
MHz, it means that the op-amp can provide a gain of 1 at 1
MHz, a gain of 10 at 100 kHz, a gain of 100 at 10 kHz, and
so on. The GBW can be found in the datasheet of the op-
amp and is usually specified for an open-loop configuration.

Example 2: R = 100 kΩ, C = 0.01 μF

This op-amp integrator has an integration time constant of τ

= RC = 100 kΩ × 0.01 μF = 1 ms, which is the same as the
previous example. However, the output voltage range is
different, because the input voltage range is different.
Assuming an input voltage range of ±0.5 V, the output
voltage range is estimated by multiplying the input voltage
range (±0.5 V) by τ and dividing by 10, giving ±0.05 V. The
frequency response rolls off at -20 dB per decade from
about 100 Hz to about 250 kHz, which is also the same as
the previous example.

Example 3: R = 1 kΩ, C = 1 μF

This op-amp integrator has an integration time constant of τ

= RC = 1 kΩ × 1 μF = 1 ms, which is again the same as the
previous examples. However, the output voltage range is
different, because the input voltage range is different.
Assuming an input voltage range of ±50 V, the output
voltage range is estimated by multiplying the input voltage
range (±50 V) by τ and dividing by 10, giving ±5 V. The
frequency response rolls off at -20 dB per decade from
about 100 Hz to about 250 kHz, which is also the same as
the previous examples.

Conclusion

An op-amp integrator is a circuit that uses an op-amp and a

capacitor to perform the mathematical operation of
integration. It produces an output voltage that is
proportional to the negative integral of the input voltage
over time. It can be used for various applications, such as
analog-to-digital converters, analog computers, and wave-
shaping circuits.

The design of an op-amp integrator involves choosing

appropriate values for R and C, as well as selecting a
suitable op-amp for the desired application. Some factors to
consider are:

 Integration time constant: It determines how fast the

capacitor charges or discharges in response to the
input voltage. It should be chosen according to the
expected frequency and duration of the input signal, as
 well as the required accuracy and stability of the
output voltage.
 Output voltage range: It depends on the input voltage
range, the integration time constant, and the supply
voltage of the op-amp. It should be kept within a
fraction of the supply voltage range, leaving some
margin for error and noise.
 Op-amp characteristics: The op-amp should have a high
open-loop gain, a high input impedance, a low output
impedance, a low offset voltage, a low bias current, a
low noise, and a wide bandwidth. These characteristics
ensure that the op-amp can amplify and integrate any
input signal with minimal error and distortion.

The frequency response of an op-amp integrator depends on

the reactance of the capacitor, which varies inversely with
frequency. As frequency increases, the gain of the op-amp
integrator decreases, following the relation:

This equation shows that the op-amp integrator has a

frequency response that rolls off at -20 dB per decade,
meaning that the output voltage decreases by a factor of 10
for every 10-fold increase in frequency. The frequency
range where the op-amp integrator works effectively
depends on the values of R and C, as well as the
characteristics of the op-amp itself. The GBW of the op-amp
is a constant value that indicates the maximum frequency at
which the op-amp can provide a certain gain.

Q. Explain the differentiator using opamp with circuit diagram

and waveforms.
Op-Amp Differentiator

An op-amp differentiator or a differentiator amplifier is a circuit configuration which

is inverse of the integrator circuit. It produces an output signal where the

instantaneous amplitude is proportional to the rate of change of the applied input

voltage.

Mathematically speaking, the output signal of a Differentiator is the first order

derivative of the input signal. For example, if the input signal is a ramp, then the

output of the circuit with an Operational Amplifier as Differentiator will be simple

DC (as the rate of change of ramp signal is constant). Similarly, if the input signal is a

sinusoid, then the output signal is also a sinusoid but with phase difference of 900.

A differentiator with only RC network is called a passive differentiator, whereas a

differentiator with active circuit components like transistors and operational

amplifiers is called an active differentiator. Active differentiators have higher output

voltage and much lower output resistance than simple RC differentiators.

An op-amp differentiator is an inverting amplifier, which uses a capacitor in series

with the input voltage. Differentiating circuits are usually designed to respond for

triangular and rectangular input waveforms.

Differentiators have frequency limitations while operating on sine wave inputs; the

circuit attenuates all low frequency signal components and allows only high

frequency components at the output. In other words, the circuit behaves like a high-

pass filter.
Ideal Op-Amp Differentiator Circuit

An op-amp differentiating amplifier uses a capacitor in series with the input voltage

source, as shown in the figure below.

For DC input, the input capacitor C1, after reaching its potential, cannot accept any
charge and behaves like an open-circuit. The non-inverting input terminal of the op-

amp is connected to ground through a resistor Rcomp, which provides the input bias

compensation, and the inverting input terminal is connected to the output through the

feedback resistor Rf.

Thus, the circuit behaves like a voltage follower.

When the input is a positive-going voltage, a current I flows into the capacitor C1, as

shown in the figure. Since the current flowing into the op-amp’s internal circuit is
zero, effectively all of the current I flows through the resistor Rf. The output voltage

is,

Vout = – (I * Rf)

Here, this output voltage is directly proportional to the rate of change of the input

voltage.

From the figure, node ‘X’ is virtually grounded and node ‘Y’ is also at ground

potential i.e., VX = VY = 0 .

From the input side, the current I can be given as:

I = C1 {d(Vin – VX) / dt} = C1 {d(Vin) / dt}

From the output side, the current I is given as:

I = -{(Vout – VX) / Rf} = -{Vout / Rf}

Equating the above two equations of current we get:

C1 {d(Vin) / dt} = -Vout / Rf

Vout = -C1 Rf {d(Vin) / dt}

Above equation indicates that the output is C1 Rf times the differentiation of the input

voltage. The product C1 Rf is called as the RC time constant of the differentiator

circuit. The negative sign indicates the output is out of phase by 1800 with respect to

the input.

The main advantage of such an active differentiating amplifier circuit is the small

time constant required for differentiation.

Input and Output Waveforms

Let us now see the output waveforms for different input signals. When a step input

(DC Level) with amplitude Vm is applied to an op-amp differentiator, the output can

be mathematically expressed as,

Vout = – C1 Rf {d(Vm) / dt}

For simplicity, assume the product C1 Rf is unity.

Therefore, Vout = 0 , because the amplitude Vm is constant and d(Vm) / dt = 0.

But practically, the output is not zero since the input step wave takes a finite amount

of time to rise from 0 volts to Vm volts. Hence, the output appears like a spike at time

t = 0, as shown in the figure below.

If the input to the differentiator is changed to a square wave, the output will be a

waveform consisting of positive and negative spikes, corresponding to the charging

and discharging of the capacitor, as shown in the figure below.

For sine wave input, which is mathematically represented as V (t) = Vm sin ωt, where

Vm is the amplitude of the input signal and t is the period, the output of the

differentiator is given as,

Vout = – C1 Rf {d(Vm sin ωt) / dt}

For simplicity, let us assume the product C1 Rf is unity.

Vout = – Vm. ω. cos ωt

Thus, the output of a differentiator for a sine wave input is a cosine wave and the

input-output waveforms are shown in the figure below.

Frequency Response of Ideal Differentiator

The gain of an op-amp differentiator is directly dependent on the frequency of the

input signal. Hence, for DC inputs where f = 0, the output is also zero. As the

frequency of the input signal increases, the output also increases. The frequency

response of an ideal differentiator is as shown in the figure below.

The frequency f1 is the frequency for which the gain of the differentiator becomes

unity. It can be seen from the figure that for frequency less than f1, the gain is less

than unity. For f1, the gain becomes the unity (0 dB) and beyond f1, the gain

increases at 20dB per decade.

Practical Op-amp Differentiator Circuit

For an ideal differentiator, the gain increases as frequency increases. Thus, at some

higher frequencies, the differentiator may become unstable and cause oscillations

which results in noise.

These problems can be avoided or corrected in a practical differentiator circuit, which

uses a resistor R1 in series with the input capacitor and a capacitor Cf in parallel with

the feedback resistor, as shown in the figure below.

The output voltage of the practical op-amp differentiating amplifier circuit is given as,

Vout = – C1 Rf {d(Vin) / dt}

i.e., the output voltage is C1 Rf times the differentiation of the input voltage.

The addition of resistor R1 and capacitor Cf stabilizes the circuit at higher

frequencies, and also reduces the effect of noise on the circuit.

Frequency Response of Practical Differentiator

The gain of the practical differentiator increases with increasing frequency and at a

particular frequency, f1, the gain becomes the unity (0 dB). The gain continues to

increase at a rate of 20dB per decade till the input frequency reaches a frequency, f2.

Beyond this frequency of the input signal, the gain of the differentiator starts to

decrease at a rate of 20dB per decade. This effect is due to the addition of the resistor

R1 and capacitor Cf. The frequency response curve of a practical differentiator is as

shown in the figure below.

Applications of Op-amp Differentiator

 Differentiating amplifiers are most commonly designed to operate on

triangular and rectangular signals.

 Differentiators also find application as wave shaping circuits, to detect high

frequency components in the input signal.

 Summary of Operational Amplifier as Differentiator

 An op-amp differentiating amplifier is an inverting amplifier circuit

configuration, which uses reactive components (usually a capacitor than

inductor).

 The differentiator performs mathematical differentiation operation on the input

signal with respect to time i.e., the instantaneous output voltage is proportional

to the rate of change of the input signal.

 Differentiating circuits are commonly used to operate on triangular and

rectangular signals. While operating on sine wave inputs, differentiating

circuits have frequency limitations.

. Q. Explain Opamp as a comparator with circuit diagram and waveform

Op-amp Comparator

The comparator is an electronic decision making circuit that makes use of an

operational amplifiers very high gain in its open-loop state, that is, there is no
feedback resistor.

The Op-amp comparator compares one analogue voltage level with another
analogue voltage level, or some preset reference voltage, VREF and produces an
output signal based on this voltage comparison. In other words, the op-amp
voltage comparator compares the magnitudes of two voltage inputs and
determines which is the largest of the two.

We have seen in previous tutorials that the operational amplifier can be used
with negative feedback to control the magnitude of its output signal in the linear
region performing a variety of different functions. We have also seen that the
standard operational amplifier is characterised by its open-loop gain AO and that
its output voltage is given by the
expression: VOUT = AO(V+ – V-) where V+ and V- correspond to the voltages at
the non-inverting and the inverting terminals respectively.

Voltage comparators on the other hand, either use positive feedback or no

feedback at all (open-loop mode) to switch its output between two saturated
states, because in the open-loop mode the amplifiers voltage gain is basically
equal to AVO. Then due to this high open loop gain, the output from the
comparator swings either fully to its positive supply rail, +Vcc or fully to its
negative supply rail, -Vcc on the application of varying input signal which
passes some preset threshold value.

The open-loop op-amp comparator is an analogue circuit that operates in its non-
linear region as changes in the two analogue inputs, V+ and V- causes it to
behave like a digital bistable device as triggering causes it to have two possible
output states, +Vcc or -Vcc. Then we can say that the voltage comparator is
essentially a 1-bit analogue to digital converter, as the input signal is analogue
but the output behaves digitally.

Consider the basic op-amp voltage comparator circuit below.

Op-amp Comparator Circuit

With reference to the op-amp comparator circuit above, lets first assume
that VIN is less than the DC voltage level at VREF, ( VIN < VREF ). As the non-
inverting (positive) input of the comparator is less than the inverting (negative)
input, the output will be LOW and at the negative supply voltage, -Vcc resulting
in a negative saturation of the output.

If we now increase the input voltage, VIN so that its value is greater than the
reference voltage VREF on the inverting input, the output voltage rapidly
switches HIGH towards the positive supply voltage, +Vcc resulting in a positive
saturation of the output. If we reduce again the input voltage VIN, so that it is
slightly less than the reference voltage, the op-amp’s output switches back to its
negative saturation voltage acting as a threshold detector.
Then we can see that the op-amp voltage comparator is a device whose output is
dependant on the value of the input voltage, VIN with respect to some DC
voltage level as the output is HIGH when the voltage on the non-inverting input
is greater than the voltage on the inverting input, and LOW when the non-
inverting input is less than the inverting input voltage. This condition is true
regardless of whether the input signal is connected to the inverting or the non-
inverting input of the comparator.

We can also see that the value of the output voltage is completely dependent on
the op-amps power supply voltage. In theory due to the op-amps high open-loop
gain the magnitude of its output voltage could be infinite in both directions,
(±∞). However practically, and for obvious reasons it is limited by the op-amps
supply rails giving VOUT = +Vcc or VOUT = -Vcc.

We said before that the basic op-amp comparator produces a positive or negative
voltage output by comparing its input voltage against some preset DC reference
voltage. Generally, a resistive voltage divider is used to set the input reference
voltage of a comparator, but a battery source, zener diode or potentiometer for a
variable reference voltage can all be used as shown.

Comparator Reference voltages

In theory the comparators reference voltage can be set to be anywhere between
0v and the supply voltage but there are practical limitations on the actual voltage
range depending on the op-amp comparator being device used.

Positive and Negative Voltage Comparators

A basic op-amp comparator circuit can be used to detect either a positive or a

negative going input voltage depending upon which input of the operational
amplifier we connect the fixed reference voltage source and the input voltage
too. In the examples above we have used the inverting input to set the reference
voltage with the input voltage connected to the non-inverting input.

But equally we could connect the inputs of the comparator the other way around
inverting the output signal to that shown above. Then an op-amp comparator can
be configured to operate in what is called an inverting or a non-inverting
configuration.

Positive Voltage Comparator

The basic configuration for the positive voltage comparator, also known as a
non-inverting comparator circuit detects when the input signal, VIN is ABOVE
or more positive than the reference voltage, VREF producing an output
at VOUT which is HIGH as shown.

Non-inverting Comparator Circuit

In this non-inverting configuration, the reference voltage is connected to the
inverting input of the operational amplifier with the input signal connected to the
non-inverting input. To keep things simple, we have assumed that the two
resistors forming the potential divider network are equal and: R1 = R2 = R. This
will produce a fixed reference voltage which is one half that of the supply
voltage, that is Vcc/2, while the input voltage is variable from zero to the supply
voltage.

When VIN is greater than VREF, the op-amp comparators output will saturate
towards the positive supply rail, Vcc. When VIN is less than VREF the op-amp
comparators output will change state and saturate at the negative supply
rail, 0v as shown.

Negative Voltage Comparator

The basic configuration for the negative voltage comparator, also known as an
inverting comparator circuit detects when the input signal, VIN is BELOW or
more negative than the reference voltage, VREF producing an output
at VOUT which is HIGH as shown.

Inverting Comparator Circuit

In the inverting configuration, which is the opposite of the positive configuration

above, the reference voltage is connected to the non-inverting input of the
operational amplifier while the input signal is connected to the inverting input.
Then when VIN is less than VREF the op-amp comparators output will saturate
towards the positive supply rail, Vcc.
Likewise the reverse is true, when VIN is greater than VREF, the op-amp
comparators output will change state and saturate towards the negative supply
rail, 0v.

Then depending upon which op-amp inputs we use for the signal and the
reference voltage, we can produce an inverting or non-inverting output. We can
take this idea of detecting either a negative or positive going signal one step
further by combining the two op-amp comparator circuits above to produce a
window comparator circuit.

Explain opamp as voltage follower .

Voltage Follower Definition: A voltage follower is

defined as an operational amplifier (op-amp) that
outputs the same voltage as its input, essentially
following the input voltage without amplification.
Input and Output Impedance: Voltage followers feature
high input impedance to prevent loading the source, and
low output impedance to efficiently drive the load.
Applications: Voltage followers are used in various
applications such as buffering for logic circuits and
active filters, ensuring stable voltage across the circuit
components.
Gain Explanation: While the voltage gain is unity (1),
voltage followers significantly enhance current gain,
making them valuable in power-sensitive circuits.
What is a Voltage Follower?
A voltage follower (also known as a buffer amplifier, unity-
gain amplifier, or isolation amplifier) is an op-amp circuit
whose output voltage is equal to the input voltage (it
“follows” the input voltage). Hence a voltage follower op-
amp does not amplify the input signal and has a voltage
gain of 1.

The voltage follower neither attenuates nor amplifies; it

simply buffers the signal.

A voltage follower circuit has a very high input impedance.

This characteristic makes it a popular choice in many
different types of circuits that require isolation between the
input and output signal.

The circuit of voltage follower is shown below.

An important law that underpins a voltage follower is Ohm’s

law.

voltage follower keeps the voltage the same—we didn’t say

it kept the current the same too!

While a voltage follower has unity voltage gain (i.e. it equals

one), it has a very high current gain.

So on the input side: very high impedance, and very low

current.

And on the output side: very low impedance, and very high
current.

Voltage stays the same, but the current goes up (because

impedance went down between the input and the output
side).

As mentioned: the input impedance of the op-amp is very

high (1 MΩ to 10 TΩ).

Due to its high input impedance, the op-amp minimally

loads the source, drawing only a small amount of current.
Because the output impedance of the op-amp is very low, it
drives the load as if it were a perfect voltage source.

Both the connections to and from the buffer are therefore

bridging connections.

This results in reduced power consumption in the source,

and less distortion from overloading and other causes of
electromagnetic interference.

Advantages of Voltage Followers

The advantages of voltage followers include:

Voltage followers provide significant power gain and current gain.

Low output impedance to the circuit, which uses the output of the voltage
follower.
The Op-amp takes zero current from the input.
Loading effects can be avoided.
Applications of Voltage Followers
Some of the applications of voltage followers include:

Buffers for logic circuits.

In Sample and hold circuits.
In Active filters.
In Bridge circuits via a transducer.

Explain construction and working principle

electromechanical relay
Electromechanical Relay
An electromechanical relay is a type of relay which function using a magnetic field
produced by an electromagnetic coil when a control signal is applied to it. It is called
as electromechanical since it has moving contacts in the output circuit which are
operated by applying an electrical signal.

Electromechanical Relay: Working Principle

An electromechanical relay transfers signals between its contacts through a
mechanical movement. It has three sections viz. input section, control
section and output section.

The input section consists of input terminals where a small control signal is to be
applied. The control section has an electromagnetic coil which gets energised when
control input signal is applied to the input terminals and the output section consists of
an movable armature and mechanical contacts – movable and stationary, the
movement of the armature makes or breaks the electrical circuit.
When an input control voltage is applied to the electromagnetic coil, it gets
magnetised and the armature is attracted by the magnetic field produced by the coil.
The movable mechanical contacts are attached to the armature, thus when the
armature moves towards the electromagnet, the contacts closes, making the output
circuit switched on. When the control signal is removed, the armature comes back to
its original position by the force of spring, making output circuit off.

Types of Electromechanical Relays

The electromechanical relays can be classified on the basis of their applications,
construction & operation, and contact configuration etc.
Classification of EMRs based on their applications

General Purpose Relays – Such as miniature relays, latching relays, timer relays,
contactors, machine tool relays, hybrid relays, smart relays, signal relays, automobile
relays and PCB relays etc.

Protection Relays – Such as thermal overload relays, earth fault relays, under or over
voltage relays, under or over current relays, buchholz relay, differential relays,
distance protection relays, sequence protection relays, electronic relays etc.
Classification of EMRs based on contact configurations
Single-Pole Single-Throw (SPST)
Single-Pole Double-Throw (SPDT)
Double-Pole single-Throw (DPST)
Double-Pole Double-Throw (DPDT)

Classification of EMRs based on their construction & operation

Electromagnetic Attraction Type Relay – Such as attraction armature type EMR,

solenoid type EMR, balanced beam type EMR.

Electromagnetic Induction Type Relay – Such as shaded pole type EMR, watt-hour
meter type EMR, induction cup type EMR.
Q.Explain Solid state relay working principle with diagram.

One of the most important components used in an electrical panel is a relay. Mostly,
people are familiar with standard electromechanical relays.

But, there is another type of relay which is also used widely for a large variety of
loads – mainly heavy and resistive types. This is a solid state relay (SSR). In this
post, we will understand the basic concept of a solid state relay.

What is a Solid State Relay?

As the name implies, solid state relay (SSR) works on semiconductors. In contrast to
an electromechanical relay which uses mechanical contacts to switch on or off a
circuit, there are no mechanical contacts inside the solid state relay.

Switching is done swiftly through semiconductors like triac, transistor, diode, and
thyristors. The technique works on either infrared light emitting diodes or LED
couplers to operate. Due to the use of semiconductors, the switching is very fast as
compared to a standard electromechanical relay.

Also, you can get a wide variety of control voltage from SSR, either fixed or variable,
due to the use of semiconductors. The solid state relay is mostly used for resistive
and heavy loads like heaters and heat tracings, which require a large amount of load
current.

Solid State Relay Working Principle

Refer to the below figure. As discussed before, solid state relay (SSR) does not have
moving parts. They consist of semiconductors and electronic parts.
 Pin
The input circuit consists of a LED which is triggered by the input voltage. Then,
there is isolation between input and output circuits.

The output circuit consists of a photo-coupler for capturing the light and converting it
into electrical energy for the load drive circuit (consisting of either triac, diodes,
transistors, or thyristors).

When the power supply is applied to the input circuit, current flows through LED
which emits light from it. The photo-coupler detects it and converts it into an
electrical voltage which is then fed to the load drive circuit, for controlling the final
output voltage to the load. When the input voltage turns off, the load too turns off.

Due to the use of Opto-coupling technology, the switching is swift, sensitive, and has
high insulation levels. The output voltage can be digital or analog, depending upon
the input circuit and load drive circuit used.

Types of Control for Solid State Relays

There are three types of control methods available for solid state relays (SSR).

They are as follows

1. Random Turn-On of Solid State Relay

2. Zero crossing of Solid State Relay
3. Proportional Control of Solid State Relay
Random Turn-On of Solid State Relay
 When the input voltage is applied as shown in the figure, the output voltage
immediately turns on and is applied for the whole AC cycle as long as the
input voltage is on.

 Pin
As soon as it turns off, the output voltage also turns off.

Zero Crossing of Solid State Relay

As shown in the figure below, when the input voltage is applied, the output voltage
does not immediately turn on; rather it starts the cycle as soon as it touches the next
available zero point in the waveform.

 Pin
Then, it is applied for the whole AC cycle as long as the input voltage is on. When the
input voltage is released, the output voltage does not immediately turn off; rather it
stops the cycle as soon as it touches the next available zero point in the waveform.
 Proportional Control of Solid State Relay

The earlier two types we discussed were digital output types. As the name implies,
proportional control solid state relay provides an analog output.

 Pin
According to the input voltage given, the output voltage will be given accordingly.
This type is used for PID control of heaters and other devices, where accurate control
of temperature is required.