Unit 3.

Processor Organization and

Architecture
Mrs. Neha Mahajan
Introduction
Introduction
Half Adder
Full Adder
Multiplexers and Demultiplexer
 What is a Multiplexer (MUX)?
• A MUX is a digital switch that
Multiplexer
has multiple inputs (sources) Block Diagram
and a single output
(destination).
• The select lines determine 2N 1

MUX
Inputs Output
which input is connected to the (sources) (destination)

output.
• MUX Types N
→ 2-to-1 (1 select line)
Select
→ 4-to-1 (2 select lines) Lines
→ 8-to-1 (3 select lines)
→ 16-to-1 (4 select lines)
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 Multiplexer
⚫ A multiplexer has
− 2N data inputs
− 1 output
− m control inputs
− where m = 2n
⚫ A multiplexer routes (or connects) the selected
data input to the output.
− The value of the control inputs determines the
data input that is selected.
Multiplexer
 Typical Application of a MUX
Multiple Sources Selector Single Destination

MP3 Player
Docking Station

D0
Laptop D1

MUX
Sound Card Y
D2

D3

Surround Sound System

Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
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 2-to-1 Multiplexer (MUX)

Data
inputs
Control Z = A′.I0 + A.I1
input
 4:1 Multiplexer (MUX)

A B Z
0 0 I0
0 1 I1
1 0 I2
1 1 I3

MSB LSB

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4-to-1 Multiplexer (MUX)

D0

MUX
D1
Y
D2

D3

B A

A/ B/
Y
S1 S0
0 0 D0

0 1 D1

1 0 D2

1 1 D3

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4:1 MUX using 2 : 1 MUX
 8:1 MUX
Truth Table – 8 To 1 MUX

A B C Z
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

MSB LSB
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
Logic Diagram of 8:1 MUX
 Exercise:
Design an 8-to-1 multiplexer using
4-to-1 and 2-to-1 multiplexers only.
8:1 Mux using 4 : 1 Mux
 Exercise:

Design a 16-to-1 multiplexer using

8-to-1 and 2-to-1 multiplexers only.
16:1 Mux using 8 : 1 Mux S3
Select Lines

S2 S1 S0
o/p

0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I 10
1 0 1 1 I 11
1 1 0 0 I 12
1 1 0 1 I 13
1 1 1 0 I 14
1 1 1 1 I 15
 What is a Demultiplexer (DEMUX)?

• A demultiplexer performs the

Demultiplexer
opposite function of a Block Diagram
multiplexer.
• A DEMUX is a digital switch
with a single input (source) and

DEMUX
1 2N
a multiple outputs Input Outputs
(source) (destinations)
(destinations).
• The select lines determine
N
which output the input is
connected to. Select
Lines

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 Demultiplexers
⚫ A demultiplexer has
− N control inputs
− 1 data input
− 2N outputs

• DEMUX Types
→ 1-to-2 (1 select line)
→ 1-to-4 (2 select lines)
→ 1-to-8 (3 select lines)
→ 1-to-16 (4 select lines)
 Typical Application of a DEMUX
Single Source Selector Multiple Destinations

B/W Laser
Printer

Fax
Machine

D0

DEMUX
X D1

D2 Color Inkjet
Printer
D3

B A Selected Destination
0 0 B/W Laser Printer Pen
0 1 Fax Machine Plotter

1 0 Color Inkjet Printer

1 1 Pen Plotter

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1-to-4 De-Multiplexer (DEMUX)
D0

DEMUX
D1
X
D2

D3

B A

B A D0 D1 D2 D3

0 0 X 0 0 0

0 1 0 X 0 0

1 0 0 0 X 0

1 1 0 0 0 X

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1 : 8 DEMUX
1 : 8 DEMUX using two 1:4 DEMUX
1:16 DEMUX using
two 1:8 DEMUX
 Encoding and Decoding :
• When connecting a logic circuit with the outside
world, incoming information from a keyboard or
other input device must be changed (encoded)
into an appropriate binary form.
• Also before binary data produced by the digital
system can be used by an output device, such as
a display, it must be decoded into a form that
can be used by the display.
• Encoders and decoders used for such jobs are
also combinational logic circuits
 Encoding and Decoding :
• For example text may be represented by an ASCII code
(American standard Code for Information
Interchange), in which each letter, number or symbol
is represented by a 7-bit binary code.
• Decimal numbers in a calculator may be sent to a
numeric display using BCD (Binary Coded Decimal).
• the word ‘code’ appears in each of these titles, and a
binary code differs from normal binary because it is
arranged in a particular way to suit a given purpose.
 ENCODERS & DECODERS

A0 O0 A0 O0
A1 O1 A1 O1
A2 O2 A2 O2
A3 ENCODER DECODER O3
A4 O4
A5 O5
A6 O6
A7 O7

Only one input activated Only one output activated

at a time at a time
 Encoder

⚫ An encoder has
− 2N inputs
− N outputs
⚫ An encoder performs the inverse operation of a
decoder.
⚫ Input: Only one of the inputs may be True/Active at one time.
⚫ Output: An encoder outputs the binary value of the selected
(or Active) input. A binary code/number corresponding to the
True input. The encoder produces a binary code on the output
pins, which changes in response to the input that has been
activated.
4:2 Encoder
 Decoder
⚫ A decoder has
− n inputs
− 2n outputs

⚫ A decoder selects one of 2n outputs by decoding the binary

value on the n inputs.
• Input: A binary code. (The code can be thought of as a binary
number.)
• Output: A single output corresponding to that code becomes
True which means Exactly one output will be active for each
combination of the inputs.
2:4 Decoder
 3:8 Decoder
MSB
Sequential Circuit
Flip Flops
Uses of Flip Flops
S-R Flip flop with Preset and Clear
SR flip flop to JK flip Flop
JK Flip flop using NAND gates
JK Flip flop Truth Table
Fig. 1

Fig. 2
 D Flip flop
▪Make R input equal to S' → gated D latch.
▪D latch eliminates the undesirable condition of invalid state
in the S-R latch.

D D Q
EN
Q
Q'
EN

Q
'
 D Flip flop
▪ When EN is HIGH,
❖D=HIGH → latch is SET
❖D=LOW → latch is RESET

▪ Hence when EN is HIGH, Q ‘follows’ the D

(data) input.
▪ Characteristic table: EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change
 What is Register?
• Registers are the smaller and the fastest accessible memory
units in the central processing unit (CPU).
• A set of flip-flops forms a register. A register is a unique high-
speed storage area in the CPU. The information is always
defined in a register before processing. The registers speed up
the implementation of programs.
• A register can hold the instruction, address location, or
operands.
• Registers implement two important functions in the CPU.
operation are as follows −
a) It can support a temporary storage location for data. This
supports the directly implementing programs to have fast
access to the data if required.
b) It can save the status of the CPU and data about the directly
implementing program.
 Registers
• It is a special temporary storage location
within the CPU.
• Registers quickly accept, store and transfer
data and instructions that are being used
immediately.
• To execute an instruction, the control unit of
the CPU retrieves it from main memory and
places it onto a register.
 Inside the CPU
• The CPU is the brain of the
computer.
• It is the part that actually
executes
the instructions.

• Let’s take a look inside.

 Inside the CPU (cont.)
Memory Registers Temporary Memory.
Computer “Loads” data from
Register 0 RAM to registers, performs
operations on data in registers,
and “stores” results from
Register 1 registers back to RAM

Register 2
Register 3

Remember our initial example: “read value of A from memory; read

value of B from memory; add values of A and B; put result in
memory in variable C.” The reads are done to registers, the
addition is done in registers, and the result is written to memory
from a register.
 Inside the CPU (cont.)
Memory Registers
Register 0 Arithmetic
Register 1 / Logic
Unit
Register 2
Register 3
For doing basic
Arithmetic / Logic
Operations on Values stored
in the Registers
 Inside the CPU (cont.)
Memory Registers
Register 0 Arithmetic
Register 1 / Logic
Unit
Register 2
Register 3
To hold the current
instruction
Instruction Register
 Inside the CPU (cont.)
Memory Registers
Register 0 Arithmetic
Register 1 / Logic
Unit
Register 2
Register 3
To hold the
Instruction Register address of the
current instruction
Instr. Pointer (IP)
in RAM
 Inside the CPU (cont.)
Memory Registers
Register 0 Arithmetic
Register 1 / Logic
Unit
Register 2
Register 3
Control Unit
Instruction Register (State Machine)

Instr. Pointer (IP)

Instruction Format
Instruction Format example

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Instruction Format

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 Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86
Instruction cycle
 Instruction cycle
• Instruction are fetched and executed by the control unit one
by one. The sequences involved for the fetch of one
instruction and its execution are known as instruction cycle.
• The Instruction Cycle details the sequence of events that takes
place as an instruction is read from memory and executed.
• In a Fetch Cycle, instruction to be executed is fetched from the
memory to the processor.
• The Decode Cycle is responsible for recognizing which
operation the instruction represents activating the correct
circuitry to perform that operation.
• During the Execute Cycle, the operation specified by the op-
code is performed on user provided data in the ALU.
• In the Store Cycle, the results from the execution cycle are
stored back to the memory.
Instruction cycle State Diagram
State Diagram for Instruction Cycle
• Instruction Address Calculation (IAC) − The address of the next instruction
is computed by adding a fixed number to the previous instruction address.
• Instruction Fetch (IF)− The instruction is read from its specific memory
location to the processor.
• Instruction Operation Decoding (ID) − The instruction is interpreted which
determines the type of operation to be performed and the operands to be
used are decided. This is called as Instruction decoding. It is carried out in
the part of control unit called Instruction decoder.
• Operand Address Calculation (OAC) − The address of the operand is
calculated that is to be fetched from memory or I/O space.
• Operand Fetch (OF) − The operand is fetched from the memory or read
from the I/O device by sending the operand address computed in OAC
stage.
• Data Operation (DO or EXEC) − The actual operation that the instruction
contains is executed.
• Operands Store (OS)− It can store the result acquired in the memory or
transfer it to the I/O.
Instruction Fetch (IF)
Instruction Operation Decoding
(ID)
Operand Fetch (OF)
Data Operation (DO or EXEC)
Operand Store (OS)
Instruction Cycle Steps
 Instruction Sequencing
Example – an instruction to add the contents of two registers (Rx and Ry)
and place result in a third register (Rz)

Step 1: Get the ADD instruction from memory into an instruction register

Step 2: Decode instruction

Instruction in IR has the code of an ADD instruction
Register indices used to generate output enables for registers Rx and Ry
Register index used to generate load signal for register Rz

Step 3: execute instruction

Enable Rx and Ry output and direct to ALU
Setup ALU to perform ADD operation
Direct result to Rz so that it can be loaded into register
 Straight line sequencing

• Straight line sequencing means the instruction

of a program is executed in a sequential
manner(i.e. every time PC is incremented by a
fixed offset).
• And no branch address is loaded on the PC.
 Example of Straight line sequencing

• Here, programs and data are stored in the same memory, i.e. von
Neumann architecture.
• First instruction of a program is stored at address i. PC gives address i and
instruction stored at that address i is fetched from the memory and then
decoded and then operand A is fetched from the memory and stored in a
temporary register and then the instruction is executed(i.e. content of
address A is copied into processor register R0).
• Side by Side during decoding or execution, the PC gets incremented by
4(i.e. it contains the address of the next instruction) because the
instruction and memory segment is of 4 bytes. So the instruction at
address i is executed.
• So every time, the PC is incremented by 4. Therefore, the program is
executing in a sequential manner. And this process is called straight line
sequencing.
straight line sequencing.