1UNIT The 741 IC Op-Amp

CONTENTS
********************************* 1-2A to 1-15A
Part-1 The 741 IC Op-Amp
General Operational
Amplifier Stages (Bias
Circuit, the Input Stage,
The Second Stage,The Output
Stage, Short Circuit Protection
Circuitry), Device Parameters,
DC and AC Analysis of Input State,
Second Stage and Output Stage

Part-2 Frequeney Response of 741, ..1-154 to 1-19A

Simplified Model, Gain,
Slew Rate, Relationship Between
and Slew Rate

1-1A (EC-Sem-5)
1-2A (EC-Sem-5) The 741 IC Op-Amp

PART1
The 741 IC Op-Amp: General Operational Amplifier Stages
(Bias Circuit, the Input Stage, The Second Stage, The Output
Stage, Short Circuit Protection Circuitry), Device Paramneters,
DC and AC Analysis of Input State, Second Stage
and Output Stage.R

cONCEPT OUTLINE

The IC-741 is a widely used as general purpose Op-Amp. It is

divided into 3 stages:
i Input differential amplifier
i. The gain stage
ii. The output stage
The Op-Amp is supplied with positive and negative supply
voltages of value 15 V.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 1.1. Write a short note on 741 Op-Amp circuit and discuss
the bias circuit.
OR
Write the characteristics of ideal Op-Amp.

Answer
A Op-Amp circuit :
1. Generally BJT based Op-Amp is focused on 741 Op-Amp circuit. If we
use IC design, the circuits use large number of transistors but relatively
few resistors and only one capacitor.
2. The block diagram of typical Op-Amp is shown in Fig. 1.1.1
No
inpuo- Level
"P* Input Intermediate shifting
O/P
O/P
Btage stage stage
Inverting stage
input
Fig. 1.1.1. Block diagram of Op-Amp.

3. The equivalent circuit of Op-Amp is shown in Fig. 1.1.2.

Tntegrated Circuits 1-3A (EC-Sem-5)

InvertingV2
input
op
Non-inverting o
input V AVid

EE
Fig. 1.1.2. Equivalent cireuit of Op-Amp
B. Characteristics of ideal Op-Amp:
1. Infinite voltage gain, A, = o.
2. Infinite input resistance, R, *.
3. Zero output resistance, R, = 0.

4. Zero output voltage when input voltage is zero.

5. Infinite bandwidth.
C. Bias circuit:
1 The bias cireuit is used to provide proportional current in the colleetor of
transistor.

2. Some transistors form the current mirror, in which transistor collector

provides bias current for other output stage of Op-Amp.
3. Finally some transistors works to provide the Vas drop between the
bases of output transistors for proper functioning of the device.

Que 1.2.Explain the three stages of Op-Amp, ie, input differential

stage, an intermediate single-ended high gain stage and an output
buffering stage. Mention device parameters for the npn and pnp
transistors.
Answer
A Stages of Op-Amp:
i Input stage:
1. The input stage consists of transistors for biasing purpo0se, transistor
also acts as emitter followers, causing the input resistance to be high
and delivering the differential input signal to the differential common
base amplifier.
2. The input stage is the differential version of the common-collector
common-base configuration.

3. The combination of transistors and resistors form the current mirror

(load circuit). It provide not only high-resistance load but also converts
the signal from differential to single-ended form with no loss in gain or
common-mode-rejection.
 The 741 1C Op-Amp
1-4A (EC-Sem-5)
function is to shift the DC
circuit includes level shifter whose
a
4.
Op-Amp that signal at output c a n swing
positive and negative.
level
of the signal so
ii. Second stage :
and two
transistors
1. The second or intermediate stage composed of some
as emitter
follower and provide high input
resistors. Transistor act
resistance. They also minimize loss of gain.
transistor. Capacitor
taken at the collector of
2. The output second stage is
of of second stage to provide frequency
is also connected in the feedback path
compensation.

iii. Output stage :

a low output resistance.
1. The output stage is to provide the amplifier with
currents without
The output stage also supplies relatively large load
dissipating large amount of power.

2. The output circuit is a class AB output stage. To keep emitter-follower

transistor conducting at all times to ensure the low output resistance.
When bias current I is greater than load current i , this is called class A
operation.
The power dissipation in output stage is reduced by arranging transistors
to turn ON only when an input signal is applied. Such arrangement is
known as class B operation.
B. Device Parameters:
For standard npn and pnp transistors.

npn: I, 10-4A, B
= = 200
and A 125 V.
pnp: 1, 10-14 A, B 50 =

and VA 50 V.
i For parallel base-emitter junction,
npn ,= 0.25x 10-14 A
pnp: 7, = 0.75 x 10-14 A

Que 13.Describe what is mean by output short circuit protection

and explain how it is achieved in the output stage of IC741.

OR
AKTU 2019-20, Marke 07
How the short circuit protection is achieved in the output stage of
741 Op-Amp?
OR
AKTU 2018-19, Mark 3.5
Find out the output resistance of 741 Op-Amp.
Answer

1. The short-circuit protection circuitry is shown in the

Fig. 1.3.1
Integrated Circuits 1-5A (EC-Sem-5)

2. The Op-Amp 741 contains a number of transistors that are normally in

the OFF state.

When the output terminal gets shorted to the ground, while keeping a

positive output voltage due to

certain input signal, this will induce a

large current in the output transistor 4

4 This will result in producing heat and cause burn-out of the transistor.
Therefore, when in
flow Q4 reaches
current 20 mA,
voltage drop across
R becomes 27 x 20 = 540 mV, which bias the transistor Q15

5. Similarly, the maximum current in Q20 is limited by R,, Q, and

4
6. When the current increases, the voltage drop across R, becomes sufficient
and the transistor G2 becomes ON and Q21 and Q24 shunt the excess
current away from the transistor Q20 hence protects the output
transistor.

Q13A
13A

R27
L9 R
R1o =

50 ka

| 20

R
50 kO
50k

Fig. 1.3.1.

Output resistance of 741 Op-Amp:

The output resistance of the Op-Amp Rout is determined from the
Fig. 1.3.2. In accordance with the definition of R,ut the input source
feeding the output stage is grounded, but its resistance is included.

2 We have assumed the

that v, is
output voltage is
negative and thus 20
conducting most of the current; transistor Q14 has theretore been
eliminated. The exact value of the output resistance wil depend on
which transistor (Q14 or Q20) is conducting and on the value of load

curre

3. The resistance of emitter of Q2 is

1-6 A (EC-Sem-5) The 741 IC Op-Amp

Ro23 e23
This resistance
appears in parallel with the series combination
of ro13A
and the resistance 1 8 19 network.

4. Since ro13A alone is larger than R.23. the effective resistance between
the base of Q20 and ground approximately to R23. the output resistance
out as

R
5.
RoutPa* +Te20
The output resistance of the 741 is specified to be typically 750.

Q13A
To13A

Rio TLarge Ro23

Rout e20B0+1
resistance
20

23
Ro2 Ro2
"out +1 Te23
Fig. 18.2.

Que 14. Discuss the DC analysis of input stage of 741 1C Op-Amp.

Answer
Reference bias current: The reference bias current
in the branch composed REpis generated
of the two diode-connected transistors Q1 and
12 and resigtor Rg
RER V-VxVaE(-Vx
For Vcc= VEE= 15 Vand VHE11EDi2 0.7V, we have IgEg =0.73 mA.
=

1. Transistor , is biased by REP and the voltage

used to bias Which has series
developed across it is
0 a emitter resistance
R,.
Integrated Circuits 1-7 A (EC-Sem-5)

c10

VEE
Fig. 14.1. The Widlar eurrent source that biases the input
stage
2. This part of the circuit is redrawn in Fig. 1.4.2 and can be recognized as
the Widlar current source.
3. From the circuit, and assuming B0 to be large, we have

VBE11-VEE10 ciR
Thus, V = I n z =IciR .(1.4.1)
co

+Vcc

21 V

21
12/18

21/pp

Fig. 14.2.Tho DC analysis of the 741l input stage.

where it has been assumed that

Is10s11
4 Substituting the known values for REE und R,, eq. (1.4.1) can be solved
by trial and error to determine c1o For our case, the result is lc1o= 19 juA.
 The 741 1C Op-Amp
1-8A (EC-Sem-5)

proceeddetermine the DC current in

to
5. Having determined Ic1o we
i8 redrawn in
the input-stage transistors. Part of the input stage
each of that
Fig. 1.4.2. From symmetry, we see

6.
e
Denote this current by . We see that if the npn ß is high, then

and e, equal, with a value of

and the base currents of Q3 are

devices.
INB, + 1)=IB, where B, denotes p of the pnp
7. The current mirror formed by e, and , i s fed by an input current of 2/,
we can express the output current of the mirror as

2
le 1+2/TP,
8. We can now r i t e a node equation for node X in Fig. 1.4.3 and thus

determine the value of 1. If P, > 1, then this node equation gives

21= Ic0

0
B16

s
VPN
-1R
Pig. 14.3.

9. For the 741, Ic1o= 19 uA; thus I = 9.5 uA. We have thus determined that

10.
ceaca=leu=9.5 pA
Fig. 1.4.3 shows the remainder of the 741 input stages. This part of the
circuit is fed by 1cs =lcs=1. Transistors , and Qg are identical and have
equal resistances , and R, in their emitters,

..(1.4.2)
Integrated Circuits 1-9A (EC-Sem-5)

Now if the base currents of Q, and Qj6 Can be neglected, then

..1.4.3)
and
ceca .(14.4)
11. Thus both the symmetry of , and Q; and the node equations at their
collectors force their currents to be equal and to equal 7.
12. The bias current of Q, can be determined from

..(1.4.5)

where By denote p of the npn transistors. To determine VaE6 We use the

transistor exponential relationship and write

BE6V7n
13. Substituting Is = 10 A and I = 9.5 mA results in VBE = 517mV. Then
substituting in eq. (1.4.5) yields Ic = 10.5 mA.

Que 1.5. Explain the DC analysis of second stage and output

stage of7411C Op-Amp.
Answer
A Second-Stage:
1. If we neglect the base current of Q23 from Op-Amp circuit then the
collector current of Q7 is approximately equal to the current supplied by
current source &138

Because Q138 has a scale current 0.75 tinmes that of Q2 its collector
current will be Ic138 =0.751REF Where we have assumed that B,> 1.
Thus Ici38=550 pA and Ici3= 550 uA.
3. At this current level the base-emitter voltage for Q17 is

VBE17 VIn 618 mV

4. The collector current of 16 can be determined from

c6E16B17+
5. This calculation yields c1616.2 uA.
B. Output-stage Bias:
1. Fig. 1.5.1 shows the output stage of the 741 with the short-circuit
protection circuitry omitted.
2. Current source Q134 delivers a current of 0.25/ REE (because I, of Q134 is
0.25 times the I, of Q,,) to the network composed of s 1 and
R10
3. If we neglect the base current of 4 and Q20, then the emitter current
of Q2 will also be equal to 0.25 /pEP Thus
 The 741 IC Op-Amp
1-10A (EC-Sem-5)

E230.2511pEF= 180 uA
c is only 180/50 = 3.6 juA, which
Thus we s e e that the base current of Q2
4 have assumed.
1s negligible compared to
Ie17 as we

determine the
is approximately 0.6 V,
we can
. We assume that VBE18
current in Ri, as 15 uA.

6. The emitter current of Q1s is therefore

E18 180- 15 = 165 A

C1s18 165 uA
Also,
At this value of current we find the VREI8 =
588 mV, which is quite close
of Q1s is 165/200 0.8 mA,=

to the value assumed. The base current

which can be added to the current in Rjo
to determine the 19 Current as
c19g1915.8uA be
the base-emitter junction of 19 can now
8. The voltage drop across

d e t e r m i n e d as,

BE19VTln 530 mV
9 Voltage drop, BBBEi8+BE19
688 +530 =1.118 V
across the series combination of the base-emitter
10. Since VBB appears
write
Junctions of 14 and Q20, we can

VBB Vln V, ln c
Is4 _20
+Vcc

Q13A
.2b IREF

19
OV

R10
40 ka

0.25 IREr

Pig. 1.5.1.The 741 output stage without the

ghort-circuit protection device8.
Integrated Circuits 1-11 A (EC-Sem-5)

11. Using calculated values of VBn and substituting

S 4 s 2 0 3 x 10-14A

12. We determine the collector current as,

c4c2o= 154 mA
13. This is the small current at which the class AB output stage is biased.

Que 1.6. Explain the input stage of small signal analysis.

Answer
1. Fig. 1.6.1 shows part of the 741 input stage for the purpose of pertorming8
small-sigmal analysis.
2. The collector of &, and Q2 are connected to a constant DC voltage and
are shown grounded. The input signal is applied between the input

terminals of Q, 923 and Q

where andr, are the emitter current and resistance respectively.

3. Four transistors, through , supply the load eircuit with a pair of

complementary current signals a

Rid
tai
PA1LA1.8l oalanalyniotthe 741 input atage
R44 1)r.
is input diferential resistance.
where, Ria
The output currenti, is
i 2x a
5. The transconductance of input stage,
1-12A (EC-Sem-5)
The 741 IC Op-Amp

6. The output resistance is, R, =r, [1 +8,(Rgl|r,)

of the second stage of
Que 1.7. Determine the small-signal model
the 741 Op-Amp. AKTU 2017-18, Marks 05
Answer
1. Fig. 1.7.1 shows the 741 second stage Op-Amp prepared for small-signal
analysis. Now we analyze the second stage to determine the values of

the parameters of the equivalent circuit shown in Fig. 1.7.2.

Input resistance : The input resistance R,2 can be found by
Ra = (P16 t 1D r 6 + IRg l| (P17+ 1) 7 + R)}} ...(1.7.1)
MN.
Substituting the appropriate parameter values yields R2=4
b. Transconductance:
L From the equivalent circuit of Fig. 1.7.2, we see that the transeonductance
G2 is the ratio of the short-circuit output current to the input voltage.
i. Short-circuiting the output terminal of the second stage to ground makes
the signal current through the output resistance of 13B zero, and the

output short-circuit current becomes equal to the collector signal

current
to a s follows
of Q17(017). This c a n be easily related u,2
17
ie17 +R (1.7.2)

..(1.7.3)
17 2
(R, || R,7) +Tae
R17 (Pi7 t 1)Ca1 *Ra ..(1.7.4)
where we have neglected roi6 because ro16> R

L Q13
16 e17
17

Rg

R17
Integrated Circuits 1-13 A (EC-Sem-5)

ii. These equations can be combined to obtain

G2 ..(1.7.5)
2

B16
C17
0Z

I---

Fig. 1.7.2. Small-signal equivalent-circuit model of the second

stage
. Output resistance:

T o determine the output resistance R of the second stage in Fig. 1.7.1

terminal and find the resistance looking back into
we ground the input
the output terminal.

. So, R,2is given by

RR138s|R,7)
where R38 is the resistance looking into the collector Q138 while its
base and emitter are connected to ground and R17 is the resistance
looking into the collector of ,7

Que 1.8.| Deseribe the all stages of small signal analysis of the 741
Op-Amp.
Answer
A Input Stage: Refer Q. 1.6, Page 1-11A, Unit-1.
B. Second Stage: Refer Q. 1.7, Page 1-12A, Unit-1.
C. Output Stage: The 741 output stage without short circuit protection
circuit is shown in Fig. 1.8.1.

Output voltage limits

1. The maximum positive output voltage is linmited by the saturation of
current-source transistor 134
Thus, ...(1.8.1)
Vomaxcc-VCEsat-VBE14
o min-VE+VCE aa t+ Eb2+EB20 (1.8.2)
 1-14A (EC-Sem-5) The 741 1C Op-Amp

+Vcc
13B 13A

LQ19
R10 R=2 kn

Q20
P23
Q23
EE

Output sage
Fig. 1.8.1.
2. Small signal model is shown in Pig. 1.8.1.

2 D23 Out
ww

o2 Vi3 Rin3 o2 Gyo3o2 RL

Fig. 1.8.2. Small sigaal model for the 741 output etage.

3. Open circuit voltage gain G. =

Vo2 IR
Circuit for finding out the output resistance is shown in Fig. 1.8.3.
5. Resistance seen looking into emitter of Q23 1S

6.
RaBt1*a
Since ro134 alone i8 much larger thanR.g 80 effective resistance between
the base Q2 and ground is equal to
of Ro23
7. Now, output resistance (R)is
R..
out
=
B20+1 +
Te20
 Integrated Circuits 1-15A (EC-Sem-5)

Q13A

To13A
L 18
R102 Ro23
Large resistanceoute20 P20
Q18

Ro2
R2 +e23
Bas+
Fig. 1.8.3. Circuit for finding the output resistance Rout

PART 2
Frequeney Response of 741, a Simplified Model, Gain, Slew
Rate, Relationship Between f, and Slew Rate.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 1.8.Draw and explain the frequency response of IC 741.

AKTU 2018-19,Marke 3.5

Answer
1. The system employs the Miller compensation technique.
2 A capacitor (C) of about 30 pF is connected in the negative feedback
path of the second stage.
3. An estimation of frequency of poles can be obtained as,
n C + |A,))
A = Gain of second stage
 1-16 A (EC-Sem-5)
The 741 IC Op-Amp
Let
A =-515
then
in15480 pF
Since, this value of capacitor is
between the base and
large so we neglect all other capacitances
ground of transistor.
5. The total resistance,
R = (R,|| R
= (6.7 MSQ ||4 MQ)
= 2.5 M2
6. The dominant pole has a
frequency Ip
= 4.1 Hz

7.
2nCR,
Calculate all the values of poles and a bode
plot is shown in Fig. 1.9.1
f=A,faaB = 243147 x 4.1 = 1 MHz
where, f, is unity-gain bandwidth.

A | dB
A= 107.7 dB

-20 dB/decade

fa dB 4.1 Hz f= A3 aB =1 MHz

ig. 1.9.1. Bode plot for the 1C 741

gain
9 Bode plot signifies that the phase
shift at f, is 90° and thus phase
-

margin is 90°. This

phase margin is sufticient to provide stable
of
closed-loop amplifiers with any value of feedback factor
operation
p.
Que 1.10. Draw the frequeney response of IC741. Give the upper
and lower 3-dB frequency of same.

Answer
A Frequency response: Refer Q. 1.9, Page 1-15A, Unit-1.
B. Upper and lower
3-dB frequency: The magnitude of open loop gain
of Op-Amp is given by,
A = 4
V1+f1¥
i. The open-loop gain A is
approximately constant from 0 Hz to
break
frequeney /1
Integrated Circuits 1-17A (EC-Sem-5)

A|in dB)

100 3dB
-20 dB/decade
0
Or
6 dB/octave
40

10 10 103 104 105 10 10 RHz)

Fig. 1.10.1. Frequency responae of IC 741 Op-Amp

i Whenf=f, the gain A is 3-dB down from its value at 0 Hz. Hence, the
break frequency is called 3-dB frequency or corner frequency or
lower 3-dB frequency.
ii. For f>11, the open-loop gain rolls-off at a rate of- 20 dB/decade or

-6 dB/octave.
iv. At a particular input frequency 7 shown, the open-loop gainA is unity,
or gain in dB is zero. This is called the unity gain-bandwidth, small-
signal bandwidth and unity gain cross-over frequency.

Que 1.11. Draw and explain the simplified model of 741 Op-Amp.

Answer
1. Fig. 1.11.1 shows a simplified model of the 741 Op-Amp. The gain of 20d
assumed to be
stage is assumed sufficiently large. The output stage is

ideal unity-gain follower.

for the based

111.1A
Pigmodeling simple model 741 on

the second stage as an integrator

2. From the Fig. 1.11.1,

Als) = 8 ) G
As) Vc) sC
Thus, Ajo) = joC.
 1-18A (Ec-Sem-5) The 741 IC Op-Amp

3. At o= o, G = 1/5.26 mAN and C. = 30 pF

f =1 MHz
where,

4. This model is only valid at frequencies />>ladB

Que 1.12. Find out the overall gain of an Op-Amp Ic-741 giving its
cascaded equivalent cireuit derived for its three stages. Also derive
the relationship between f, and slew rate for IC-741.

AKTU 2019-20,Marks07
OR
Define the slew rate. Also derive the relationship between f, and

slew rate for the IC-741. ARTU 2015-16, Marka10

Answer
A Overall gain of an Op-Amp IC-741:
The overall voltage gain A, of the Op-Amp is the product of voltage
gains of each stage as given by,
A, = |A||A||A3|

where, A = Gain of differential amplifier stage

A = Gain of the second stage

A = Gain of the output stage
B. Slew rate: The slew rate is defined as the maximum rate of change of
output voltage per unit of time and is expressed in volts per
microsecond, i.e.,

SR= V/ us
at lmax

C. Relationship between f, and SR:

1. Consider a voltage follower shown in Fig. 1.12.1(a). The input is large
amplitude, high frequency sine wave.
2. , =
Vm sin ot
Then, output = Vmsin ot
3. Fig. 1.12. 1(b) shows the input-output waveform.
4. The rate of change of the output is given by,

du,
dt cos ot
Integrated Circuits 1-19A (EC-Sem-5)

(a) Voltage follower 6) Input/output waveform

Fig. 1.12.1
5. The maximum rate
otf change of the output occurs when cos ot = 1. That

is, SR =
dt l
6. Therefore, slew rate =
2nf Vm V/s

2nf
10V Vus

where, f= Input frequency (Hz)

m Peak output amplitude.
Que 1.13.|A 741 IC Op-Amp whose slew rate is 0.5 lus is used as an
inverting amplifier with a gain of 50. The voltage gain vs frequency
curve of 741 1IC is flat upto 20 KHz. What maximum
peak to peak
input signal can be applied without distorting the output ?

Answer

Given: Slew rate, SR =0.5 V/us, Gain

50,f=20
To Find: Maximum peak to peak input signal.
=
KHz

27f
1. We know, SR= V/as ..(1.13.1)
where is
10
V, peak value of output sine wave (V).
2. Putting all given values in eq. (1.13.1), we get,
2n (20x10*)v,
0.5=
10
0.5x 10
Vp 2n (20) = 3.98 V (undistorted)

3. Maximum peak to peak input signal that can be aplied without distorting
output is 2 x 3.98 = 7.96 V
 2UNIT
Linear Applications
of IC Op-Amp

CONTENTS
Part-1 Linear Applications of ... ***** 2-2Ato 2-9A
IC Op-Amps: Op-Amp
Based V-I and I-V
Converters, Instrumentation
Amplifier, Generalized
Impedance Converter, Simulation
of Inductors

Part-2 :Active Analog Filters :. **ssa . S A to 2-18A

Sallen KeySecond Order

Pilter, Designing of Second
Order Low and High Pass
Butterworth Filter

Part-3 Introduction to Bandpass.. 2-19A to 2-36A

and Band Stop Filter,
All Pass Active Filters, KHNN
Filters, Introduction to Design
of Higher Order Filters

2-1A (EC-Sem-5)
 Linear Applications of IC Op-Amps
2-2 A (EC-Sem-5)

PART 1] -V
Based V-I and
Linear Applications of IC Op-Amps: Op-Amp Generalized
Converters, Instrumentation Amplifier,
mpedance Coverter, Simulation of Inductors.

CONCE PT OUTLINE

The voltage to current converters accepts an input voltage V

and gives an output current

There a r e two circuits of V-I converter namely :

to current with floating load.

Voltage
Voltage to current with grounded load.
A current to voltage converter or ideal current controlled voltage
source, also called transresistance amplifier is the one, whose
k times the magnitude of
Output voltage is equal to a constant
an independent input currentl,
i. k1
Output voltage is independent of the load connected to it. The
constant k has the units of ohms.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 2.1.Draw V-I converter and derive its output equation for

floating load.

Answer
1 The Fig. 2.1.1 shows an arrangement of voltage to current converter
with load resistor R,. Here R is in floating condition i.e., not connected
to ground.
2. The input is applied to non-inverting end and the feedback voltage
across R, drives the inverting input end.

The feedback voltage across R, depends on the output current i, and it

is in series with the input difference voltage Vd:
4. Due to the concept of virtual ground, the voltage at node A will be V
Thus, VinR
i.e., an input voltage Vin 1s converted into an output current of

Vi R
Integrated Circuits 2-3 A (EC-Sem-5)

Fig. 2.1.1
Que 22. Draw and explain 1-V and V-I converters and derive its

output. AKTU 2018-19, Marks 07

Answer
A -V converter:
1. The current to voltage converter is shown in Fig. 2.2.1.
2. The open-loop gain A, of the Op-Amp is very large, so due to virtual
short concept,
- V2
V
3. As the input impedance of Op-Amp is very high,
B1B20

R
in W
in

oV-iRp

-EE

Fig. 2.2.1.Current to voltage convertor

4. Gain of inverting ampifier is given by

A,VR
V R
R Vin .(2.2.1)
 Linear Applications of IC Op-Amps
2-4 A (EC-Sem-5)

4. But V, V2
= and
V, = 0

V2 0

terminal is also at ground potential and entire input

5. Thus the inverting
voltage appears acroSs

in
Vin
R
(2.2.2)

6. Substituting eq. (2.2.2) in eq. (2.2.1), we get

V
R
..(2.2.3)
V.-R,Ain
The eq. (2.2.3) shows how this circuit converts input current into a

proportional voltage.
B. VIconverter: Refer Q. 2.1, Page 2-2A, Unit-2.

Derive the expression of output voltage for

Que 23
instrumentation amplifier.

Answer
1 The instrumentation amplifier shown in Fig. 2.3.1 has high input
impedance and a high gain.
The Op-Amps A, and Az as shown in Fig. 2.3.1 are voltage follower or
buffer circuits acting as the input stage for each of the input V, and V2
3. They have zero differential input voltage, i.e., Vd = 0. Under such
conditions with common mode signal = 0, and V, = V2 the voltage across

the resistor R is zero.

4. The voltages at the inverting terminals of the buffers are equal to the
input voltages. Since no current flows through the resistorsR and R',
the output voltages are V=V,and V=V, respoctively.

5. The current flowing in the resistor R is I = and the same

R
currentI will flow through the resistors R' in the direction as shown in
Fig. 2.3.1. The voltage at the non-inverting terminal of Op-Amp A, is

R+R
Integrated Circuits 2-5 A (EC-Sem-5)

6. By using superposition theorem, we get

7.
V-V1RRv
Simplitying, we get
..(2.3.1)

R W
W

W
R'

R2
V2
Fig. 2.3.1. Instrumentation amplifier
8. Since there is no current entering the Op-Amp, the current

I , which lows throught esistor R'.

V RI+V,-V-v)+V,
and
V RI+V, ,-V)+V,
9 Substituting the values Vj and Vin eq (2.3.1), then we get

V V, -V)+(V,-V
V, ,-V
10. By using a variable resistor R, the gain ofthis instrunmentation amplifier
can be varied.

Que 24. Describe the Antoniou inductance simulation cireuit

with properly labeled circuit diagram and give mathematical

expressions in eupport of your answer.AKTU2016-16, Marks10

Answer
1. Fig. 2.4.1 shows the Antoniou inductance simulation cireuit.
2-6 A (EC-Sem-5) Linear Applications of IC Op-Amps

L
R
W

inV,/
sCR,R,R/R2
Fig. 24.1
2. Applying KCL, we get

V-VV = 0
1/sC, R,

L
3. Apply KCL, we get

V,-V -o ...(2.4.1)
R
4. Substituting the value of V, in eq. (2.4.1)

R,V,-V+R,V,-R,",|1*C.R=0 .2.4.2)

5. Apply KCL, then we get

V,-VV-0 R,
R V-V,) +R,(V,-V,)=0
V R +R)-R,V, +R,V,
V, ,LR+R2v,
R
.2.4.3)
6. Now put the value of V, in eq. (2.4.2),

then,
C,RR)
Integrated Circuits 2-7 A (EC-Sem-5)
7. Current acrOss resistance
R,

- CR.
V,R_
8. Then input impedance
sC,R.R,R
C,R,R,R,
R
which is that of an inductance L given b,
L= GRRR,
R
9.
IfR, =Rz R^ = =
R, =R and C,=C
then, L= CR2

Que 2.5.Draw the generalized impedance converter and derive

its impedance equation. Also simulate an inductor.

AKTU 2017-18, Marks 05

AKTU 2019-20, Marks 07
Answer
A General Impedance Converter (GIC)
Generalized impedance converters (GICs) are Op-Amp circuits that
employ RC networks for simulating frequency-dependent impedance
elements such as inductors. Fig. 2.5.1 shows the circuit ofa GIC.
2. From Fig. 2.5.1, at node 1,

...(2.5.1)
where V Vcc and V2 = Vo1 Now, between nodes 2 and 4, we obtain
(using KCL)

Z Z, ..(2.5.2)
3 From the Fig. 2.5.2,we observe that nodes 1 and 3 are virtually shorted,
and hence using KCL

Vo-Vec Vcc -Vo2 ..(2.5.3)

4.
where
Rearranging eq.(2.5.3) yields
VoVA
(Z+ 2,) Vec= Vo2 Z2 +Vo1 .(2.5.4)
5. Now by using KCL between nodes 4 and 5, we have
 2-8 A (EC-Sem-5) Linear Applications of IC Op-Amps

(2.5.5)

02

Vo1
Virtual short

Virtual short2

Fig. 25.1. Generalized impedance converter

6. Substitution for Vs Vec and rearrangements give

Vg=or+2) ..(2.5.6)

7. Substituting for Vv2 from eq. (2.5.6) into eq. (2.5.4), we get

, +Z,) Voc = 5
z,+ V, Z, ..(2.5.7)

8. Rearranging eq. (2.5.7), we have

Vec,+- ,-V
CC
Z Zs
or, Z, Zs-Z,
Vcc22 La2 Vo1
= .(2.5.8)

9. Substituting for Vo1 from eq. (2.5.8) into (2.5.1) and simplifying, we
obtain
T,- Vec4-2,2,-Z,
Z, 2
Z,) ..(2.5.9)

10. Rearrangement of eq. (2.5.9) yields the input impedance of the circuit

Z- oc2Z,2
c
.(2.5.10)
ntegrated Circuits 2-9 A (EC-Sem-5)

11. Eq. (2.5.10) shows that the circuit shown in Fig. 2.5.1 can be used as
gTOunded impedance whose nature and value depends on the nature
and values of impedance elements to
Z, Zg
B. Simulation of Inductor: ReferQ. 2.4, Page 2-5A, Unit-2.

PART-2
Active Analog Filters: Sallen Key Second Order Filter,
Designing of Second Order Low and High pass Butteruworth Filter.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 2.6. Classify Active filters and write its advantages

Answer
A Classification of active filters:
to resistors and
1. Active filters employ transistors or Op-Amps in addition
capacitors.
range of the
2. The type of element used dictates the operating frequency
filter is shown in Fig. 2.6.1.
filter. classification
The of active
Active filters

All-pass filter
Low-pas8 i l t e r High-pass filter Band-pass filter Band-stop filter

Fig. 2.6.1
the active element and resistors
of these filters uses a n Op-Amp
as
3. Each
elements.
and capacitors as the passive

Gain,
Gain,
Ideal
Ideal
response response

Pass band
band Stop band Stop band
L
Frequency
Frequency b)
(a)
 2-10A (EC-Sem-5) Linear Applications of IC Op-Amps

Gain,
V
Gain.

Ideal Ideal
response respons

07top Pass Stop Pass Stop Pass

band band band .T0 band band band

requency Lc 'H requeney

C)
d)

Voltage

A
WW
e)

Fig. 2.6.2. Frequency response ofthe major active filters

(a) Low-pass ; b) High-pass ; (c) Band-pass ; (d) Band-reject:
Phase shift between input and output voltage of an all-pass filter
4 Fig. 2.6.2 shows frequency response characteristics of the five types of
filters. The ideal response is shown by dashed curves, while the solid
lines indicate the practical filter response.
B. Advantages of active filters
1 No loading problem: The Op-Amp provides a high input resistance
and low output resistance. Therefore active filters using Op-Amp do not
load the input source or load.
Flexibility in gain and frequency adjustment: In active filters, the
input signal is not attenuated while passing through filter and thus
provides flexibility in gain. In addition, the active filter is easy to tune,
therefore easy frequency adjustment is possible.
3. Small component size: Active filters use which
smaller n size.
components are

No insertion loss: The active filters do not exhibit any insertion loss.
5. Passband gain : These filters provide some pass band
gain.
Que 27. Compare active filters and passive filter.
 2-11A (EC-Sem-5)
Integrated Circuits

Answer

Active filter Passive filter

S.No. Passive tilters cannot cause
Active filters have a power
1. they cannot bring
gain i.e., c a n add energy into power gain, t.e.,
into the circuit.
energy
the circuit.
Passive filters do not require any
filters require an
Active
external power.
external power suPPIy.
Passive filters have no frequency
Active filters have frequency
limitation due to active limitations.

elements.
Passive filters are relatively
control
provides complex
It
than active filters.
system and thereforecheaper
expensive than passive
filters.

second order active

Write short note on Sallen Key
Que 28.
a

filter.

Answer order active filters

structure used for the second
1. Ageneral Sallen-Key
shown in the Fig. 2.8.1.
is
W ww-
R R

Vn
Y

Pig-28.1
is used in the non-inverting
amplifier mode hence we can

2. The Op-Amp
Wnte,
V.= Vp* [Gain)
=
V,A,

1+ for non-inverting mode

where A, =

Voltage at node B
and V =

elements to be connected in
and Y, are the admittances of the
Y, Y2, Yg
the circuit.
 2-12A (EC-Sem-5) Linear Applications of IC Op-Amps

Applying KCL at node A,

(in-VY-(-VY3-(V-Vg ¥2 =0
where, inCurrent entering at A (Vn-AY =

I3= Current through Y, leaving A = (Va- V,)Y3

l=Currentthrough Y leaving A = (Va-V)Y2

+Y2+Y3) +VpY2 +V,Ys, =0

Vn Y-VY,
4Now current entering at the Op-Ampterminals is zero hence current I,2
2.8.1)

flowing through Y, tlows through Y, also.

Va-V)Y= V,¥1
V= +Y V,(Y,+ Y ...(2.8.2)
AY
5. Substituting the values of Va and Vg in terms of V, in the eq. (2.8.1), we
get

V.Y- A,Y2
v+Y,+Y)Y,vY, =0
V.Y, -Vv++Y)Y-Y_Y.
:

A,Y -Y
:. V. Y, -VYY, +Y +¥Y:YY+YY+YY-Y-A,Y.Y,
A,Y
VY, =V,7,, +Y, Y, +}+Y)+YY,1-A, ))
A,
YY, +Y,¥,+Y, +Y)+ Y,Y, (1-4,)
6. This is the voltage gain of a general Sallen-Key structure used for
second order active filters.

Que 2.9 Write a short note on first order low-pass and

high-pass filter.

Annwer
A First order low-pass filter
1. Fig. 2.9.1 is an
active low-pass filter with single RC network connected
to the non-inverting terminal of Op-Amp.
2. The input
resistor
H,
the gain of the filter in the
and feedback resistor R, are used to determine
passband.
3. Referring to Pig8. 2.9.1, the voltage V across the
capacitor is
V, 1+j2 RC
4. The output voltage V, for non-inverting amplifier is
Integrated Circuits
2-13 A (EC-Sem-5)

,-
w-

-oVo

Fig. 2.9.1. First order low-pass filter with variable gain.

5. By substituting V, in the above equation, the output voltage V, becomes

v- T-J2/RC

where is the gain of the low-pass filter which is a function of

frequency,A = 1 + i j is the passband gain of the filter, / 27rkC

the high cut-off frequency of the filter.

6. The frequency response o f the filter can be determined by using the
magnitude of the gain of the low-pass filter, which is expressed as
A

B. First order high-pass filter :

1. The active high-pass filter with a single RC network connected to
non-inverting terminal of the Op-Amps shown in Fig. 2.9.2.
The input resistor R, and feedback resistor R, are used to determine
the gain of the filter in the pass- band.
3. The output voltage V, ofthe first order active high-filter is

1 } j 2 /RC
=
V.1 R)1+ j2n fRC
V,
4. Therefore, the gain of the filter becomes
 Linear Applications of IC Op-Amps
2-14 A (EC-Sem-5)

A .(2.9.1)

where pass-band gain of the filter is A = 1 + f i s the frequeney

R)
of the input signal and the lower cut-off frequency of the filter is

2TRC
R Voltage gain
ww-
-20 dB/decade

V0.707 A

Stop band; Pass band

(a) (b)
Fig. 2.9.2. (a) First order active high-pass filter with variable gain,
(b) Frequeney response of an active high-passfilter
The frequency response of the filter is obtained from the magnitude of
the filter

A
That is, |H)|= V

Que 2.10.Draw the circuit of second order low-pass filter and find
the expression for its cut-off frequeney.

Answer
The second order low-pass filter can be obtained simply by inserting an
additional RC network into the first order low pass filter.
2. RC2 is the additional RC network.

3. The frequency response is shown in Fig. 2.10.1(6). It shows that the

response in the stop-band rolls offat a rate of-40 dB/decade. This rate
is double the rate of the first order filter. That means second order
filters have a sharper frequency response.
The resistors R, and R, will decide the gain of the filter.
5. The cut-of frequeney f, is determined by R, C. Rg and C as follows:
Integrated Circuits 2-15A (EC-Sem-5)

1,2 R,R,CC3
R
w
R
R R3
Op-Amp

(a)
Voltage
Gain decreases at
gain
40 dB/decade
Ayr
0.707 AvF

Pass-band Stop-band

Frequency
Fig. 2.10.1.(a) Second order low-pass filter (b) Frequency response

Que 2.11. Classify active filter. Design second order low pass filter

with f=2KHz and passband gain of 3. ARTU 2018-19,Marks 07

Answer

A Active filter: Refer Q. 2.6, Page 2-9A, Unit-2.

B. Numerical:
Given: Gain = 3,fy=2kHz
To Design:Second order low-pass filter.
1. Let, C, C=0.0047F
Then, R =R3 27,C2m(2x 10*) (47x10
= 16.93 k2 = 17 ka

R,
2. Voltage gain, A R,
3-1+ R,
 Linear Applications of IC Op-Amps
2-16 A (EC-Sem-5)

R= 2R,
R, = 27 k
Assuming
2 27 5 4 k2
R= x

3. The required circuit shown in Fig. 2.11.1.

54 k
W wWw
27 k2

R2 R3 |741/35
w W
17 ka l7.k2
EE 10 k2
Vi Ca T C3
10.0047 jaF|0.0047 uF

Fig 211.1. 8econd order low-pass butterworth lter

Que 2.12. 2nd order Butterworth high-pass filter with
Design a

overall passband gain of 3 having corner frequency 2 KHz. Also

find and plot the frequency response at 100 Hz, 500 Hz, 1000 Hz,
1500 Hz, 2000 Hz, and 5000 Hz.

Answer

Given: Pass-band gain = 3,f =2 KHz

To Design: Second order Butterworth high-pass filter.

1. We know,
2 RR,C,C 2 R°C*
R = R= R, C = C, = Cand assunming, C = 0.01uF
Considering
R:
2 f2 x 2000 x 0.01 x
10
R 7.95 kn

2 Voltage gain, A 1
R
3 1+- R, 2R,
R
Choose R, = 10 Ka, R,= 20 Kan
Integrated Circuits 2-17A (EC-Sem-5)
3. To plot frequency response

1+ 2000

4 Table with in dB i.e., 20 log and frequency with frequency

in |in
response is shown in Fig. 2.12.1.
Table 2.12.1.

fin Hz
in in dB
100 42.4
500 14.5
1000 -2.76
1500 3.25
2000 6.532
5000 9.432

wwwT www
F
+Vcc
Vo
C2 3 Op-Amp 0.707

R2R
(a)

Voltage gain 40 dB/decade

Ay
A

stopband i Passband

Frequency
(b)
Fig. 2.12.1. (a) Second order high-pass butterworth filter,
(b) Frequeney response
 of IC Op-Amps
Linear Applications
2-18 A (EC-Sem-5)

filters.
and contrast active filters and passive
Que 2.13.| Compare Butterworth filter to have
cut-off
second order low-pass
Design a

frequency of 1 KHz.
AKTU 2017-18, Marks 05

Answer
Unit-2.
Comparison : Refer Q. 2.7, Page 2-10A,
Numerical:
1/2rRC
Given:fu =1 KHz =order low-pass Butterworth filter.
To Design: Second
1.6 K2.
Let C- 0.1 uF, gives the choice of R =

1.414. Then the passband gain,

2, the damping factor
=
a
2. For n =

A 3 - a=3-1.414 =1.586.
order loW-pass
the normalized second
3. The transfer function of
Butterworth filter is

1.586
s+1.414s, +1

Now, A, = 1+ 1.586 =1 +0.586

R
W
R R

w C
I

Fig. 2.13.1.Second order low-paas butterworth filter

5.86 KQ and 10 Ka. Then, we get A, 1.586.

R,
=

Rp
=

4. Let, =

with component values as

5. The circuit realized in the Fig. 2.13.1
R 1.6 KA, C 0.1 uF, Rp= 5.86 KQ and R, 100 Ka.
=
=

6. For minimum DC offset, 2R, which has not been taken into
R,|| Rp =

consideration here, otherwise, we would have to modity the values of R

and C accordingly which comes out to be R = 1.85 KQ, C = 0.086 pF,

5.86 KQ, R, = 10 Ka.

R =
Integrated Circuits 2-19 A (EC-Sem-5)

PART3
Introduction to Bandpass and Band Stop Filter, All
Pass Active Filters, KHN Filters, Introduction to
Design of Higher Order Filters.

Questions-Answers

Long Answer Type and Medium Answer Type Questions

Que 2.14. Explain bandpass filters and its types.

Answer
A Bandpass filter
1. Abandpass filter passes a particular band of frequencies and attenuates
any input frequency outside this pass-band.
2. This filter has a maximum gain at the resonant frequency G,), which

is defined as

3. The figure of merit or.quality factor Q, is given by

where B is bandwidth, f4 is higher cut-off frequency and f is lower

cut-off frequency.

B.
i
Types
Narrow bandpass filter:
1. The narrow bandpass filter using one inverting mode Op-Amp with
two feedback paths is shown in Pig. 2.14.Ka) and its frequeney response
is shown in Fig. 2.14.16).
2. The resonant frequency can be changed by adjusting R, without
changing the bandwidth or gain.
3. The bandwidth B is determined by resistor R and the two matched
capacitors C as given by

B= 0.1691
RC
where B =f,/Q.
The adjustable resistor R, is determined by
R
R, 20 - 1
 2-20 A (EC-Sem-5) Linear Applications of IC Op-Amps

5. Its resonant frequency f, is determined from

f 0.1125 R
I,RC R
Bandwidth
ZR

w - B
0.707 --**

R,:
0.1 L
0.1 01,
(a) )

Fig. 2.14.1. (a) Narrow bandpass filter circuit and

(b) Its frequeney response
ii. Wide bandpass filter:
1. A bandpass filter can be constructed simply by connecting low-pass
and filters in cascade as shown in Fig. 2.14.2(a).
high-pass
2. Here the low-pass circuit will pass all frequencies up to its cut-off
frequency fa while the high-pass circuit will block all frequencies
be at least
cut-off frequency L
its provided Iy>IL1e., lu must
below
10 times f
of the low and high-pass sections must have
3. The cut-off frequencies
the combination gives a filter with
the equal passband gain. Hence,
shown in Fig. 2.14.2(6).
passband from ; to fH as
Low-pass High-pass
response response
VV,L
Low-passHigh-pass

filter filter

(a)
and high-pass filters acting as
Fig. 2.14.2. (a) Cascaded low-pass filter.
bandpass
of the
filter (b) Frequency response bandpass
and
4. For realizing a :20 dB/decade bandpass filter, first
order high-pass
2.14.3(a). Its
first order low-pass sections are cascadedas
shown in Pig.
Fig. 2.14.3(6).
frequency response is shown in
Integrated Circuitss 2-21 A (EC-Sem-5)

First-order First-order
high-pass section low-pass section

R R
W W ww-w
V
(a)

Gain, +20 dB/decade

-20 dB/decade
0.707A

Stop Pass-bandStop band

band

H
6)
Fig. 2.14.3. (a) 20 dB/decade-wide bandpass filter and
(b) its frequency
response
Que2.15. Design a wide bandpass filter with lower cut-off
frequeney f 200 Hz, higher cut-off frequency fy = 1 KHz and a
pass-bend gain = 4.
AKTU 2016-17, Marks 10
Answer

Given:f= 200 KHr; fH 1 KHz; A=4

To Design : Wide bandpass filter.
A Components of the low-pass filter:
Let C 0.01 uF

2 2f,C 2x 1000x 0.01 x10

15.91 Kn

3 The gain of the low-pass filter can be considered half,

ALP 2

2-1+ R
Rg1 R, = 10 K2 (assume)
 Op-Amps
Linear Applications ofIC
2-22 A (EC-Sem-5)

filter
B. Components of the high-pass
1. Let CH= 0.05 uF

2f, C 2tx 200 x0.05 10

x

R4= 15.91 KO
section
low-pass
First order high-pass First order
K
section
W wW
RH +Vcc
WW W-
cc
L Op-Amp
Amp>

-VEE
R

Fig. 2.15.1

3. The gain = 2

1+ H=2

10 K2 (assume)
RH=Ry =

4. Quality factor, Q.
200x 1000
=0.56
800

500 Hz and
Design a wide bandpass filter with f
=

Que 2.16
draw frequency response of the
u 1500 Hz and passband gain of 5,
filter and find value ofQ. AKTU 2018-19, Marks 10
Answer
Given:f 500 Hz; fy= 1500 Hz; A = 5

To Find:Q.
A. Components of the low-pass filter :

1 Let C= 0.01 uP

= 10.6 KO
"L2,C; 2t x1500'x 0.01 x10
 Integrated Circuits
2-23 A (EC-Sem-5)
3. The gain of the
low-pass filter can be considered half,
ALP= 2.5

2.5 1
RFz = 1.5 Rz
Let we choose R, 10 KQ
FL 15 Ka
B.
Components of the high-pass filter:
F i r s t order high-pass
section
-First order low-pass' section
FL
RH KFH w WW
www W
+Vcc

Ca
Op-Amp
Op-Amp Vo
VEE

(a) Wide bandpass filter.

Gain

+20 dB/decade
AVp5 -20 dB/decade
0.707 Ap

Stopi
band -Passband band
P

500 Hz fu= 1500 Hz Frequency

(6) Frequency response of a bandpass filter
Fig. 2.16.1.
1. Let C 0.05 u

2. 1
R "2nf,CH 27 x 500 x 0.05x 10
R= 6.37 KO
3. The gain = 2.5

1+ 2.5

R 1.5 Ru
Let we choose
1 0 Kn
FL 16 KQ
2-24 A (EC-Sem-5) Linear Applications of IC Op-Amps

4 Quality factor, - f y6o010001500 0.866

f f-f
Que 2.17.Write a short note on band-reject filters.
OR
Draw and explain narrow band-reject filter. Also, find its transfer

function. AKTU 2019-20, Marks 07

Answer
A Band-reject filter:
Band-reject filter, also called as the band-elimination or band-stop
filter, attenuates the frequencies in the stopband and passes them
outside this band.
B. Types:
Narrow band-reject filter:
The narrow band-reject filter, often called the notch filter, is the twin T
network cascaded with the voltage follower as shown in Fig. 2.17.1la).

L
R/2 2C
RS

Ra

(a) Circuit of a narrow band-reject (notch) filter

Gain.t Bandwidth
A= 1
0.707

(b) Its frequency response.

2.
P2.17.1
Applying Kirchhoff's current law at node Va we get
(V-VC (V.-VC+(KV,-V.) 2G = 0
sCVaC +2KC) V, = «C + G) V. ..(2.17.1)
Integrated Circuits 2-25 A (EC-Sem-5)

where Rand G-
R +R)
3. Applying Kirchhoff current law at node Va» v ge
V-V,)G+(V.-V,G +2KV, -V,) sC = 0
GV+(G+ 2 KsC) V, = 2(G + sC) V
.(2.17.2)
At node V
(V-V,) sC+ (V%-V,) G=0
sCV+GV, = (G + sC) V.
..(2.117.3)
4. From the above three node
voltage eq. (2.17.1), (2.17.2) and (2.17.3),
the transfer function can be written as

V,(s) G+s C
HS) Vs)G +Sc +4(1-K)sCG

C
3+C +4(1- K)s
5. In the steady-state, that is s =
jo,

Hyo)=
o - j4 (1- K) a0,
where

6. At 3 dB cut-off
CRC °r ,2nRC
frequency,

7.
Therefore, o- o,'= :4(l-K) o0,
C+41K
D
1=0
8. Upon solving the above quadratic equation, we obtain the upper and
lower half power frequencies as,

f1+4(1-K + 21- K)
and f.y1+4(1- K* -2(1 - K
The 3 dB bandwidth is
B
fa-f=4 (l-K f,
Q 41-K)
ii. Wide band-reject filter:
1 Fig. 2. 17.2a) shows a wide band-reject filter that is obtained by
paralleling a high-pass filter with a cut-off frequency of f with a
low-pass 1ilter.
 2-26 A (EC-Sem-5) Linear Applications of IC Op-Amps

A V,

ww

(a) Circuit of a wide band-reject filter

ass-bandRejectPass-band
band
A
3 dB

(6) Its frequency response

Fig. 2.17.2.
With cut-off frequency of fp. provided f> f and a summing amplifier
connected in series to add the filtered individual passband components.
The passband gains of both the high-pass and low-pass sections must
be equal.
The frequency response characteristic of the wide band-reject filter is
shown in Fig. 2.17.2 (6).

Que 2.18 Discuss all-pass filter in brief.

Answer
An al-pass flter passes all frequeney components of the input signal
without attenuation, while providing predictable phase shifts for different
frequencies of the input signal.
When signals are transmitted over transmission lines, such as telephone
wires, they undergo change in phase. To compensate for these phase
changes, all-pass filters are required.
3. The all-pass filters are also callod delay equalizers or phase correctors.
4. Fig. 2.18.1(a) shows an all-pass filter wherein R,=R.
Integrated Circuits 2-27 A (EC-Sem-5)

5. The output voltage v, of the filter can be obtained by using the

superposition theorem,

.(2.18.1)

7. But - j = 1/j and Xc = 1/21fC. Therefore, substituting for X¢ and

simplifying, we get

2
j2r/RC +1)
or 1-j2nfRC (2.118.2)
Un 1+ j2rfRC
where fis the frequency of the input signal in hertz.

Rp= R

Vcc

o
in
R
R

(a)

Voltage

Phase angle (deg)

90|180°270° /360° 450 540"

190° (b)
Fig. 2.18..
8. Eq. (2.18.2) indicates that the amplitude of v,/ v is unity: that is,
e,l = l n throughout the useful frequency range, and the phase
shift between v, and vin is a function of input frequency /.
9 T h e phase angle o is given by,

2 tan Zn/RC .1218.3)

 Linear Applications of IC Op-Amps
2-28 A (EC-Sem-5)

where in
degrees, finhertz, R in ohms, and C in farads.
10. Eq. (2.18.3) is used to find the phase angle o iff, R and C are known.

11. Figure 2.18.1(b) shows a phase shift of 90° between the input vip and
of R and C, the
output v,: That is, v, lags vn by 90°. For fixed values
from 0 to- 180° the frequency fis varied from
phase angle ¢ changes as

0 to a

12. In Fig. 2.18.1(b), if the positions of R and C are interchanged, the phase
That is, output v, leads
shift between input and output becomes positive.
input bin
Que 2.19. Draw the circuit of KHIN filter and derive the expression

for its voltage gain. AKTU 2016-17, Marks 10

OR
Derived the expression of voltage gain in KHN Biquad filter. Draw
the KHN Biquad filter and derive transfer function of the BPF and

LPF from that.

AKTU 2017.-18,Marks10
AKTU 2019-20,Marks07
Answer
1. The second order high-pass transfer function is

Ks hp (2.19.1)
s +8

where K in high frequency gain

2. Simplify eq. (2.19.1) and we get,

(2.19.2)

3. The signal ( o ) Vhp can be obtained by passing Va» through an

integrator with time constant equal to
l/0
Passing resulting signal through another identical integrator results
in the third signal involving Vhp in eq. (2.19.2) and rearranging
eq. (2.19.2), we get

5.
VV ,-,
Biquad means the circuit is capable of realizing a biquadratic transter
(2.19.3)

function.

6. Eq.(2.19.3) can be transfer to block diagram as shown in Fig. 2.19.1

 2-29 A (EC-Sem-5)
Integrated Circuits

1
,
Vhp
R

hp hbp
Fig. 2.19.1
for first
The output of second integrator
is labeled as
Vi while
Vb
7.
integrator.
function is given by
8. Bandpass filter transfer

19.4)
Tap V,
Kos .(2.19
19.5)
9. Using eq. (2.19.1),1 bp slo, /)+o
by (using eq. (2.19.1))
10. Low-pass filter transfer function is given

Ko ...(2.19.6)
1p v +sto, /Q)+o,
2.19.2, we replace each integrator with
11. To obtain Op-Amp circuit in Fig. block
CR = 1/o, also replace
summer

Miller integrator circuit having

with Op-Amp summing circuit.
K e r w i n - H u e l s m a n - N e w c o m b or KHN
The resulting circuit is known
as
12.
2.19.2.
biquad as shown in Fig.
R.

Re

V,wW

bp

Pie 2192. KHN bguad filo

R of integrator so CR l/o. For resistors,
=

13. Select suitable values of C and in terms of

we use superposition
to express the output of summer Vh

its inputs,

, dV,-
2-30 A (EC-Sem-6) Linear Applications of IC Op-Amps

..(2.19.7)

14. Equating the last RHS term of eq. (2.19.3) and(2.19.7) gives
R,
R
15. Now equating second to last terms on RHS of eq. (2.19.3) and (2.19.4)
and let R,=R,

R
2-1
16. Finally equating coefficients of V in eq. (2.19.3) and (2.19.7) and
substituting R,=R, and RJR3

Then, K= 2 - 1 )

17. The KHN biquad can be used to realize notch and all-pass functions by
summing weighted versions of the three outputs LP, BP, and HP. Such
an Op-Amp summer is shown in Fig. 2.19.3.
18. From Fig. 2.19.3, we can write

V-V R ..(2.19.8)

hp WW Rp
H W

V1p W-
Fig. 2.19.3. Notch and all pass filter using KHN flter.
19. Substituting for Thp Tbps and T1, from eq. (2.19.1), (2.19.5) and (2.19.6)
give the overall transfer function

-K B/R,)s*-stR, / R,)0, +(R,/R,\oj

+s0/Q)+ o
20. To obtain noteh function by selecting Rg = o
Integrated Circuits 2-31 A (EC-Sem-5)

Que 2.20.Describe the circuit for the KHN filter using three
Op-Amp. Design a second order Butterworth low-pass filter having
upper cut-off frequency1 KHz. Determine its frequeney response.

AKTU 2016-16, Marks 15

Answer
A KHN Alter: Refer Q. 2.19, Page 2-28A, Unit-2.
B. Numerical : Refer Q 2.13, Page, 2-18A, Unit-2.
C. Frequency response :
1 The gain of second order low-pass Butterworth filter is given by
1.586
Tyo)= 4

Tgo)lB 20 log 1.586

Input frequency (Hz) 1Tgo)|dB

4.34

100 4.005

1000 0.99=

2000 8.298

2. Frequency response is shown in Fig. 2.20.1.

ITjo) in dB

1
dB
- 8.29 d

fHz)
fo- 1KHz 2KHz

Fi. 2.20.1.

Que 2.21. Write a short note on higher-order filter.

 Linear Applications of IC Op-Amps
2-32 A (EC-Sem-5)

Answer
at the rate of
1. In the stopband the gain of the filter changes
/ decade for first-order filters and at
40 dB/decade for second-
20
dB
order filters. This means that, as the order of the filter i8 increased, the

stopband response of the filter approaches its ideal stopband

actual
characteristic.
First order low-pass Second order low-pass
section section
R, Rp
www ww
A2

R EC
L

Fig. 2.21.1
2. Higher-order filters, such as third, fourth, fifth, and so on, are formed
simply by using the first and second-order filters.

Second order low-pass Second order low-pass

section section

*cc Vo
EE

PiR. 2.21.2
For example, a third-order low-pass filter is formed by connecting in
series or cascading first-and second-order low-pass filters; a
fourth-order low-pass 1ilter is composed of two cascaded second-order
low-pass sections, and so on.
Integrated Circuits 2-33 A (EC-Sem-5)

3. Although there is no limit to the order filter that

of the
the order of the filter increases, so does its size.
can be formed, as

Also, its accuracy declines, in that the difference between the actual
stopband response and the theoretical stopband response increases with
an increase in the order of the filter.

5. Fig. 2.21.1 shows third and fourth-order low-pass Butterworth filters.

In the third-order filter the voltage gain of the first-order section is one
and that of the second-order section is two.
6. In the fourth-order the gain of the first section is 1.152 while that of the
second section is 2.235. These gain values are necessary to guarantee
Butterworth response and must remain the same regardless of the
filter's cut-off frequency
7. Furthermore, the overall gain of the filter is equal to the product of the
individual voltage gains of the tilter sections.
Thus the overall gain of the third-order filters is 2.0, and that of the
fourth order filters is (1.152) (2.235) = 2.57.

Que 2.22.| Derive the output expression for RC phase shift

oscillator. AKTU 2017-18, Marks 05

Answer
1 The circuit of an RC phase shift oscillator is shown in Fig. 2.22.1. The
Op-Amp is used in the inverting mode and therefore provides 180
phase shift. The additional phase of 180° is provided by the RC feedback
network to obtain a total phase shift of 360°.
The feedback network consists of three identical RC stages, Each of the
RC stage provides a 60" phase shift so that the total phase shift due to
feedback network is 180".

3. The feedback factor p of the RC network can be ealeulated by writing

the KVLequations from Fig. 2.22.2.

2.22.1)

-1,R+1|2R 1=0 ..(2.22.2)

2R
1 6 ..(2.22.3)
0-1,R +1 =

anu
 Linear Applications of IC Op-Amps
2-34A (Ec-Sem-5)

R Amplifier
ww
R
wwww
Vo

COmp

- -

R
Feedback
network

Fig. 2.22.1. Phase shift oscillator

network:
Fig. 2.22.2. Caleulating Bfrom phase shift

4. Solving eq. (2.22.1), (2.22.2) and (2.22.3) for 1, we get

V,Rs'C
3 1+5sRC+6s'C R* +s'C'R
.1
V,R's'C"
and
1+ 5sRC +6s c'R+s'C°R

1+
sRC sCR s'C'R'
8 = Jo, 8 - o * and s' =-jo", we get
5. Replacing
6 1
1+
joRC o'R'C* jo'*'C
(2.22.4)
(1-5ca )+ jal6 -

a)
Integrated Circuits 2-35 A (Ec-Sem-5)

1
where,
coRC
6. For Aß =1, B should be real, that is the
must be zero, thus
imaginary term in eq. (2.22.4)

a6-a)= 0
a6
a V6
That is, = 6
oRC
7. The expression for frequency of oscillation, f,, is therefore given by

f.
2TRC6
8. Putting a' = 6in eq. (2.23.4), we get

29
The negative sign indicates that the feedback network produces a phase
shift of 180°.

9. So,
IP 29
Since AßI 21
Therefore, for sustained oscillations,
29
10. The gain A, is kept greater than 29 to ensure that variations in circuit
parameters will not make |A,B| <1, otherwise oscillations will die out.

VERY IMPORTANT QUESTIONS

-

Following questions are very important. These questions

may be asked in your SESSIONALS as well as
UNIVERSITY EXAMINATION.

1 . Draw and explain 1-V and VI converters and derive its

output.
Ans Refer Q. 2.2.

Q.2. Describe the Antoniou inductance simulation cireuit with

properly labeled circuit diagram and give mnthematical
expressions in support of your answer.
Ans Refer Q. 2.4.
 3
UNIT
Compensation and
Frequency
Non-Linearity

CONTENTS
Part-1 Frequency .3-2A to 3-13A
Compensation, .
Compensation of Two Stage
****
****

Op-Amps, Slewing in Two Stage

Op-Amp. Non-linearity of
Differential Circuits, Effect of
Negative Feedback on
Non-linearity

Part-2 Non-linear Applications of . 13A to 3-23A

IC Op-Amps Basie Log-Antilog
Amplifiers using Diode and
BJT Temperature Compensated
Log-Antilog Amplifier using Diode,
Peak Detector, Sample and
Hold Circuits

Part-3 : Op-Amp as a Comparator and . -23A to 3-42A

Zero Crossing Detector, Astable

Multivibrator and Monostable
Multivibrator, Generation of
Triangular Waveforms, Analog
Multipliers and Their Applications

3-1A(EC-Sem-6)
 & Non-Linearity
3-2 A (EC-Sem-5) Frequency Compensation

PART 1
Frequency Compensation, Compensation of Two Stage Op-Amps,
Slewing in Two Stage Op-Amp, Non-linearity of Differential
Non-linearity.
Circuits, Effect of Negative Feedback on

CONCEPT OUTLINE

are
T h e two types of compensation techniques
used in practice
i. External frequency compensation
ii. Internal frequency compensation.

Questions-Answers

Answer Type Questions

Long Answer Type and Medium

compensation ? Explain
Que 3.1.What are types of frequeney
any one.

Answer

Types of Frequency compensation:

Internal frequency compensation.

ii External frequency compensation:

to the Op-Amp for
The compensating network is connected externally
modifying the response suiting the requirements.
the response so that 20 dB/decade
The compensating network alters
-

2.
a broad range of frequency.
of roll-off rate is achieved over
methods
The commonly used external compensation
are

Pole-Zero (lag) compensation

Miller effect compensation
c Dominant-Pole compensation:
1. Assume A is the uncompensated transfer function of an open-loop

Op-Amp, whose transfer function is given by

A= A,0,0,0 ..(3.1.1)
(s +a)6 +0
<
where 0 <
o <
®2 O3
Integrated Circuits 3-3A (EC-Sem-5)
2. Figure 3.1.1(a) shows a dominant-pole compensation network by adding
an RC network in
series with an Op-Amp, it can be achieved by
or

connecting capacitor
a C at a suitable high resistance node with respect
to ground

io

(a) Dominant-pole compensation

No compensation
20 dB/decade

- 40 dB/decade

Dominant
pole -60 dB/decade
Compensation flog scale)
2 3
(b) Gain Vs frequency characteristics for dominant pole
compensation.
Fig. 3.1.1
3. Then, the compensated transfer function A" after
compensation is given
Dy

JJoC
A' AR A
1ifIf)
JO
wheref= V2rhC is the break frequency of the compensating network.
Using eq. (3.1.1), we get the compensated transfer function as

A'= 7

where f h <2<l
5. The capacitance C is selected such that, the modified loop gain drops
down to 0 dB with a roll-off rate as given by 20 dB/decade at a frequency,
where the poles of the uncompensated system transfer funetion A
contributes negligible phase shift.
6 Nornally, the break frequeneyfa=a /2t isseleetedso that, the transfer
function A' passes through OdB at the pole f, of A. The uncompensated
and compensated magnitude plots are shown in Fig. (3.1.1(b).

Que 32. Explain pole-zero compensation method.

 & Non-Linearity
3-4A (EC-Sem-5) Frequency Compensation

Answer
added to the uncompensated
1. In this method, both pole and zero a r e

transfer function A.
of the pole-zero
2. Figure 3.2.1(a) shows the circuit arrangement than the
method. The zero is added at a higher frequency
compensation
pole.
= R
W

TC2

(a) Pole-zero compensation

No compensation
20 dB/decade

Pole-zer
com pensation
40 dB/decade

20dB/decade

60 dB/decade
0 dB
T2 3 log scale)
(a) Its open-loop Vs trequency response

Fig. 3.2.1.

3. The transfer function of the compensation network is given by,

R
Z,Z R, +

R,+X
where, 2 =R,and
Z R,c
JoC

1+
joR,C,_
1+jo R, +R,*2 1

where,
2rR,C, ana
Integrated Circuits 3-5 A (EC-Sem-5)

1
2rt R+R,C,
4. The compensating network introduces a zero at the first corner
Irequency I of uncompensated transfer function represented by A,
which cancels the etfect of
pole at /
5. The pole of the
compensation
network at given as
lo 2t
1s selected
such that the compensated transfer function A' passes through 0 dB at
the second corner
frequencyf2. This is shown in Fig. 3.2.1(b) graphically
by having A' passing through 0 dB at frequency f2 with a slope of
-20 dB/decade.
6. The overall transfer function of the amplifier with compensation network
is given by

A' = _

Therefore, A'

where 0fo <f </

Que 3.3. Discuss Miller effect compensation method in brief.

Answer
1. Figure 3.3.1(a) shows the Op-Amp inverting amplifier with capacitor C
connected in parallel with the feedback resistor Ra.

W-

R
WW

(a) Inverting amplitier with (b) Phase lead network of the

miller capacitor. compensated Op-Amp

2. The combination of C, and R, behaves as phase-lead network in the

feedback of Op-Amp as shown in Fig. 3.3.1(b).
loop
 & Non-Linearity
3-6 A (EC-Sem-5) Frequency Compensation

3. Thus, C, andR, introduce a phase lead to cancel some amount of phase

lag in the loop.

Que 3.4.Write a short note on internal frequency compensation.

Answer
in
Broad bandwidth may not be the only criterion required
some
1.
applications like instrumentation. In such cases, internally compensated
be employed. They a r e tound
Op-Amps called compensated Op-Amps can
to be stable regardless of the value of closed-loop gain and without any

external compensation methods.

The frequency response of uA741 Op-Amp which is internally

compensated is reproduced in Fig. 3.4.1.

A| in dB)

Ao 00 3 dB

80+
20 dB/decade

-6 dB/octave
40

20
fiHz)
10 10 10 10 10 10 10
T

Fig 341 unity

of 30 pF that shunts
3. TheOp-Amp 741 internally contains a capacitance
to decrease in
OFF the signal current at higher frequencies, leading
output signal.
the open-loop gain to
This internal compensating capacitor causes
dB/decade rate that assures a stable characteristic for the
roll-off at-20
circuit.
of1 MHz. This
5. The Op-Amp 741 has a gain-bandwidth (GBW) product
at any point on the
represents that the product of gain and frequency
Vs frequency curve is 1 MHz.
open loop gain
6. Ifthe Op-Amp is connected for a gain dB, or 10", then the bandwidth
of 60
obtainable is 1 KHz. For a gain of 10, the bandwidth increases to

100 KHz.
Que 3.5.Explain Miller compensation of two stage Op-Amp.
Integrated Circuits 3-7 A (EC-Sem-5)

Answer
1. In Fig. 3.5.1(a), the first stage exhibits high output impedance and the
second stage provides a moderate gain, thereby providing a suitable
environment for Miller multiplication of capacitors.
2. As shown in Fig. 3.5.16), the idea is to create a large capacitance at node
E, equal to (1 A , , ) Ce moving the corresponding pole to

R C + 1 +A,)C, where Cg denotes the capacitance at node E

before C is added.
3. As a result, a low frequency pole can be established with a moderate
capacitor value, saving considerable chip area. This technique is called
"Miller compensation".

Av

"outi
a (b)
Fig. 3.6.1. Miller compensationof a two-stage Op-Amp.
4 In to
addition lowering the required capacitor value, Miller compensation
entails a very important property:it moves the output pole away from
the origin.

ue 36.Write a short note on slewingin two stage Op-Amp.

Answer
1. In Fig. 3.6.1(a) Vin experiences a Jarge positive step at t = 0, turning OFF
Ma, M, and M
2. The circuit can be simplified to that in Fig. 3.6.14b), revealing that Ccis
charged bya constant current Iss if parasitic capacitances at node X are
negligible.

Recognizing that the gain of the output stage makes node X a virtual
ground, we write: Vou3sc
Thus, the positive slew rate equals Iss/Cc. During slewing, Mg must
provide two currents:gs and
5. IfM, is not wide enough to sustain Iss+ in saturation, then Vy drops
significantly, possibly driving M, into the triode region.
6. For the negative slew rate, we simplify the circuit as shown in
Fig. 3.6.1c). Here I, must support both ss nd ps For example, if
I =lss, then Vy rises Bo as to turn OFF M,. If, <lgs, then M, enters the
triode region and the slew rate is given by psc
 3-8 A (EC-Sem-5) Frequeney Compensation & Non-Linearity

Vout

V pD

M
Vin M M out

Iss
(a) Simple two-stage Op-Amp
DD pD

lss 5
Cc
M L

SS

(b) Simplified circuit during (c) Simplified cireuit during

positive slewing negative slewing
Fig. 3.8.1

Que 3.7 The input/output characteristic of a differential

amplifier is approximated as y ) = u,rlt) + aS(t). Caleulate the
maximum non-linearity if the input range is from to
-

* xax

Ymax

ma
+mAX

|-Ymax
8.7.1
Integrated Cireuits 3-9A (EC-Sem-5)

Answer

1. The
polynomial equationis
y t ) = a,r(t) + a r ( t ) + agr°(t) + (3.7.1)
2 As shown in Fig. 3.7.1, we can express the straight line passing through
the end points as

=
d,Ax mas x
max

3. The difference between y andy, is therefore equal to

Ay = " - g *max
Taking derivative with respect to x then we get

1x -a3* max

5. Putting
d Ay 0 then
=
we get,

*= *maxN3
6. The maximum deviation is equal to 2a, (33). Normalized to the
maximum output, the non-linearity is obtained as

3V3 *
24as
2a,max
na a mas
7. The maximum peak-to-peak output swing is equal to %a,*as+a,ma

For small non-linearities, neglect a,x with respect to

we can
ama
arriving at

mas 3,/3a,
8. The relative non-linearity is proportional to the square of the maximum
input.
9. The non-linearity of a cireuit can also be characterized by applying a
sinusoid at the input and measuring the harmonic content of the output.
10. If xt) =A cos ot, then eq. (3.7.1) becomes,
yt) = 1 A cos øt + A * cos- (øt + a cos" ot **

,Acos ot+ |11+ cos(2ot) + 3 cos ot + cos(3»t) +

 3-10 A (EC-Sem-5)
Frequency Compensation & Non-Linearity
11. We observe that higher-order terms
yield higher harmonics. In particular,
even-order terms and odd-order terms result in even and odd harmonics,
respectively. The magnitude of the n" harmonic grows roughiy in
proportion to the n power of the input amplitude.

Que 38. Write a short note on non-linearity of differential

circuits.

Answer
1. Differential circuits exhibit an "odd-symmetric"
input/output
characteristic, i.e., f(-x)= -fx). And the polynomial equation is
ylt) = a,xlt)+ a 0 ) + a r 0 ) t..
3.8.1)
2. For the polynwmial of eq.(3.8.1) to be an odd function, all of the even-
order terms, must be zero :

yt) = a,x{t) + a , r t ) + a g ) +..

3.
...3.8.2)
Eq.(3.8.2) indicating that a differential circuit driven by a differential
signal produces no even harmonics. This is another very important
property of differential operation.

V pD

VpD
Rp
R W/L Vout WL
Mo
Vin M2 L
V
W/L

Iss 21

Fig. 3.8.1.
Single ended and
differential amplifiers
providing the same voltage gain.

4. In order to appreciate the reduction of non-linearity obtained by

differential operation, let us consider the two amplifiers shown in
Fig. 3.8.1, each of which is designed to provide a
ot
small-signal voltage
gain

.3.8.3)

4,C (Va-V R, ..(3.8.4)

5 Suppose a signal V, cos (t is applied to each circuit. Examining
drain currents for simplicity, we can write for the
only the
common-source stage:
Integrated Cireuits 3-11A (EC-Sem-5)

CVas-Vra +V., coscot

W
u.CVas-Vru,C(oVu)V,cosat
cos o

W
I+p,C Vas-V, cosof C..VI1+cos(20)
.(3.8.5)
6. Thus, the amplitude of the second harmonic, AD2 normalized to that of
the fundamental, A, 1S

HD2 m .(3.8.6)
40Vas-V)
7. On the other hand, for M, and M, in Fig. 3.8.1, we have

4lssV .(3.8.7)

CV. y41V-V-V (3.8.8)

8. If |Vinl<« Vas-V then

V
Ip-pa = H,C.Va- Vru4Vas-V ..3.8.9)

...(3.8.10)

V cos cof
=

H,C.Vas-Vu. costf 8(Vs -V ...(3.8.11)

Since ot 13 wt + cos(3ot)}/4, we obtain

9. cos = cos

VmCos(3ot) ...(3.8.110)
p-In, 32Vs-VCOsO 8 32(1Vs-V
then
10. If V» 3V,/18Vas- Vru1,
V 3.8.11)
A, 32Vas-Vru
(3.8.9) indicates that the differential
11. Comparison of eq. (3.8.8) and eq.
circuit exhibits much less distortion than its single-ended counterpart
while providing the same voltage gain and output swing.
 & Non-Linearity
3-12A (EC-Sem-5) Frequency Compensation

and eq. (3.8.11) yield a

For example, if V, 0.2(Vas- VTH), eq. (3.8.10)

=

distortion of 5% and 0. 125 %, respectively.

non-linearity ?
Que 3.9. What is the effect of negative feedback on

Answer
1. We obeerved that negative feedback makes the closed-loop gain relatively
independent of the Op-Amp's open-loop gain.
2. Since non-linearity can be viewed as variation of the small-signal gain
feedback supPpresses this
with the input level, we expect that negative
variation as well, yielding higher linearity for the closed-loop system.

xt)o ax + a2x 1

Fig. 3.9.1. Feedback system incorporating

a
non-linear feedtorward amplifier
3. Let us assume that the core amplifier in the system of Fig. 3.9.1 has an

input-output characteristicy =at+ ax.

We apply a sinusoidal input z(t)= Vm cos ot, postulating that the output
and a second harmonic and hence
Contains a
rundamental component
can be approximated as y a cos øt +b cos 2»t.
5. The output of the subtractor can be written as,
y, z t ) -By(¬) ..(3.9.1)
2ot) ..(3.9.2)
mCOS ot - pla cOs o t +
b cos
(V-Ba) cos wt- Bb cos 2ot . (3.9.3)
6. This signal experiences the non-linearity of the feed forward amplifier,
thereby producing an output given by
y) = G1 ) cos ot - pb cos 2»t|

+a(m ßa) cos ot-Bb cos 2ot]

-
.3.9.4)
= la,(V»-Ba) - a,V-Ba)pb] cos ot

Bh+2npacos 2ot t (3.9.5)

-
7. The coefficients of cos ot and cos 20ot in eq. (3.9.5) must be equal to a and
b, respectively :
a =
(a-pb) (,m-pa) ..(3.9.6)
= - a,Bb + 2 Ba)? ...(3.9.7)

8. The assumption of small non-linearity implies that both az and b are

small quantities, yielding a = a,(Vm-Ba) and hence

a 1+ pa,
.(3.9.8)
Integrated Circuits 3-13 A (EC-Sem-5)

which is to be expected because Ba, is the loop gain. To caleulate b, we

Write

Vm-Ba= (3.9.9)
thus expressing (3.9.7) as

b= - a,ßb+ 7
That is

2a (1+pa,
1
It follows that
2 1 Ba,
9. For a meaningful comparison, we normalize the amplitude of the second
harmonic to that of the fundamental:

b,11
a 2 a, (1+ Ba,
10. Without feedback, on the other hand, such a ratio would be equal to
(a,V/2/a,Vm =a,V2a). Thus, the relative magnitude of the second
factor (1
harmonic has dropped by a
of +
Ba,)
11. Negative feedback therefore reduces the relative second harmonic by a
factor of (1 +ßa, and the gain by1+ Ba.

PART-2
Non-linear Applications of IC Op-Amps: Basic Log-Antilog
Amplifiers using Diode and BJT, Temperuture Compensated
Log-Antilog Amplifier using Diode, Peak Detector,
Sample and Hold Circuits.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

short note logarithmie amplifier with its

Que 8.10. Write a on

mathematical expression.
 & Non-Linearity
3-14A (EC-Sem-5) Frequency Compensation

Answer
1. Afundamental log amplifier is formed by placing a transistor in negative
3.10.1.
feedback path of Op-Amp as shown in Fig.

W
in

Fig. 3.10.1.
2. The node B is at virtual ground hence V = 0. The current through

resistorR can be written aS

I= inB _
"n ..(3.10.1)
R R

...(3.10.2)
I=l, =l=
3. At the Op-Amp input currentis zero
I = I, = Collector current .3.10.3)
4. The voltage VCB = 0 as the collector is at virtual ground and base is
of
grounded. Hence, we can wTite the equation 1 as,

= s , (eVer/V ..(3.10.4)
5. Take natural log on both sides of eq. (3.10.4

'V Iin ...(3.10.5)

6. Substitute the eq. (3.10.2) in eq. (3.10.5), we get

..(3.10.6)
UREF
-1,R and the output is
where same as
VB
BE

"-V In .3.10.7)

REF
Que 3.11. Draw the circuit for anti-log amplifier and derive the
expression.

Answer
1. Fig. 3.11.1, shows the anti-log amplifier using transistor,
Integrated Circuits 3-15 A (EC-Sem-5)

Virtual ground
w
in V
BE c B

Fig. 3.11.1. Basic Anti-log amplifier circuit.

The node B is at a virtual ground hence V, =0. Thus both collector and
base of the transistor are at ground potential and VoR = 0. Hence the
voltage across the transistor is Va and can be written as

.(3.11.1)
3. From Fig. 3.11.1, VBE=n
3.11.2)
Now the current c and currentI are same as Op-Amp input current is
zero,

...3.11.3)

5. Substitute eq. (3.11.3) in eq. (3.11.2) we get,

o VT
Is e'n
-Is R, eu/7 .3.11.4)
6. Assume I, R, = v,We can write the equation,

-ref en
1. Thus the output voltage v, is proportional to the exponential of u, ie.,
anti-log ofv, Thus the circuit works as basic anti-log amplifier.

Que 3.12. Describe temperature compensated log amplifier using

two Op-Amp and explain its operation. AKTU2017-18, Marks 05

Answer
1. The logarithmic amplifier is very sensitive to temperature. To minimize
the temperature effects, the circuit called temperature-compensuted
logarithmic amplifier is used, in which two matched diodes are used to
cancel the temperature-dependent offset term log I.
2. Similarly, a thermistor, which is a temperature-sensitive resistor can be
used to cancel the temperature-dependent scaling factor nV
3 The output voltage of Op-Amp A, ia negative of the voltage across diode
D, and is given by
 & Non-Linearity
3-16A (EC-Sem-5) Frequency Compensation

.3.12.1)
- V - nV,| log- log ,
4. Similarly, the voltage across diode D, is given by 3.12.2)
Vlog- log is
is the reverse saturation current
where is the forward current andi,
of diode D,
are same.
reverse saturation currents
5. As both diodes are matched, their
The voltage at the non-inverting
terminal A, is given by
of Op-Amp
..(3.12.3)
Vo Vn=- nV, log|
+

the
offset term is eliminated from
6. Thus, the temperature-dependent and its output
output of A,. The Op-AmpA, isa non-inverting amplifier
is given by

..(3.12.4)

(R+R +znv, log 13.12.5)

R, +R R
7. Thus the circuit shown in Fig. 3.12.1 cancels the temperature-dependent
output
at the of the log amplifier and provides a
terms present
temperature-independent logarithmic output.

R R
ww wwwT W
L

2
V2
K
01

Pig. 3.12.1.Cirout for a temperature-compensated logarithmic amplifier.

Que 3.13. Derive the expression for output voltage of temperature

compensated anti-log amplifier.

Answer

The temperature compensated anti-log amplifier is shown in

Fig. 3.13.1. This circuit uses a constant current source , as shown
in Fig. 3.13.1.
 Integrated Circuits
3-17A (EC-Sem-5)

A is at virtual
ground
w
R

V2 V,

Fig. 3.18.1. Temperature compensated antilog

2 The voltage at
amplifier
non-inverting terminal of Op-Amp is given by,
R,

1R+R)" ...3.13.1)

3 Output voltage of first Op-Amp which is acting as a subtractor is given

Oy,
V = V1-Vrn

RPV. -V» ...3.13.2)

4. The expression for the forward
voltage acrOss the diode 1 is given by
V-n V, llog, (U) log, 7,) -

5.
Substituting the value of V in eq. (3.13.2) we get,

R R Va-n V, log,4)-log, ,
..(3.13.3)
6. Applying the concept of virtual ground to the second
amplifier in
Fig. 3.13.1 we get,

V-VP2=-n V7llog, )-log, (,) .(3.13.4)

where
I=and l,=1,
7. Equating eq. (3. 13.3) and (3.13.4) we
get,
R R n V,llog, (l,) - log, , l = - n V , log, (V, / V ) - log, ,

R,+R.-rlos,
R ,) -n Vylog, (V, /V)

RR. Vrllog, ) - log, (V, /V)I

 & Non-Linearity
3-18A (EC-Sem-5) rrequeney Compensation

7,R
= n V,log, V
RR
precision reetifier? Explain
Que 3.14.| What do you understand by
rectifier.
the working of half wave precision

Answer
ideal diode for
A Precision r e c t i f i e r : A circuit which can act as an
cut-in voltage of the
which a r e below the level of
rectifying voltages
circuit.
diode a r e called precision rectifier
half
precision rectifier: Fig. 3.14.1 shows a precision
B. Half wave ofa diode placed in the negative-feedback
w a v e rectifier circuit consisting
resistance.
with R being the rectifier load
path of a n Op-Amp,
C. Operation:
Op-Amp will go positive
1. Ifv, goes positive, the output voltage v of the
closed feedback path
and the diode will conduct, thus establishing
a
terminal.
terminal and the negative input
between the Op-Amp's output
c a u s e a virtual short circuit
to appear
2. The negative-feedback path will
between the two input terminals.
terminal, which is also the output
3. Thus the voltage at the negative input
will (to within a few millivolts) that at the positive input
equal
voltage vo.
terminal, which is the input voltage u,,

Consider now the case when v, goes negative. The Op-Amp's output
4.
will tend to follow and go negative.
voltage vA
and current will flow through
This will reverse-bias the diode,
no
5.
to 0 V. Thus, for v, < 0,
resistance R, causing vo to remain equal

uperdiode"

Fig. 3.14.1. Half wave precision rectifier.

Integrated Circuitss 3-19 A (EC-Sem-5)

V
i

D-ON D-OFF
Fig. 3.14.2. Waveform of Half wave precision rectifier

Que 3.15.| Draw the circuit diagram of full wave precision rectifñer
and find expression for output voltage for both
positive and negative
half cycle of input sinusoidal waveform.

AKTU 2018-19, Marks 07

OR
Explain orking of precision full wave rectifier with necessaryY

wavefor.
AKTU 2016-17, Marks 10
OR
What are precision rectifiers ? Describe the working of single
Op-Amp based full wave precision rectifier.

AKTU 2019-20, Marks 07

Answer
A. Precision rectifier: Refer Q. 3.14, Page 3-18A, Unit-3.
B. Full wave precision rectifier:
1. For positive half cycle of V, diode D, will be ON and D, will be OFF.
Both the Op-Amps will act like inverter and thus, V, will follow the input
From Fig. 3.15.2,
WWT W
R

Vo
3-20 A (EC-Sem-5) Frequency Compensation & Non-Linearity

Hence, Vo n =-Vin
and v= V , )= Vn

R R

Vin o W
oVo
Vo1

Fig. 3.15.2.
diode will be OFF and D, will be ON.
2. In negative half cycle of Vi D,
W
01
2R

Vino Vo
01

W
Fig. 3.16.8
Applying KCL at nodeA,

0
R R 2R
Now, V = 0 IVirtual ground concept

in1o
R
=0
V 2
27
o1 3 Vin

i. Also,

Hence, for
V= V
 Integrated Circuits 3-21 A (EC-Sem-5)

Vint

Fig. 3.15.4. Input and output waveforms of full wave

rectifier
Que 3.16. Explain the working of peak detectors.
AKTU 2018-19, Marks 3.5
Answer
1. Fig. 3.16.1 shows a peak detector that measures the positive peak values
o1 Square wave input.
2. For positive half-cycle of
V the diode D, conducts and charge capacitor
C to positive peak value V, of the input Vin i.e. the Op-Amp acts as a
voltage follower.
3. During negative half cycle of V diode D, is reversed biased and
open-circuit. Here voltage across Cis retained.
4. For proper operation of the circuit, the time constant
and discharging
charging (CR)
time constant
(CR,) must satisfy,
CR, S TI 10
Here, R= Resistance of forward bias diode
T Time period of input waveform
and, CR 2 107T
Here, R, is load resistor.
5. Ris very small, then use of buffer is needed between C and
R,.
R
W
741

c C

D2
Fig. 3.16.1.
6. Resistance R is used to protect the Op-Amp against the excessive
discharge currents, whhen power supply is switched OFF. D, conducts
during negative half cycle to present Op-Amp from going into negative
saturation and helps to reduce recovery time of Op-Amp.
3-22 A (BEC-Sem-5) Frequeney Compensation & Non-Linearity

7. The input and output waveforms is shown in Fig. 3.16.2.

in

DV

Vo

0V

Fig. 3.16.2.

Que 3.17. Describe the sample and hold circuit with the help of an
Op-Amp. What are the applications of sample and hold circuit ?

AKTU 2015-16, Marks 10

Answer
A Sample and hold circuit:
1 Fig. 3.17.1 shows the circuit for sample and hold using Op-Amp. It samples
an input signal and holds on to its last sampled value until the input is
Sampled again.

Pig.3.17.
2. Op-Amp and enhancement MOSFET is used in the circuit. MOSFET
acts as switch to control V, while C serves as a storage clement. Vi, to be
sampled is applied to drain andV, across the gate of MOSFET.
3 During positive portion of V, the MOSFET conducts and allow input
voltage to charge capacitor C.
Integrated Circuits 3-23 A (EC-Sem-5)

V.

No

Fig. 3.17.2. Input and output waveforms.

4. When V, is zero, the MOSFET is OFF and the discharge path for capacitor
Cis through the Op-Amp.
5. However, the input resistance of the Op-Amp voltage follower is also
very high: hence the voltage across C is retained. Fig. 3.17.2 shows the
input and output waveforms.
6. The time period T, of voltage V, during which the voltage across the C is
equal to the input voltage are called sample periods.
The time period 7, of V, during which the voltage across the capacitor C
is constant are called hold periods as shown in Fig. 3.17.2.

B. Applications
i PAM demodulator.

CM.
to digital converters.
i Analog

PART-3
Op-Amp as a Comparator and Zero Crossing Detector, Astable
Multivibrator and Monostable Multivibrator, Generation of
Triangular Waveforms, Analog Multipliers and Their Applications.

Questions-Answers
Long Answer 1ype and Medium Answer Type Questions
 3-24 A (EC-Sem-5) Frequency Compensation & Non-Linearity

Que 3.18. Write a short note on comparator and enlist its

applications.
Answer
A Comparator
1. A comparator is a circuit that is used for comparing a signal voltage
applied at one input of Op-Amp witha known reference voltage at other
input.

.
10

V-VREF 71 2
V,- VREX mV

-10

(a) (6)

Fig. 3.18.1. The transfer characteristics (a) ideal comparator

(6) Practical comparator.

2. It is basically an open-loop Op-Amp with output : V,(=Ve) as shown in

ideal transfer characteristics of Fig. 3.18.1(a).

3. There are basically two types of comparator:

a. Non-inverting comparator:

1. The circuit of Fig. 3.18.2a) is calleda non-inverting comparator. A fixed

reference voltage Vis applied to (-ve) input and a time varying signal
, 15 applied to (+ve) input.

2. The output voltage is at - V,a, for u, < V,er And v, goes to + V,, for

3 The output waveform for a sinusoidal input signal applied to the (+ve)
input is shown in Fig. 3.18.216) and (e) for positive and
negative V
respectively.
Integrated Circuits 3-25 A (EC-Sem-5)

OV

V +sat

V
ov
+V
, V,<ref
(c) Vrer negative
(b)Vrerpositive
Fig.3.18.2
b. Inverting comparator:
In inverting comparator, fixed reference voltage V, is applied to (+ ve)
input and a time varying signalv, is applied to (-ve) input.

R
ww

(a)
 & Non-Linearity
3-26 A (EC-Sem-5) Frequency Compensation

rer
OV

V OV

V.
V,>rd V,>-Vref
(b) (c)

Fig. 3.18.3. (a) Inverting comparator. Input and output waveforms

for (6) V 0 ( 0 Ve 0

B. Applications :
i Zero crossing detector
i Window detector
ii. Phase meter.

Que 3,19.| Write short notes on zero crossing detection.

Answer

1. The basic comparators can be used as zero crossing detector by makin

WE 0.

2. Whenever the input voltage crosses the x-axis, V, changes from + V , to

-V, or - Vto + as shown in Fig. 3.19.1.
Integrated Circuits 3-27A (EC-Sem-5)

R
w REF 0

Vre R=R,||R Vsat

Vin
(a) sat
Fig. 3.19.1

3. Zero crossing detector is also called sine to square wave generator.

There are two types of zero crossing detectors
a Non-inverting zero crossing detector:
1. In a non-inverting zero crossing detector, the Op-Amp is used in open
loop configuration. Inverting terminal of the Op-Amp is grounded and
input is applied to the non-inverting terminal. The cireuit is shown in
Fig. 3.19.2.

Reference voltage is set by zero

R V
in

Fig. 3.10.2. Non-invorting zero orossing detector

2. During the positive half cycle, the input voltage is positive i.e., above
the reference voltage (O V). Hence the output voltage is + V,ut
3. During negative half cycle, the input voltage Vin is negative, i.e., below
the reference voltage. The output voltage is then -

V,at
4. Thus the output voltage switches between + aA andVaat whenever
the input signal crosses the zero level. This is shown in Fig. 3.19.3.
3-28 A (Ec-Sem-5) Frequency Compensation & Non-Linearity

zero croSSing point

Vin

sat
Fig.3.19.3. Input is sinusoidal

b. Inverting zero crossing detector:

1. In the inverting zero erossing detector, input is directly applied to the
inverting input terminalwhile the non-inverting terminal is grounded.
The circuit is shown in Fig. 3.19.4.

Vin
RV
Reference voltage
set by zero.

Fig 3.19.4. Inverting zero crossing detecto

During positive half cycle, inverting terminal is more positive than
non-inverting terminal, so output is -Vat While for negative half cycle,
the output is +VaThis cireuit is called an inverter. The waveforms
are shown in Fig. 3.19.5.
Zero crossing point
in

V
V
Fig. 3.19.5. Input is sinusoidal.
Integrated Circuits 3-29 A (EC-Sem-5)

Que 3.20.| Deseribe the Schmitt trigger with help of proper cireuit

dingram and transfer characteristies. AKTU 2018-19, Marks3.5

Answer
1 If positive feedback is added to the comparator circuit, gain can be
increased greatly. This cireuit is called Schmitt trigger. It is basically an
inverting comparator circuit with a positive feedback.
R

in wM
V
W

W R

Fig. 3.20.1. Schmitttrigger

2 Schmitt trigger also exhibits the phenomenon of hysteresis. The input
and feedback voltage to the
voltage is applied to the (-ve) input terminal
(+ve) input terminal
3. Input voltage V, triggers output V,, every time it exceeds certain voltage
levels. These voltage levels are called upper threshold voltage (Vand
lower threshold voltage (Vr
4. Now, suppose the output V.= +Va The voltage at (+) input terminal

will be

(3.20.1
UTRR+
This voltage is upper threshold voltage. As long as V is less than Vi
the output V, remains constant at +

the output then switches to

5. When V, is just greater than VT
- V and remains at this level as long as V,> VT

the voltage at (+ve) input terminal

will be
6. For V, =
-

V
R, ..(3.20.2)
+R
This voltage is called lower threshold voltage.
long as Vis above or positive with respect
7 The output voltage is -

V as

The output voltage V, changes to +

V, il
Vgoes more negative
to V for input
Resistor H 18 shown as k, | K, compensate
than or below
V,r
bias current,
wavelorms are shown in Fig. 3.20.2.
. nput and output voltage
 & Non-Linearity
3-30 A (EC-Sem-5) Frequeney Compensation

in

VUTE

Fig. 3.20.2.

9. Hysteresis curve
(Transfer characteristics):
From eq. (3.20.1) and (3.20.2),
i
VTVer
2R
VuT-VarR+R,""
This difference is called hysteresis width.

+ sat

VLT VT

Hysteresis
volta
VH =(VUT-VLr'
-Vsat
Fig. 3.20.3

do not change the

dead band because change in V,,
ii. V, also called
is
Out switches from
output voltage.
That is when the input exceeds VUT
state,+ ,When the input
+VtoV and
reverts back
to its original
goes below Vr
into a square wave.
Uses: Schmitt trigger 18 u s e to convert any wave
10.
 Integrated Circuits
3-31 A (EC-Sem-5)

Que 3.21. Describe the Schmitt

trigger with the help of
circuit diagram and transfer proper
the upper threshold characteristics. A Schmitt trigger with
level VUT = 0 V and
converts 1 RHz sine wave of hysteresis width is 0.2 V
Calculate the time duration
amplitude
of the
4
VPp into a
square wave.
negative and positive portion of
the output waveform.
AKTU 2015-16, Marks 15
Answer
A Schmitt trigger and its transfer characteristics: Refer
Page 3-29A, Unit-3. Q. 3.20,
B. Numerical:

Given: VT 0,
V= 0.2 V.f= 1 KHz
To Find: Time duration.

So, VuVor-VLr=0.2V
LT-0.2V
2. In Fig. 3.21.1 the angle 0 can be calculated as
0.2 Vm sin (r 0)
+
=-Vm sin 0=-2 sin
a r c sin 0.1 = 0.l radian
V,
2 V

LT=0.2 T
VuTT 0V

T,

T
Fig. 3.21.1
3. The period, T / f = 1/1000 = 1 ms
oT, = 2n (1000) T, = 0.1

T= (0.1/2 T) ms = 0.016 ms
4. So, T = T/2 + T, = 0.516 ms
and T = T/2-T, = 0.484 ms
 Non-Linearity
Compensation &
Frequency
3-32 A (EC-Sem-5)

with a neat
circuit works
how a Schmitt trigger
Que 3.22.Explain with Vn 2 V, Vr
-
2 V.
Sechmitt trigger
diagram. Design
a

13 V. AKTU 2017-18, Marks 05

Assume V

Answer 3.20, Page 3-29A, Unit-3.

A Schmitt trigger : Refer Q.
B. Numerical:

Given: Vn= 2V, Vzr =-2V, +V. 13 V

To Design: Schmitt trigger
VuT
1 We know,
VTR+ R+V
2V= R+ -(+
R 13)
..3.22.1)
0.154
and LrRR-V

(-13)
.(3.22.2)

E 13 -0.154
and (3.22.2)
2. From eq. (3.22.1)

= 0.154
R+R
Let R,= 100
100 0.154
R+100
R, = 549.35N

in out

W
R, = 549.36

R =100
Fig 3.22.1,
 Integrated Circuits
- 3-33 A (EC-Sem-5)

Que 3.23. Draw the

with
circuit diagram for monostable multivibrator
operation al amplifier.
expression for its time period. Explain its operation. Derive the
OR
Draw and explain the working of monostable multivibrator
using
Op-Amp.
AKTU 2019-20, Marks o7
Answer
A Monostable multivibrator:
1. Fig. 3.23.1 shows the circuit
diagram of monostable
diode D, clamps the capacitor voltage to 0.7 V when multivibrator.
the
A
* sat output is at

2. The negative going

pulse signal magnitude V,of
passing through the differentiator (triggering signal)
R,C and diode D,
going triggering pulse and is applied produces negative
a
to the (+)
input terminal.
W

Fig. 3.23.1.
B. Operation:
1. For monostable operation, the trigger pulse width T, should be much
less than T, the pulsewidth of the monostable multivibrator.
2. The diode D, is used
avoidto
spikes that may be present at malfunctioning
by blocking the positive
the differentiated trigger
input.
3. Fig. 3.23.2 shows the trigger and output waveform.
4. When V, is
+V,at' voltage divider R, and R, feedback VT to the (+ve)
input. The diode D, clamps the (-ve) input at approximately 0.7 V
(because the diode is forward biased).
5 The feedback voltage at (+ve) terminal is higher than (-ve) terminal
therefore Op-Amp holds V, at
state.
+Vwat This output state is called as stable
3-34 A (EC-Sem-5) Frequency Compensation & Non-Linearity

6. If the negative spike (trigger signal) is applied to (+ ve) of Op-Amp

which is higher than the voltage at (-ve) terminal. The combination o
feedback voltage and negative trigger voltage will be pulled below the

voltage at (-ve)
input
7. Once the (+ ve) input becomes negative with respect to the (- ve)
input, V switches to -Vsnt With this change, the one-shot is now in its
timing state. This state is an unstable state.
8. Due to V.= - V,at the diode D, is reverse biased and the capacitor C
and more
the -ve) input. The (- ve) input becomes
more
charges,
negative with respect to ground. When the capacitor voltage is more
than (+ ve) terminal, V, switches to + Vsat

Trigger-
pulse after
diode D

0.7 V
Capacitor
voltage Vc

* * * * * * * * * * * * * * * * * .

**
+gat Stable
state

Quasi stable state

T-
This width depends on
the value of R and C
Pig, 3.23.2. Iaput and output waveform
C. Expresston for time period :
1. The general solutionfor a signal time constant low pass RC cireuit with
V, and V,as initial and final value is

V V+ (V-V e-tRC
2. For the circuit, V-V. and V, = Vp ( diode forward voltage)
Integrated Circuits 3-35 A (EC-Sem-5)

The output Vc is
Vc-sat + (Vp+ Vnt) e-RC ...(3.23.1D
Ifthe time constant T= RC and whent = T

Ve= -BVsat

eR+Ra
where R2
Therefore
R+R2
4. After
-BVsa-V«t+(p+VseuRC
simplification, the pulse widths is obtained as
T RC n+V%/V ..(3.23.2)
-B
IfV.at> V and R, = R, so that p = 0.5 then
T= 0.69RC

Que 3.24.A monostable multivibrator is to be used as

divide-by-4 network. The frequency of input triKger is 12 KHz. If
the value of C 0.05 F, what should be value
=
of R?
Answer

Given:f-12 KHz, C = 0.05 uF

To Find:R.
For a divide-by-4 network, , should be slightly larger than thrice the
period of the input trigger signal.
2. Let 3.2 7T

Therefore . 12 KH 3.2 x 8.33 x 105

26.656 x
10-° secc
, 1.1RC = 26.656 x 10-

R=26.656 x10 k N = 5kn

1.1 x
0.05 x 10-.84
Que 3.25.1 Explain astable multivibrator with its waveform.
 & Non-Linearity
3-36 A (EC-Sem-5) Frequeney Compensation

Answer
i8 also called as astable multivibrator or free
1. Square wave generator
running osCillator.
Circuit of square wave generator is as shown in Fig. 3.25.1. The principle
to operate in
of square wave output is to torce an Op-Amp
of generation
the saturation region.

3. Afraction of output is fed back to the (+ ve) input terminal. This fraction
is given by,

R+R
ww

Fig. 3.25.1
4. Thus, the reference voltage is BV, and may take values as + pV

after
The output is also fed back to the (-ve) input terminal
or
-pVat (-ve) input terminal voltage
integrating by RC combination. When
wave output.
exceedsREP SWitching takes place resulting in square

Vo
+BVsat

Fig. 3.25.2
5. Now, consider the waveform shown in Fig. 3.26.2. When the output is at
+VCapacitor C starts charging through R. Voltage at (+ ve) input
terminal is + BV.at Now as the charge C' rises above this reference
voltage + pV,a Output switches to - V,.t
Integrated Circuits 3-37A (EC-Sem-5)

6. At this instant,
voltage on the capacitor is +pV..tt hence it starts
discharging through Rie., towards-pV,When output voltage switches
to
V the capacitor charges more negatively until its
voltage just
exceeds-BV.
7. The output switches back to +
V, and hence the eycle repeats itselt.
8. Now, voltage the
across
capacitor, as a function of time is given by
V) =
VRnal + (mitialVina) e C
As,
Vinal+Vsat
and
initia pV,.
V) V. (-BV.V.)e
= +

V ) = Va -V,a (1 + p)e-tRC
RC

9. Att = t,, voltage across capacitor reaches to +BVa therefore,

After solving,
V)=pV, VVt (1+p)e tuRc

RC In-
This is only half of the tetal period.
.
Total time period 2,= = 2RC In
Que3.26.| Explain the generation of square and triangular
waveforms from astable multivibrator operation using
Op-Amp. Also find expression of the time period for both cases.

AKTU 2016-17, Marks 15

OR
Draw and explain the circuit of triangular wave generator. How
square wave can be obtained using this triangular wave.

AKTU 2017-18, Marks 05

Answer
A Generation of square waveforms : Rofer Q. 3.25, Page 3-35A,
Unit-3.
B. Generation of triangular waveforms:
A triangular wave can be simply obtained by integrating a square
wave.

2. Triangular wave generator along with waveforms is shown in

Pig. 3.26.l (a).
 3-38 A (EC-Sem-5)
Frequency Compensation & Non-Linearity

w
3 R A

(a) Triangular wavelorm generator

Voltage
+Vat

ran
2
-V sat
(b) Waveforms.
Fig. 3.26.1.
Working:
Assume output of comparator A, is at +Vat SO output of integrator will
be a negative going ramp as shown in Fig. 3.26.1(6).
2. When the negative going ramp reaches to -VFamp the output of A,
switches trom + to -Vsat The sequence then repeats to give
triangular wave at the output of Aq.
3. The frequeney of triangular waveform can be calculated as follows
The effective voltage at point P during the time when output of A, is at
+satevel is given by,

-V R,+ R, .(3.26.1)
A t t t , the voltage at point Pbecomes equal to zero. Therefore from
eq. 3 . 2 6 . 1)

..13.26.2)
ii. Similarly, at t = t when the output of A, switches from -V.a to

at
ramp R,
iv. Therefore, peak to peak amplitude of the triangular wave is
Integrated Circuits
339 A (EC-Sem-5)

V.pp)= +Tam ramp ...(3.26.3)

V. The R.
output switches from
Putting the values in the basic
-Vam to
+ram, in half the time period T/2.
integrator equation,
V.= udt

V,pp)= -Vt =
RC,\ 2)

T 2RC, Pp) ..(3.26.4)

vi. Putting the value of V.pp) from eq. (3.26.4), we get
T GR
Hence the frequency of oscillation f, is,

fT4RcR
Que 327.| Write a short note on analog multiplier also give its
applications.
OR
Write short notes on the following:
i Analog multiplier.

i. Logarithmic amplifier.
AKTU 2018-19, Marks 07
Answer

Analog multiplier:
A multiplier is an active network whose
output is proportional to the
product of two input signals.
Fig. 3.27.1 shows the basic block diagram of an analog multiplier, which
uses
two logarithmic amplifiers, an adder, and an antilog amplifier.
Log
In(V,)

dder InVx V2Antilog

amp
Log
V mp
IaCv

Pig 3.27.1. Banic block diagram of an analog

3. The
multiplier
input signals, which are to be multiplied, ure applied to the input
loganthmic anplifiers.
3-40 A (Ec-Sem-5) Frequency Compensation & Non-Linearity

the logarithm of the input signal and

The logarithmic amplifiers produce
these outputs are applied to the adder circuit.
5. The output adder circuit, which is the logarithm
of the of product of the
two input signals, is fed to the anti-log amplifier.
the terms and
5. The anti-log amplifier finally removes the logarithm of
produces the multiplication of the input signals.
i.e., VxV2= Anti-log (V, xV2)
Applications of analog multiplier:
a. Squarer circuit:
1. The squarer circuit is shown in Fig. 3.27.2.The basic multiplier can be
used to square any positive or negative number provided the number
voltage between O to
can be represented by a
VRE
The voltage V, representing the number is connected to both the inputs
It is possible to square a sine wave voltage too.

3. In Fig. 3.27.2, if a sine wave voltage e, = V, sin ot is applied to both the

inputs, then the output voltage, v, is given by

REF
4. Forr , b Sin 27 x 10°t and
VRE =
10 V,

= ( s i n 27 x 1014 = 2.5 cos 2rt x 2*10't

2
1.25 1.25 cos 2 x 2 x 10t
The output contains a DC term and frequency is doubled.

10 kN

Fig. 3.27.2.
b. Phase angle detection:
1. If the input signals applied to a multiplier are
, Sin ot
(ot + 6)
,mySin
2. Then, u = m sin ot sin (ot + 0)
U. VRR
x
icos - cos (2ot 0) +
Integrated Circuits 341A (EC-Sem-5)

3. The phase difference 0 between the two point signals can be caleulated
from the DC component in the output voltage V That is,

.DC 2RREF
x COs0
ii. Logarithmic amplifier: Refer Q. 3.10, Page 3-13A, Unit-3.

Que 3.28. What do you mean by the quadrant operation of

multiplier? Draw and explain a GILBERT analog multiplier.

AKTU 2017-18, Marks 10

AKTU 2019-20, Marks 07
Answer
A quadrant operation of multiplier
1 The quadrant defines the applicability of the cireuit for bipolar signals at
its inputs.
2 Pirst-quadrant device accepts only positive input signals, the two
guadrant device accepts one bipolar signal and one unipolar signal and
the four-quadrant device accepts two bipolar signals.
B. GILBERT analog multiplier
1. The GILBERT multiplier cell is a modification of the emitter coupled cell
and this allows four-quadrant multiplication. Therefore, it forms the
basis of most of the integrated cireuit balanced multipliers.

ca lest
,
ca

Fig. 3.28.1. GiLBERT multiplier coll.

2. Two eross-coupled emitter-coupled pairs in series connection with an
emitter coupled pair form the structure of the GILBERT multiplier eell.
3 The collector currents of Q, and Q, are given by
3-42 A (EC-Sem-5)) Frequeney Compensation & Non-Linearity

C 3.28.1)

and ...(3.28.2)

4. Similarly the collector currents of Q, and Q, are given by

.28.3)

and ...(3.28.4)
+e

5. The collector currentsI, a n d o f transistors, and Q, can be expressed

as

E ...3.28.5)

and ..(3.28.6)
ea+y
6. Substituting eq. (3.28.5) in eq. (3.28.1) and (3.28.2), we get

BE ..3.28.7)
es11eI11+e*
and ...(3.28.8)
c 1+eV][1+ e ""*]
7. Similarly, substituting eq. (3.28.6) in eq. (3.28.3) and (3.28.4), we get

..(3.28.9)

and ..(3.28.10)

8. The differential output current Al is given by

That is,
a= tle)-d+ln
3.28.11)
9. Substituting eq. (3.28.7) to (3.28.10) in eq. (3.28.11) and employing
exponential formulae tor hyperbolic functions, we get

V
A =Eunh tanh|; ...3.28.12)
eq. (3.28.12) shows that when V, and V, are smal, the GILBERT cell
shown in Fig. 3.28.I can be used as a four-quadrant analog
multiplier
with the use of current-to-voltage converters.
 4
UNIT
Digital Integrated
Circuit Design

CONTENTS
4-2A to 4-16A
Part-1 : An Overview, CMOS Logic Gate ..
Circuits, Basic Structure, CMOS
Realization of Inverters, AND,
OR, NAND and NOR Gates
. 4-16A to 4-23A
Part-2 :Latches and Flip-Flops:.**.******************
The Latch, CMOS
mplementation of SR
Plip-Flops, a Simpler CMOS
Implementation of the Clocked
SR Flip-Flop, CMOS Implementation
of J-K Flip-Flops,
D Flip-Flop Circuits

4-1A (EC-Sem-5)
4-2 A (EC-Sem-5) Digital Integrated Circuit Design

PART-1
An Overvieu, CMOS Logic Gate Circuits, Basic Structure, CMOs
Realization of Inverters, AND, OR, NAND and NOR Gates.

CONCEPT OUTLINE

Digital IC technologies and logic-circuit families

CMOS BiCMOS GaAs

Bipolar

Comp- Pseudo-
Pass Dynamic TTL ECL
lementary NMOS Transistor logicC
CMOS logic
CMOStechnology is the most dominant ofall the IC technologies
available for digital circuit design.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 4.1. Diseuss CMOS circuit and its features.

Answer
A CMOS circuit:
1. The CMOS logic gate consists of two networks.
The pull-down network (PDN) constructed of NMOS transistor.
i. The pull-up network (PUN) constructed of PMOS transistors.

The two networks are operated by the input variables, in a

complementary fashion.
3. Thus, for the three-input gate represented in Fig. 4.1.1, the PDN will
conduct for all input combinations that require a low output (Y= 0) and
will then pull the output node down to ground, causing a zero voltage to

appear at the output, v, = 0.

Simultaneously, the PUN will be OFF, and no direct DC path will exist
between Vp and ground. On the other hand, all input combinations
that call for a high output (Y = 1) will cause the PUN to conduct, and the
 4-3A (EC-Sem-5)
Integrated Circuits output
establishing an
the output node up
to Vpp:
PUN will then pull
voltage v, p
VpD
A Pull-up networ
(PUN)
o

A Pull-down etwork
BO (PDN)

CMOS logic gate.

of a three-input
4.1.1. Representation the PDN
Fig. PMOS t r a n s i s t o r s , and
The PUN comprises
comprises NMOS transistors.

no DC
current path
and again,
PDN will be cut-off,
5. Simultaneously, the circuit.
exist in the
and ground will
between VDD
B. Features: state; it
or GND and in steady
connected to Vpp voltage t r a n s t e r
The output is always
L
swing
(between 0 V and VpD
gives full logic margin8.
and large noise
characteristics
of the devices.
the relative sizes
levels are not dependent upon s t a t e . Thus,
2. Logic and GND in steady
There is no direct path between VpD
3. is negligible.
of CMOS circuit
static power dissipation
and fast switching speed.
4. It has high input impedance
fan-in and fan-out on propagation
the effect of
Que 4.2. Explain
cireuit.
delay in CMOS digital logic

Answer
additional input
of its inputs. Each
1. The fan-in of a gate number is the
transistors, one NMOS and
requires two additional
toa CMOS gate
one PMOS. but also the
not only increases the chip area

The additional transistor the propagation delay.

increases
per gate and
total effective capacitance
device size, we are
able to preserve the current-driving
3. Byincreasing
capability. increased
both the
However, the capacitance
C i n e r e a s c s because of increases
4. device size. Normally delay
and i n c r e a s e in
number of inputs
followinga quadratic function of fan-in.
4-4A (EC-Sem-5)
Digital Integrated Circuit Design
5. An increase in a gate's fan-out adds
thus, increases its directly to its load capacitance and
propagation delay.
Que 4.3. Explain the working operation of CMOS inverter with
VTC characteristics.

Answer
A CMOS inverter circuit:
1. Fig. 4.3.1 shows the CMOS inverter. In the CMOS
and NMOS devices inverter, the PMOS
Qp and Qy are driven simultaneously by an input
in
VpD

Vost
H
Fig. 4.3.1. CMOS ínverter circuit.
B. Working operation:
1. When input is high (=
Vpp)Qy is made to conduct, while as isshown
cut-off. This causes the output becomes low (V, = 0) &p
forced to
in
Fig. 4.3.2.

DD
OFF

V==0
HON
Fig. 4.3.2.
2. When input is low ( 0 V) ey is OFF and Q, becomes ON, therefore the
output becomes logic high (V, = VDn as shown in Fig. 4.3.3.

DD

ON
V0 oV,= 1

OFF
Fig 4.3.3.
 4-5 A (EC-Sem-5)
Integrated Cireuits

inverter circuit.
3. Table 4.3.1 shows the operation of COMS
Table 4.3.1.

OFF
ON

OFF ON

characteristics:
C. Voltage transfer
4.3.4, the positive output voltage corresponds
more
to
1. As shown in Fig. corresponds
and the m o r e negative output voltage
a logic 1 is VOH VDLD
to a logic 0 1s VoL
the PMOS transistor is
cut-off and
2. When output is in the logic 0 state,
transistor is cut-off.
when the output is in the logic1
state, the NMOS

NMOS cut-off
VOH DD

VTP Threshold voltage

for PMOS transistor

VoL DD in

VTND-VTP
Fig. 4.3.4.

Que 44.Derive the formula for VIz

and VIH of CMOS inverter.
AKTU2016-17, Marks 7.5
AKTU 2018-19, Marks 07
OR
for CMOS inverter over its
Describe different regions of operation
VTC characteristics.

Answer
The NMOS transistor operates in saturation if Vin> VT,N and if the
condition is satisfied.
following
4.4.1)
VDN,N2VO,N-V0.NV2V-VT0, N
2. The PMOS transistor operates in saturation ifV <(p+Vu,p, and if:
.4.4.2)
V,Vox- VmpVS V-
3. The table 4.4.1 lists these regions and the corresponding critical input
and output voltage levels.
4-6 A (EC-Sem-5)
Digital Integrated Circuit Design
Table 4.4.1.
Region NMOS PMOS
A
< p. N Von cut-off linear
B
IL high= VowSaturation linear

Vh saturation saturation
D low= VoL linear
IH saturation

(VpD o, P VOL linear cut-otf

4. In region A, where Vi < Vny» the NMOS transistor is cut-off and the
output voltage is equal to
VoH =Vp
5. As the input voltage is increased beyond Vp, N (into region B), the
NMOS transistor starts conducting in saturation mode and the output
voltage begins to decrease. The critical voltage V, which corresponds
to (d Vjd Vi)=- 1 is located within region B.
6. As the output voltage further decrease, the PMOS transistor enters
saturation at the boundary of region C. It is seen from, Fig. 4.4.1 that
the inverter threshold voltage, where Vn = Vu is located in region.

DD
VGS.P
PMOS| Vps. P

VinVos. N D, N outDsN

1NMOS

Fig.44.1. CMOS inverter cireuit.

7. When the output voltage Vu falls below ( Vo, w), the NMOS
transistor starts to operate in linear mode. This corresponds to region
D in Fig. 4.4.2, where the critical voltage point Vi with
(d V d V,) =- 1 is also located.

8. Finally, in region E, with the input voltage V > ( + Vu, p. the

PMOS transistor is cut-off, and the output voltage is Vo = 0.
 4-7A (EC-Sem-5)
Integrated Circuits

Vout
outinTo,P
VpD

Voutin V», N
NMOS in
saturation

PMOS in
saturation

EEEEE both in
3saturation
in
DD
IH DD* To, P

VTo, P To,N
PMOS transistors
regions of the NMOS and the
Fig. 44.2. Operating

Calcuiation of V
is equal to (-1), i.e., dVdVn=-1|
the slope of the VTC
By definition,
when the input voltage is V VIL
in s a t u r a t i o n
the NMOS transistor operates
2. Note that in this case,
transistor in the linear region.
operates
while thePMOS
current equation:
obtain the following
From
p x=ppwe
4.4.1)
(2Vas,P Vro, pVns,P-VËs,pl
-

S.NV?o, w"=
(V-Vpp-(VVpD
(V-V,=2 (V-V»-Vz»
..4.4.2)
differentiate both sides of
To satisfy the derivative
condition at VIL, We
4.
eq.(4.4.2) with respect to V

-VpD
VD
-

Vro,p) dVn( u
k, V - T . n = k| (Vn
.4.4.3)
-Vaw
(4.4.3), we obtain
Substituting V =
V and (dV, dVn=-1 in eq.
5.
4-8 A (EC-Sem-5) Digital Integrated Circuit Design

k,(VLV x) = k,(2V,ur - V+ Vm. p - VoDd 4.4.4)

6. The critical voltage V, can now be found as a function of the output
voltage Vot as follows:
2outVro,p-Vpo
+ hg
+r Yro, N (4.4.5)

where k, is defined as,

k,
Calculation of V
When the input is equal to V the NMOS transistor operates in the
linear region and the PMOS transistor operates in saturation.

2. From p, x=lp,P
1206s N-Vro, N)Vps, N-Vos.nl =Vos,P- Vro, p.4.4.6)

2(V-Vro, N) V, Vl= nVoo-Vro,p (4.4.7)

3 Now, differentiate both sides of eq. (4.4.7) with respect to Vn

V-Vro.x V-Vaud
k,V,-VDD- VT p.(4.4.8)
=

obtain
4 Substituting V,n Vu and (dV,u,/ dV,,)=-1 in eq. (4.4.8),
=
we

k(V+Va + 2V) =k, (Vn=VoD Vn 4.4.9)

5. The critical voltage V can now be found as a function of as follows :

VIHDD Vro,p **a (2 Vro.N ...(4.4.10)

1+k
Que45. Describe different regions of
inverter over its VTC characteristics.
operation for CMOS

Considera CMOS inverter with following parameters:

0.7 V,
VpD3.3 V, Vr,w=0.6 V, Vro,p
200 AN, k, =80 pAVa
Calculate the noise margin of the CMOS inverter circuit.

AKTU 2016-16, Marke 15

Answer
A Regions of operation for CMOS: Refer Q 4.4, Page 4-6A, Unit-4.
 4-9A (EC-Sem-5)
Integrated Circuits

B. Numerical:
Given: Vpp=3.3 V, V, N=0.6 V, V0,p =0.7 V,k, = 200 uAN,

80 uAWM Nno bon TUl10)0A

To Find: Noise margin.
1. We know, kg k200=
80 2.5
2. As VoL = 0 and VOH = 3.3 V, to calculate V, in terms of the output
voltage, we use

2Vout +Vro,P-VDD +RR VTo, N

VL 1+k
2 Vout 0.7-3.3+1.5
1+2.5
..(4.5.1)
0.57 Vout-0.71 ...4.5.2)
3. Also, k,(V- Vz =
k(2VV V.-VDD +
Putting value of V in eq. (4.5.2), we get
2.5(0.57 Vout-0.71 -0.6) 200.57 Vout-0.71-3.3 +0.7)
=

(ot3.3)-(out3.3* (4.5.3)
5. This expression yields a second-order polynomial in Vout as follows:

0.66 V+0.05Vou 6 . 6 5 = 0 .4.5.4)

Vot 3.14 V ..4.5.5)
6. From eq. (4.5.1), we can calculate the critical voltage Vz as :

VL= 0.57 x 1.08 V

3.14-0.71 =

7. To calculate VI in terms of the output voltage, use

DDVTo.p tn (2 VutVro. ..4.5.6)

l+R
3.3-0.7+ 2.52Vou U.0=143 V.+1.17 4.5.7)
1+2.5
.4.5.8)
8.
9.
Again, k, (- V+ VTwx+ 2Vk, (V-VpD-Vp
Now, substitute the value of Vin eq. (4.5.8),
2.51201.43 Vut + 1.17-0.6VuV= (1.43 Vo-1.43) ...4.5.9)
2.61 Vou+6.94 Vout-2.04 0
10. On solving, we
get,
out0.27 V .4.5.10)
11. From eq (4.5.9) and (4.5.10) we can calculate the critical voltage V a
VIH = 143 x 0.27+1.17=1.66 V
12. Finally, we find the noise margina for low voltage levels and for high
voltage levels

NM- V-Vot = 1.08 V

4-10 A (EC-Sem-5) Digital Integrated Circuit Design

NMHVOn- ViH = 1.75 V

Que 4.6. Discuss the features of CMOS circuit. Realize one

AND-OR-INVERT (AOI) and one OR-AND-INVERT (OAD funetion
using CMOS logic circuit.
AKTU2017-18,Marke10
AKTU 2019-20, Marks 07
Answer
i Features of CMOS circuit: Refer Q. 4.1, Page 4-2A, Unit-4.
ii. AOI and OAI funetions:
1. AOI and OAI functions can be implemented with just one gate level
transistor. Both the complex gates have a propagation delay equivalent
to that of a single NAND or NOR gate.
2. AOI and OAI gates are essentially representations of SOP and POS
expressions of functions respectively.

DD

A
Bo
CMOS logic circuit.
Fig. 4.6.1.AOI realisation using

3. Let us implement the function,

F= AB+ CD
their s u m is the OR
two AND functions and
Here, AB and CD are
as an
inverted. Thus F can be implemented
function, which is finally
AOI gate.
4. Fig. 4.6.1 shows the CMOS
realization
of an AOI gate.
Integrated Circuits 4-11A (EC-Sem-5)

5. The CMOS realization of the OR-AND-INVERT (OA) gate is the dual of

that for the AND-OR-INVERT gate and is easily obtained by flipping the
latter end-for-end while interchanging all NMOS circuits with PMOS
Circuits and vice versa, as shown in Fig. 4.6.2.

6. The output expression for OAI gate is,

F (A+B)C+ D)

DD
A4 pc C

B PD D
F

A sa B

c-
Fig. 4.62.CMOS realisation of an OAI gate.

Que 4.7.Sketch the CMOS logic circuit realization of the

expression
Y= A(B +C)+ DE

AKCTU 2018-19, Marks3.5

Answer
CMOS logie circuit reslization of

Y A(B +C)+ DE
4-12 A (EC-Sem-5)
Digital Integrated Circuit Design

VDD
B4
CD

D-L E-4

A D

CA
Fig. 4.7.1
Que 4.8.| Design a CMOS half adder circuit with inputs A and B.
AKTU 2016-17, Marks 7.5

Answer
1 For CMOS half adder:
Sum=A DB
Carry = AB

2. CMOS half-adder circuit is shown in Fig. 4.8.1.

DD DD

VDD

Carry pD

IL Sum
B

Fig. 4.8.1
Integrated Circuits 4-13 A (EC-Sem-5)

Que 4.9. Design a CMOS full adder circuit with inputs A, B, and
C and two outputs S and
C,
Answer
1. The sum (S) and carry (C) of the full adder are defined by the following
two combinational boolean functions of the three input variables, A, B,
and C.

Sum, S= A B eC = ABC+ ABC + ABC + ACB

Carry, C. AB+ AC + BC
CMOS implementation:
DD

JP
V pD
B

-A

-B

Fig. 4.9.1. Transistor-level schematic of the one-bit full-adder circuit.

Que 4.10. Realize the circuit of2 input NOR gate and 2 input NAND
gate using CMOS and explain the operation.

AKTU 2019-20, Marks 07

Answer

A. 2input NOR gate:

Realization of 2 input NOR gate circuit is shown in Fig. 4.10.1.

T YpD
A-4C
B-4
Ot

AHL B-LL

Fig. 4.10.1
4-14A (EC-Sem-5)
Digital Integrated Circuit Design
Operation: The logic operation of NOR gate is such that the output is
HIGH only when all inputs are LOW for
remaining all other conditions,
the output is LOW.
B. 2 input NAND gate:
Realization of 2 input NAND gate circuit is shown in Fig. 4.10.2.
Operation: A NAND gate produces a LOW output only when all the
inputs are HIGH. When any of the inputs is LOW, the output will be
HIGH.

-DD

B-L

A
A L

BH
Fig. 4.10.2.

Que 4.11. Sketch a CMOS logic circuit that realizes the funetion:
F -ABC+ DEF (use only CMOS NOR gate)
P, = (A +B C) (D+E +F) (use only CMOS NAND gate)

Answer
1 Given, F = ABC +DEF = ABC.DEF= (A + B+ )-(Ö+ Ë +F)
CMOSlogic cireuit:
DD
D

B4 -E
-P
T-4
ABC DEP
F = +

411.1
 Integrated Circuits 4-15A (EC-Sem-5)

2. Given, F, = (A + B+C)(D+ E + F)
-
(A+B C+ (D+E+F
= (A BC)+(DE F)
CMOS logiccircuit:

pD

B- C

F2= (A + B + C) (D + E + F)

B-

Fig. 4.11.2

Que 4.12 Give two different CMOS realizati on of the

Exclusive-OR gate funetion in which the PDN and PUN are dual

network.
AKTU 2017-18, Marks O5
Answer
1. For Exclusive OR function we have,
Y= AB + AB

Y AB+ AB = AB AB = (A +B) (A + B3

AB+ AB

Realization I:
2. Note that Fig. 4.12.16b) is drawn by converting parallel networks of
Fig. 4.12.1(a) to serial networks.
3 Now by connecting PUN of Fig. 4.12.1(a) with PDN of Fig. 4.12.16) we
can realize Exclusive-OR function.
4-16 A (EC-Sem-5)
Digital Integrated Circuit Design
+
DD
Y

A Bt

B
***

Parallel network=
to serial network
(a) PUN for Y = A B+ AB
(b) Dual of Fig. 4.12.1(a)
Fig.4.12.1
Realization II:

PDN for Y =AB + AB is shown in Fig. 4.12.24a).

Note that Fig. 4.12.26) is drawn by converting series networks into

parallel networks.
5. Now by connecting PUN of Fig. 4.12.26) with PDN of Fig. 4.12.2(a) we
can realize Exclusive-OR function.
*DD

B-

'..
Series network
to parallel network
(a) PDN for Y = AB+ AB (b) Dual of Fig. 4.12.2(a)

Fig.4.122.

PART-2
Latches and Flip-Flops: The Lateh, CMOS Implementation of SR
the Clocked SR
Flip-Flops, a Simpler CMOS Tmplementation of
Flip-Flop, CMOS Inplementation of J-K Flip-Flops,
D Flip-Plop Circuits,
 Integrated Circuits
4-17A (EC-Sem-5)

Questions-Answers
Long Answer Type and Medium Answer Type Questions

latch.
Que 4.13. Write a short note on

Answer
1. The basic memory element, the latch, is shown in Fig. 4.13.1la). It
and
2.
consists of two cross-coupled logic inverters, G, G
The inverters form a positive feedback loop. To investigate the operation
of the latch we break the feedback loop at the input of one of the
inverters, say G, and apply an input signal, t , as shown in Fig 4.13.16).
3. Assuming that the input impedance of G, is large, breaking the feedback
loop will not change the loop voltage transfer characteristic, which can
be determined from the circuit of Fig. 4.13.16) by plotting vz versus vw
This is the voltage transfer characteristic of two cascaded inverters and
thus takes the shape shown in Pig. 4.13.1(c).

VOR
Unstable
w peran
point w
Stable
Operating
point
versus w

vy Stable operating point

6)
W

Fig. 4.13.1. (a) Basic latch. (6) The latch with the feedback loop opened.
(c) Determining the operating pointls) of the latch.

5. Observe that the transfer characteristic consists of three segments with

the middle segment corresponding to the transition region of the
invert
rters.
6. Also shown in Fig. 4.13.1(c) is a straight line with unity slope. This
straight line represents the
relationship Uw = that is realized
reconnecting Z to W to close the feedback loop.
Uz by
7. As indicated the straight line intersects the loop transfer
curve at three
points, A, B and C. Thus, any of these three points can serve as the
operating point for the latch.
8 While points A and C are stable operating points in the sense that the
circuit can remain at either indelinitely, Point Bis an unstable
operating
point, the latch cannot operate at B tor any significant period of time.
4-18 A (EC-Sem-5) Digital Integrated Circuit Design

of clocked SR
Que 4.14. | Realize a
simpler CMOS implementation
flip flop. Also explain the working of circuit.

AKTU 2016-17, Marks 10

OR
Give CMOS implementation of a SR fip-flop and explain its working.

AKTU 2017-18, Marks 05

AKTU 2019-20, Marks 07
OR
clocked SR flip-flop and explain its
Give CMOS implementation of a

working. AKTU 2018-19, Marks 07

Answer
4.14.1 shows gate level
A Clocked SR flip-flop using NAND gate: Fig.
circuit.
schematie of clocked NAND based SR lip-flop
R
CK

Fig. 4.14.1
B. CMOS Implementation:
clocked Sk flip-flop is shown in
1 A simpler implementation of a

Here, pass transistor logic is employed to implement the

Fig. 4.14.2.
clocked set-reset function.
DD

QP

Fig. 4.14.2. A simpler CMOS implemntation of the clocked

SR lip-lop
inverters and two pass
The SR flip-1lop comprising two cross-coupled
The pass transistors a r e turned ON when
the
transistors Q, andQ6they connect the flip-flop input S and R. The pass
and
clock 0) is high,
transistors act as transmission gates allowing the inputs S and R.
C. Operation:
=1 and Q =0, and
1. Consider the flip-flop output has the initial state Q
the input R = 1 and S = 0 is applied to the input of lip-flop.
and , are turned ON
2 When the clock ¢ is high, the transIstors ,
Integrated Circuits 4-19A (EC-Sem-5)

3. For this input R= 1 and S =0, the transistor is turned ON and pull
down the out put Q = 0.
These output Q is applied to the input of Q, and , transistors, this will

make the transistor @, is turned ON and the output Q becomes high.

5. Now consider the output has initial stateQ =0 and Q = 1, and the input
R= 0 and S =1. When the clock is high, the pass transistors Q, and
are turned ON. For this input R = 0 and S =1, the transistor Q, turned
ON and Q is turned OPF.
6. This causes the output Q =0 and Q is applied to the input of transistors
Q, and Q,. Now the transistor Q, turned ON and this make the output
i s high.
Que 4.16. Explain the mechanism of JK and Master-slave flip fop
with its working.

Answer
A JK lip-flop:
1 The circuit diagram of JK fip-flop is shown in Fig. 4.15.1.

CK-

Pig. 4.15.l.

In SR fip-flop S = R =l is not allowed so SR flip-flop has been overcome

by JK flip-flop. The truth table of JK fip-flop is shown below:
Truth Table:
Operation

No change i.e., q,

0
Reset
bf
Set
0 1

1 1
4-20 A (EC-Sem-5)
Digital Integrated Circuit Design
3. The working of JK
flip-flop is similar to SR
J=K=1, the output exists i.e., when J=K=1,ip-flop except that when
the output is 1, when its
previous output is '0' and '0' if its previous output is 1.
TheconditionJ= K=1anses amajor problemi.e., race-around
Consider J=K=1 and Q =0 and a condition.
5. After a time interval at
pulse is applied at clock (CK) input.
equal to
propagation delay through two NAND
gates in series, the output will change toQ=1. In other case if we have
J=K=1 and Q 1after another At time the
=
output will change back to
Q=0ie., the output will oscillate between 0 and 1.
At the end
of CR, the output is uncertain and the condition is race-around
condition.
There are two methods to avoid
race-around condition.
JK master
B.
slave
flip-flop. ii. Edge-triggered flip-flop.
Master-slave flip-flop :
1. This is the cascade network of two SR
flip-flop with feedback from the
output of the second to the inputs of the first.
The master-slave flip-flop is shown in Fig. 4.15.2.

CK

Fig. 4.15.2.
3. When CKis 1, the master is enabled and the
output Q, and ,m respondsS
to inputs (J and K) as shown in
truth table of JK flip-flop.
When CK is 0 then master is disable and slave is in
active mode and the
outputs Q and Q follows ,, and Q,m respectively.
5. In this circuit, the inputs to the R and S AND do not change
gates during the
clock pulse (CK), and therelore the race around condition does not exist.

Que 4.16. Sketch

properly labeled master slave D nip-flop
the

circuit and explain its operation with the help of

proper waveform
of the elock signal.
AKTU 2015-16, Marks 10
OR

Draw the D flip-lop using CMOS.

AKTU 2018-19, Marks 3.5
Answer

A Dlip-flop:
The D flip-flop has two nput8, data input D and a clock input ¢. The
complementary outputs are labeled as Q and Q.
 4-21 A (EC-Sem-5)
Integrated Circuits

m e m o r y or
reset state, and any
the flip-flop is in the
2. When clock is low, the state of flip-flop.
effect on
input line have
no
D the
changes on
is equal to D line just before
As clock goes high, 1lip-flop output edge triggered.
3.
such flip-flop is said to be
clock,
rising edge of the of D lip-flop is shown in
based circuit implementation
A CMOS
Fig. 4.16.l. feedback loop,
two inverters connected in positive low (o 0 and
The circuit consists of when the clock is
=

is closed at particular time

and the loop
1). the switch that
closes
connected to the flip-flop through
6. The input D is
when the clock is high.

DD DD

DO

Inverter-l Inverter-2

Fig. 416.1
the D input connected to input of
7. When ¢ is high, the loop is opened,
inverter l. to value of D,
node of inverter I is charged
8. The capacitance at input
to value of D.
while capacitance at input
node inverter 2 is charged the feedback
of
line is isolated from flip-flop,
9. When clock is low, the input to the value
latch requires the state corTesponding
loop is closed and the DD.
and providing an output Q
=

before o
of D just went down
B. Master-slaveD flip-flop: circuits a s shown in
pair of D tlip-tlop
1. The m a s t e r - s l a v e
consists
of t h a t two clock phases must be
Fig. 4.16.2. To emphasize
non-overlapping, we denote them by o, and d2

Do

2
Master Slave
Fig. 4.16.2.
4-22 A (EC-Sem-5)
Digital Integrated Circuit Design

Ln -Non-overlap
L.
interval

Fig. 4.16.3 Waveforms of the two-phase non-overlapping elock required.

2. When o, is high and o, is low, the input is connected to the-master
latch whose feedback loop is opened, while the slave latch is isolated.
3. Thus, the output Q remains at the value stored
slave latch whose loop is
previously in the
now closed. The node capacitances of master
latch are
charged to the
aPpropriate voltages corresponding to the
present value of D.
4. When o, goes low, the master latch is isolated from input data line D.
When o2 goes high, the feedback loop of the master latch is closed,
locking in the value of D. Further, its output is connected to
slave latch whose loop is the
now open.
The node capacitances in the slave are
appropriately charged so that,
when , goes high again, the slave latch locks in the new value ofD and
provides the output Q = D1.The D fip-flop has two inputs, data input D

and a clock input 6. The complementary outputs are labeled as Q and Q.

Que 4.17. Discuss D-F/F circuit using NAND CMOS gates.

AKTU 2017-18, Marks O5

Answer
1. Fig. 4.17.1 shows the circuit realization of Dflip-flop with CMOSNAND
gate. This circuit consists of two stages implemented by SR NAND latehes.

CLK

LO
D-

Fig. 4.17.1. A positive edge triggered D nip-lop.

 4-23 A (EC-Sem-5)
Integrated Circuits

and data
latchesthe left) processes the clock
2. The input stage (the two on
(the single
correct input signals for the output stage
Signals to e n s u r e
latch on the right).
of the input stage a r e high
3. If the clock is low, both the output signals
is unaffected and it stores
of the data input; the output latch
regardless
the previous state.

of the output
When the clock signal changes from low to high, only
one

low and set/resets the

voltages (depending on the data signal) goes
becomes low; if D= 1, the upper
output latch. IfD =0, the lower output
output becomes low.

the outputs keep their states

5. If the clock signal continues staying high,
regardless of the data input and force the output latch to stay in the
remains active while the
corresponding state as the input logical zero

clock is high.
store the data only while the
6. Hence the role of the output latch is to
clock is low.
The D latch is normally, implemented with transmission gate (TG
switches as shown in the Fig. 4.17.2.

CR VDD DI

D
CK
CK

CK

Fg,4172
8. Input D is accepted when CK is high. When CK goes low, the input is
open-circuited and the latch is set with the prior data D.
5 UNIT
Integrated Circuit
Timer

CONTENTS
Part-1: Integrated Circuit Timer:.. . 5-2A to 5-1IA
Timer IC 555 Pin and Functional
Block Diagram, Monostable and
Ast able Multivibrator using the
555 IC

Part-2 Voltage Controlled Oscillator :. 5-12A to 5-14A

VCO IC 566 Pin and Functional
Block Diagram and Applications

.5-14A to 5-21A
Part-3: Phase Locked L0op (PLIL):
Basic Principle of PLL, Block

Diagram, Working, Ex-OR Gates

and Multiplier as Phase Detectors,
Applications of PLL

5-1 A (EC-Sem-5)
5-2 A (EC-Sem-5)
Integrated Circuit Timer

Integrated
PART-1
Circuit Timer : Timer IC 555 Pin
and Functional
Block Diagram, Monostable and Astable
Multivibràtor using the 555 IC.
CONCEPT OUTLINE
The 555 timer is a
highly stable device for
generating accurate
time delay or oscillation.
Applications of 555 timers include pulse generator, ramp and
square wave generator, monostable multivibrator, burglar alarm
etc.

Questions-Answers
Long Answer Type and Medium Answer 1ype Questions

Que 5.1.Draw and explain the block diagram of IC 555.

AKTU 2017-18, Marks 05

OR
Draw the functional block diagram of IC 555 and explain its working.
AKTU 2018-19, Marks 3.5
Ans
1. In the stable state, the output Q of the flip-flop (FF) is high. This makes
the output low because of power amplifer which is basically an inverter.
2 If negative going trigger pulse is applied to pin 2 and should have its DC
level greater than the threshold level of the lower comparator (i.e..
Vcc/3), now the trigger passes through (Vcc/3), the output of the lower
comparator goes high and sets the FF (Q=1,Q=0). Therefore the
output of IC 555 becomes high.
3. When the threshold voltage at pin 6 passes through (23) Vc, the output
ofthe upper comparator goes high and resets the PF (Q=0,=1).

The reset input (pin 4) is used to resot the FP and the flip fop output
becomes high and the output of IC 666 becomes low beceause the output
of FF is 1.
 5-3A (EC-Sem-5)
Integrated Circuits

Re
4
5 k?

Threshold
TVcc
Control
Control
FF

Trigger
kS2

Power
Output
Discharg 3
amp
R

5.1.1. Functional diagram of IC 555.

Fig.

Draw the ofIC 555 and explain the function

Que 5.2. pin-diagram
of each pin.

Answer
1. Fig. 5.2.1 shows the pin-diagram of 8-pin DIP 555 timer.

Ground (1) (5)+ Vcc

Trigger (2) (6) Discharge

555

Output (3) Y (7) Threshold

( 8 ) Control voltage
Reset (4)
Fig. 6.2.1.
5-4A (EC-Sem-5)
Integrated Circuit Timer
Funetionn:
1. Ground: All the voltages measured with respect to this terminal.
are

2. Trigger: The output of the timer is controlled by this pin. The output is
low if the voltage is
greater than 2/3 Vcc. Por negative going pulse of
amplitude larger than l/3 Vcc is applied to this pin, the comparator II
output goes high, which in turn makes the output high as long as the
trigger terminal has a low voltage.
3. Output: The complementary signal out of the flip-flop
output stage and becomes the output of the timer.
goes through an

4 Reset: This pin is

connected to supply i.e., +Vcc in order
false triggering. Generally pin 4 is not used.
to avoid any

5 Supply +Vcc: The 555 times works with supply voltage +5 V to +18 V
with respect to ground.
& Discharge: A capacitor is connected externally to the ground at this
pin. Internally the collector of the discharge transistor is coming at this
pin. A high Q output from the flip-flop makes the transistor OFF, i.e.
open cireuit and external capacitor charges at a rate determined by
external RC network. When output Q is low, transistor gets saturated
and external capacitor discharges.
7. Threshold: When voltage is greater than or equal to 2/3 Vcc. the
output of comparator I goes high which makes the output of the timer
low.

Control voltage : The pulse width of output waveform can be varied

by imposing a voltage at this pin. In most applications this pin is not
required and a capacitor is connected to this pin and ground to prevent
noise introduction in the circuit.

Que 53. What are different modes of operation of IC 555 ? Draw

the circuit diagram of a delay circuit using 565. What is maximum
delay that can be provided with 555 with a capacitor of 1000 F?

Answer
A Modes of operation of IC 555: The timer (555) can operate in two
modes:

Amonostable (one-shot) multivibrator

A n astable (free running) multivibrator.
Integrated Circuits 5-5 A (EC-Sem-55)

B. Circuit diagram:
+Vcc
+Vcc

0 Output

Nc 555

Voc R

0.01 uF

Fig. 5.3.1 Astable multivibrator using 555 timer.

C. Numerical:
Given: C 1000 uF
To Find : Maximum delay.

1. The totalperiod of output wavetorm is

T=t+a=0.69 (R, + 2R,)C
2. For maximumn delay, it is
given that
C= 1000 uF and
T
we
assume R, R, 1
0.69 (1 KN + 2 x 1 KN) 1000 x 10-
= KQ
=
0.69 (3 k2) x 10 x 10-5
0.69 x 3 = 2.07
sec
So, the maximum delay is 2.07 seconds.

Que 54.Draw the functional

block diagram of IC 555 and explain
its working. Draw the circuit diagram of a monostable multivibrator
using 555 and find expression for
quasi state period.
AKTU 2018-19, Marks 07
OR
Explain the block diagram of IC 555. Derive the
monostable multi-vibrator using 555. expression
delay of a
for time

AKTU 2019-20, Marks 0

Answor
A Functional block diagram IC 555: Refer Q.5.1,
Page 5-2A, Unit-5.
 Integrated Circuit Timer
5-6 A (EC-Sem-5)

B. Monostable multivibrator using IC 555:

1. Fig. 5.4.1 shows a monost able muitivibrator implemented using the

555 1C together with an external resistor R and an external

capacitor C.

In the stable state the flip-flop will be in the reset state, and thus its

transistor , will be
output will be high, turning ON transistor Q,.
a low level at the
saturated, and thusv, will be close to 0 V, resulting in
output of comparator 1.

CC

Comparator 1

R Q
Flip-flop
Compara S J

Urigs
100
Q W

555 timer connected to implement a

Fig. 5.4.1. The
monostable multivibrator.

terminal, labeled vtricger is kept high

3. The voltage at the trigger input 2 also will be low,
and thus the output comparator
greater than VT),
reset state, Q will be low
and thus v, will be
Since the flip-flop in the
closed to 0DV.
monostable multivibrator, a negative input pulse is applied
5. Totrigger the the output of
trigger input
to the
terminal. As Urigger below VTL goes
of
to level, thus setting the tlip-tlop. Output
comparator 2 goes high
high, and output Q goes low,
high, and thus v, goes
the flip-flop goes

turning OFF transistor

R, and its voltage
6. Capacitor C now charge up throughin resIstor
begins to
5.4.2the monostable
Fig.
rises exponentially toward Vcc as shown
state.
m u l t i v i b r a t o r i8 n o w
in its quasi-stable
 5-7A (EC-Sem-5)
Integrated Circuits

of comparator 1, VTH
7. This state prevails until v, reaches the threshold
1 goes high, resetting the
at that time the output of comparator

flip-flop. turns ON transistor

now goes high and
8. Output Q of the fip-flop
trigger

VL

Vcc

VTH

cc

Fig. 5.4.2. Waveform of the circuit.

C, causing v, to go to
9. In turn, transistor Q, rapidly discharges capacitor
OV. Also, when the flip-flop resets its Q, output goes low and thus v,
multivibrator is now back in its stable
V. The monostable
goes back to 0
state and is ready to receive
a new triggering pulse.
the time interval that the monostable
10. The width of the pulse, T, is determined
quasi-stable state; it can be
in the by
multivibrator spends is
reference to the waveforms in Fig. 5.4.2
at which the trigger pulse
waveform of ve. can be expressed as
applied as t 0, the exponential
=

,Vcc1-e-iCR)

Substituting =TH catt T

T= RC In 3 = 1.1 RCC

where, T= Time delay

duty eyele and
Derive the expression for time delay,
Que 5.5. multivibrator.
oscillation for astuble
frequency of
5-8A (EC-Sem-5) Integrated Circuit Timer

Answer
The circuit using 555 timer in astable mode or in free running is shown
in Fig. 5.5.1.
2. The cireuit does not require external trigger to change the state of the
output and hence is also called free-running multivibrator.

1+Vcc
8 4
7

R3 2 555

Fig. 5.5.1
3. Pin 2 to pin 6 of timer 555 are shorted, it to work as a free-running
multivibrator. When the voltage across capacitor, Vc equals 2/3 Vcc
comparator-1 trigger the flip-flop inside the timer and the output goes
low as shown in Fig. 5.5.2.

Vc
Charging
Voc Discharging

2/3Vcc

1/3Vcc --. --. .

- -

Fig. 5.5.2.

4. At this point the C, starts discharging through R, and transistor inside

the timer. As soon as voltage V. equal /3 Vee comparator II output
triggers the flip-tlop and the output goes high. This cycle goes on repeating.

5. The external capacitor C, charges through R, and R, and discharges

through R, only. So. the duty eycle is set by the ratio of these two
resistances. The C, charges and discharges between 2/3 V., and 1/3 V
respectively.
 5-9 A (EC-Sem-5)
Integrated Circuits

to 23 is
6. The time during which the capacitor charges from
1/3 Ve V
equal to the time the output is high and given by
0.693 (R, +R,C,
discharges from 2/3 Vto
7. Similarly the time during which the capacitor
V3 V is equal to the time the output is low and is given by

4= 0.693 R, C,
8 Hence the total period of output waveform is
T + = 0.693 (R, +2R,)C
ratio of time in the high state to the total period T
9. The duty cycle is the
and is given by
(R+R)
Duty cyele T (R, +2R,)
10. The frequency of oscillation is given by,

T 0.6930R, +2R,C,
1.44
R 2R,C
Que 5.6. Draw the functional block diagram of IC-555 and explain

555 timer as an astable multivibrator with an

its working. Design a
output signal timer frequency of 700 Hz and 60 % duty cycle.

ARTU 2016-16,Marks10
Answer
A Functional bloek diagram and working of IC 555: Refer Q. 5.1,
Page 5-2A, Unit-5.
B. Numerical:

700 Hz
Given: Duty cycle, D
timer
=
60 %=0.6;
astable
Frequeney,f=
multivibrator.
To Design:555 as an

1. Assume, C 0.01 uF

2. We know, D= + R
+2R,
0.6 R+R ...(5.6.1)
+2R,
3. Also,
1.44
TR+2,C
0.01 10*
1.44
T R, +2R,
5-10 A (EC-Sem-5) Integrated Circuit Timer

R,+ 2R2 1.44 x 10 = 2x 10" N (5.6.2)

7
4. Substituting this value from eq. (5.6.2) in eq. (5.6.1)

0.6 R
2x110
12x 10 =
R, +R, 5.6.3)
Rg = 80 ksn
R = 40 kN

5. The circuit is shown in

Fig. 5.6.1.
O+5V

R 40 k
3-o Output
80 k
R22
0.01
0.01

Fig. 5.8.1.

Que 5.7. Design a 555 timer as astable multivibrator giving its

block diagram which provides an output signal frequency of 2 KHz
and 75 duty cyele. AKTU 2017-18, Marks 05
Answer

Given : Frequency, f 2 KHz, Duty cycle, D = 75 %

To Design:555 timer as an astable multivibrator.
1. We know, T 10 0.5 ms

D-
TON = 0.5 x 0.75 = 3.75 x 10- sec

ToP= T-ToN 1.25 x10-see

2. Duty cycle is more than 50 % hence modified circuit must be used.

3 The modified circuit is shown in Fig. 5.7.1.

4. Let C= 0.01 uF
 5-11A (EC-Sem-5)
Integrated Circuits

R, and diode D while discharging

The charging of C takes place through
takes place throughR, only
ON 0.693 R,C
ne oFF0.693 R,C
- 0 +Vcc

3- Output
DR

L 0.01uF
Fig. 5.7.1.
and C,
5. Using values of FON oPp
R, =
8.658 k2
20.202 kn
and R, =

Que 5.8.
For 555 astable multivibrator RA
= 4.7
k0, Ra =1 kQ and
C 1 uF. Determine the positive pulse width, the negative pulse
What is the duty eycle of
width, and the free-running frequeney.
output waveform ? AKTU 2016-17, Marks 10
Answer

Given:RA =4.7 KN, R, = 1 KS2, C 1u

To Find: Duty eycle, D.

1. Positive pulse width,

0.69 RA +RpC
= 0.69 (4.7 K2 +1 K2) ( 1 0 - ) = 3.933 ms

2. Negative pulse width,

a0.69(R,)C
0 . 6 9 (1 KQ) (10-°) = 0.69 ms

3. Free-running frequeney,
= 0.216 KHz

L (3.933+0.69K10 )
4 % Duty cycle = - x 100 3.933 x100 = 85.07 o
(3.933+0.69)
5-12A (EC-Sem-5)
Integrated Circuit Timer

PART-2|
Voltage Controlled Oscillator: VCo IC 566 Pin and Functional
Block Diagram and Applications.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 5.9. Explain the operation of VCO with help of functional

block diagram. Also show the
pin-diagram of VCO.
Answer

The pin configuration and the basic block diagram of IC 566 VCO are
shown in the Fig. 5.9,.1(a) and (b)
respectively. The frequency of oscillation
is determined by an externally connected resistor
R, and a capacitor C
2. The control voltage or the
modulating input is
v, applied at the control
terminal (pin 5).
3. The triangular voltage obtained at pin 4 is shown in Fig. 5.9.2(c). It is
generated by alternately charging the capacitor C, by one current source,
and discharging it linearly through another current sOurce. The
amount
of charge and discharge voltage
swing is determined by the Schmitt
trigger.
4. The Schmitt trigger also provides the square-wave output at pin 3
through the power amplifier Ag and the triangular output is available at
pin 4 through the buffer amplifier A,
Operation of VCO :
1. The output voltage swing of the Schmitt trigger is set to the levels
and Vcc
0.5Vcc. In Fig. 5.9.2, if R, R, in the positive feedback path, the
=

voltage at the non-inverting terminal of Op-Amp A2 swings from

0.5 to 0.25
Vcc Vcc
During charging of C, when the
voltage
across just exceeds 0.5 Vcc
the Schmitt trigger switches to LOw (0.5 Vcc) and the capacitor starts
discharging.
3 When the voltage across C, reduces to 0.25 Vcc the Schmitt trigger
switches to HIGH (Vc)
4 By maintaining the source current and sink current of the two current
sources equal, a uniform triangular voltage with equal positive and
negative slopes is obtained at pin 4.
 5-13 A (EC-Sem-3)
Integrated Circuits

Ground

NC 2SE566 C
Squarenut
wave output 3
vco 6 R
Modulation
Triangut 4
wave output
input

(a) Pin diagram

9+cc

Constant
current
source
Modulating sink
input, Ve fferSchmitt
Buftertrigger
A
Inverter
(Power Amp.)

(b) Basic block diagram

Out

+V 12 volts

+4

TH

+
UL
(c) Output wavetorms

oscillator.
Fig. 5.9.1. Voltage controlled
buffered is
of Schmitt trigger, inverted and
5. The square-wave output
available at pin 3.
3 and 4 are shown in Fig. 5.9. 1(c).
6. The waveforms at the output pins
oscillator in brief. Also write
Que 5.10. Discuss voltage controlled

its applications.
 5-14 A (EC-Sem-5)
Integrated Circuit Timer

Answer
A VCO: Refer Q. 5.9,
B.
Page 5-12A, Unit-5.
1.
Applications :
Frequency modulation.
The various
application of VCO are :

2. Signal generation (Triangular or

3. Function generation. square wave)
4.
5.
Frequency
In
shift
keying i.e. FSK demodulator.
trequency multipliers.
6. Tone generation.

Phase Locked Loop (PLL) : Basic

PART-3
Principle of PLL, Block Diagram,
Working, Ex-OR Gates and Multiplier as Phase Detectors,
Applications of PLL.

Questions-Answers
Long Answer Type and Medium Answer Type Questions

Que 5.11.| Explain the types of phase detectors with suitable

circuit diagrams and input-output waveforms.
AKTU 2016-17, Marks 10
Answer
Phase detectors comparators
or used in PLL be
A Analog phase detector:
a can
of two types
1. Fig. 5.11.1 shows a switch type phase detector. Here, switch is an electronic
switch which is being opened and closed by the VCO output
2. Switch is closed only when VcO output is
signal.
positive and switeh is
open for
negative VCO output.
Electronic switch

Input
Signal (Vf) rOr voltage

Signal from
VcoVo, o)
Fig. 5.11.1.
3. Fig. 5.11.2 shows the input signal V, at the sanme frequency f, but at
different phase shifts = 0°, 90° and 180°.
4. Por V, having 4 = 0", a positive error voltage will be produced.
 5-15A (EC-Sem-5)
Integrated Circuits

produced at the switch

5. When = 90°, the average value error voltage of appear
is zero and when 180", only the
=
negative half cycles of input
thus error voltage is negative.
across the output,
6. Error voltage is zero for o = 90°, hence perfect lock thus, VcO output
should be 90° out of phase.
and input signal V,
VCO output
voltage V 1

InputtV, Positive
with = 0° error

voltage
Input V Zero error
with= 90 voltage

Negative
InputtV,
with = 180°
error
voltage
Fig. 5.11.2. I/O waveforms of phase detector
B. Digital phase detector:
detector is a
simple XOR gate. XOR gate output is high
1. A digital phase
only if one of its inputs is high.
2. The two inputs of the gate are connected to the input signal (V,f) and
output signal (V,T,) respectively.

L
Output- e
UL
Fig. 5.11.3.
3. Output will increase with increase in the phase difference
4. For 0 ° the waveforms at inputsf, and f, overlap and output is always
zero. Therefore, the average error voltage will be zero. It will be maximum
for = 180°.
5. Thus, in this phase detector, phase must be zero for zero error voltage
ie., for perfect lock condition.

Que 5.12. Write a note on Ex-OR as a phase detector.

AKTU 2018-19, Marks 3.5

5-16A (BEC-Sem-5))
Integrated Circuit Timer

Answer
1. The Exclusive-OR
phase detector is shown in Fig. 5.12.1. The output of
Ex-OR gate circuit is
high only when any one of the two input
namely f, or
f, is high. signals,

Fig. 5.12.1.
Exclusive-OR phase detector
2. The input and
output waveform for f, f, are shown in
digital phase detector, the phase error o is defined as Fig.
=

a 5.12.2. In

2 T7
where T is the
period of input signals
frequency of same and t is the
time difference between the leading
3. edges of the two signals.
Fig. 5.12.2 shows that /,leadsf, by o degrees and the
of the Ex-OR gate is a function of the DC output voltage
phase error between the two
inputs.
4. Ex-OR phase detector can be realized using ICs such as CD4070. The
output DC voltage depends on the duty cycle of the
input waveforms.
Therefore, this type of phase detector is employed when the waveforms
of
f, and , are of square waveform with 50 % duty
cycle.

VaeOutput

Fig 5.12.2. Input and output

wavefroms
Que 6.13. Explain the working of PLL with suitable block
diagram.
Write down the different applications of PLLL

OR
AKTU 2016-17, Marka 10
Draw the block diagram of PLL and
explain its operation. Explain
lock-in range, capture range and pull-in time of a PLL. List
the
applications of PLL.
AKTU 2017-16, Murka 10
OR
AKTU 201.0, Marka 0
Explain the working of PLL with suitable block diagram.

AKSTU 2018-19, Marka 3.5

 5-17A (EC-Sem-5)
Integrated Circuits

Answer
PLL:
A Principle of operation ofdetector comparator are the input voltage
The two inputs of the phase
or
1. controlled
at frequency 1, and the feedback voltage from a voltage
V,
oscillator (vcO) at frequency o
2. The phase detector compares these two signals and produces a DC
voltage V, which is proportional to the phase difference betweenf, and

3. The output voltage V, phase detector is called as error voltage.

of the
to low-pass filter.
This error voltage is then applied
the high frequency noise present
in the phase
Low-pass tilter removes
DC level.
detector output and produces a ripple free
level by the amplifier and
5. This DC level is amplified to an adequate

6.
applied toa VCo.
The DC amplifier output voltage is called as the control voltage Vc-

Phase Lowpass Amp

detector filter

vo Fig. 5.13.1. Block diagram of PLL

is applied at the input of a VCO. The output
7. The control voltage Vc
frequency of VCO is directly proportional to the DC control voltage Ve
8. TheVCO frequency f, is compared with the input frequency ,
by the
until it is equal to the
phase detector and it is adjusted continuously
input frequencyf, i.e.. f, =1
in direction to reduce the
Once, the action of shifting VCO frequency
a
9.
starts, we say the signal is in the
frequency difference between /, andf,
capture range.
10. When the output frequency is exactly the same as the input frequency,
PLL is then said to be locked.
11. Once locked the output frequency f, is identical to f, except for a finite
phase difference.

generates a control voltage Vc to shift VCOD

12. This
phase difference Once locked, PLL
frequency from /, to f, thereby maintaining the lock.
tracks the frequency changes of the input signal.
B. Lock-in range: Once the PLL is locked, it can track the frequency
changes in the
incoming signals. The range ot frequencies over which
the PLL can maintain lock with the incoming signal is called lock-in
range or tracking range.
C. Capture range: The range of frequencies over which the PLL can
acquire lock with an input signal is called the capture range.
5-18 A (EC-Sem-5)
Integrated Circuit Timer
D. Pull-in time: The total time taken
by the PLL to establish lock is called
pull-in time. Thisdepends on the initial phase and
between the two signals as
frequency difference
well as on the loop gain and
characternstics. loop
filter

Applications:
1. Frequency divider
2. Frequency multiplier
3. Frequency synthesizer 4. AM detector
5. FM detector FSK demodulator.

Que 5.14.Draw the functional block diagram of PLL IC. Explain

its working and deduce the
range of signal that can be locked.
expression for maximum frequency

Answer
A Functional block diagram:
+cc
10
Input 2 Phase Error WT
3.6 ka 7 TDemo-
dulated
Input detector or
cOmparator
amplifier
uphier output
Phase Reference
comparator 5
VCO input - output

UL4
VCO output Vco +

Vcc Vcc
Fig. 5.14.1. Functional block diagram of PLL-565.
Workingg:
It may be seen that phase locked loop is internally broken between the
VcO output and the phase
comparator input.
2. A short circuit between pins 4 and 5 connects the VCO output to the
phase comparator so as to compare f, with input signal f
3. A capacitor C' is connected between pin 7 and pin 10(supply terminal) to
make a low-pass filter with the internal resistance of 3.6 KO. This
capacitor should be large enough to eliminate the variations in the
demodulated output at pin 7.
B. Derivation of lock-range:
1 Assume radian is the phase difference between the input signal and
the VCO voltage. Then the output voltage v, of the analog phase detector
1s given by

Kl ..5.14.1)
 5-19A (EC-Sem-5)
Integrated Circuits

where K is the phase angle-to-voltage transfer coefficient of the phase

detector.
2. Therefore. the control voltage to VCO is

..(5.14.2)
,AKl
where A is the voltage gain oftheampliier
3. This control voltage v, shifts VCO frequeney from its free running
irequeney Io to a trequencyf represented by
...(5.14.3)
where K, is the voltage to frequency transfer coefficient of the VCO.
When PLL achieves lock with signal frequency f, we have
f=fo+ Rgv
5. From eq. (5.14.2) and eq. (5.14.3) we get

Therefore,
2 K,K,A
6. The maximum output voltage magnitude available from the phase
detector occurs for o =r and 0 radian and

etmax)+ K,
2
7. Then, the corresponding value of the maximum control voltage available
to drive the VCO is given by

rtmax ) KA
8. The maximum VCO swing in frequency that can be achieved is given by

-fomas= K* emas= KgK,A ...5.14.4)

9. Therefore,the maximum range of signal
frequencies over which the
PLL can remain locked will be

10. The lock-in

frequency range is 24/, and from eq. (5.14.4) it is given by
Lock-in range = 24L = KKAr = K,t
.5.14.5)
where KKA =
K, is the loop bandwidth.

11.
or,

The lock-in range is

f,KKAl)-x.
symmetrically
( located with
running frequency I% of VCo. For IC PLL
respect to the free
665, we have
K= V
where
V=+Vcc--Vcc)
5-20 A (EC-Sem-5)
Integrated Circuit Timer

12. For PLL,

and = 1.4
Hence, from eq. (5.14.5) the lock-in
range becomes
7.8fN
Que 5.15. Explain the application of PLL as frequeney multiplier
with suitable circuit diagram.

Answer
1. Adivide by N network is connected externally between VCO output and
phase comparator input as shown in Fig. 5.15.1.
2. Since the output of the divider network is locked to input frequency f,
VCO actually operates at frequeney which
a
is N times higher thanf.
f,=fJN

Phase
Input LPF Amplifier
comparator

T/N
Network VCO
(Freq. divider)
PLL
Output
Fig. 5.16.1.

Que 5.16.| Describe PLL application as frequeney translator.

Answer
1. A schematiefor shifting the frequency of an oscillator by a small factor
i5 shown in Fig. 5.16.1.
2. The signalf, which has to be shifted and the output frequency , of the
VCO
are applied as inputs to the mixer.
3.
The output of the mixer contains the sum and difference of f, and /
However, the output of LPFcontains only the difference signal ,-/,).
The translation or offset frequeney 7 / «/,) is applied to the phase
comparator.
When PLIL is in locked state,

f.=,
Thus, it is possible to shilt the incoming frequeney/, by /
Integrated Circuits 5-21A (EC-Sem-5)

Phase
Input
ulapne compirato Amplifer
Offset freq
VCO

Outpu PLL

5.16.1. PLL used as a frequency translator

Que 5.17. Determine the free running frequeney f. and the lock
range, fL and the
R, =12 K, c, = 0.001
capture range, fe for PLL 565 having
uF, C, = 10 uF, C, 0.001 uE, Vec= 10V. Show
the graphical representation of relationship between lock
frequency, capture frequeney and free running frequeney.

Answer

Given R, = 12 Ka, C, = 0.001 uF, C, = 10 uF, C, =0.001 juF,

Vcc 10 v.
To Find: ffle

1.Z
1 Free running
Irequeey io
4 R.C,

1.2 25 KHz
4 x 12 10" x 0.001 x
10
2. Lock range,
z=:20 I: Vec =10-- 10) V
= 9.76 KHz
1/2

3. Capture range,
f 23.610C,
9.75x10 199.47 Hz
2nx3.6x 10 x 10 10"
Lock range

Capture range-

15.25 K 24.801 K 25K 26.199K 34.75 K

Fig. 5.17.1