Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

MODULE-5
INTRODUCTION TO VERILOG
Verilog Behavioral description: Highlights of behavioral description, Structure of behavioral description,
Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description
of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog) of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural description,
Structural description of ripple carry adder.
(Section4.1 to 4.2 of Text 3)

Behavioral Description highlights

The behavioral description is a powerful tool to describe the systems for which the digital logic
structures are not known or hard to generate. Examples of such system are complex arithmetic
units, computer control units, and some biological mechanisms. In dataflow modeling a system
was described by using logic equations. In behavioral modeling a system is described by showing
how the outputs behave according to the changes in inputs. In this style of description (modeling),
it is not necessary to know the logic diagram of the system, but we must know the behavior of the
outputs in response to the changes in the inputs. In Verilog, the major behavioral-description
statements are always and initial.
Structure of Verilog Behavioral Description
A simple example of HDL code describing a system (half_add) using behavioral description is
shown below. Usually sequential statements such as IF or Case are used to describe the change of
the output.Here, the name of the module is half_adder. It has two inputs a and b, two outputs S and
C. Any signal declared as output should be declared as a register (reg).Therefore sum and carry are
declared as registers.
module half_adder(a,b,sum,carry);
input a,b;
output reg sum, carry;
always @ (a,b)
begin
case({a,b})
2’b00:begin
sum=1’b0;

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 1
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

carry=1,b0;
end
2’b01:begin
sum =1’b1;
carry =1,b0;
end
2’b01:begin
sum =1’b1;
carry =1,b0;
end
default: begin
sum =1’b0;
carry =1,b1;
end
endcase
endmodule

Sequential Statements

There are several statements associated with behavioral descriptions. These statements have
to appear inside inside always or initial in Verilog.
IF Statement

Syntax

if (Boolean Expression)
begin
statement 1;
statement 2;
statement 3;
.......
end
Note: begin and end can be omitted if there is only statement

Example:
if (clk == 1)
temp = s1;

IF-ELSE Statement
Syntax

if (Boolean Expression)
begin statement 1;
statement 2;
statement 3;
.......
end

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 2
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

else
begin
statement a;
statement b;
statement c;
.......
end

Example:

if (clk == 1’b1) // 1’b1 means 1-bit binary number of value 1.

temp = s1;
else
temp = s2;

ELSE-IF statement

Syntax

if (Boolean Expression1)
begin
statement1;
statement2;
.....
end
else if (Boolean expression2)
begin
statementi;
statementj;
.....
end
else
begin
statementa;
statementb;
....
end
Example:

if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 3
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

Example: BEHAVIORAL DESCRIPTION OF A 2x1 MULTIPLEXER WITH TRI-

STATE OUTPUT

HDL Description of a 2x1 Multiplexer Using IF-Else

module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y;
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 1)
Y = 1’bz;
else
begin
if (SEL)
Y = B;
else
Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 4
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

Y = A;
end
end
endmodule
HDL Description of a 2x1 Multiplexer Using Else-IF
module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y;
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 0 & SEL == 1)
Y = B;
else if (Gbar == 0 & SEL == 0)
Y = A;
else
Y = 1’bz; //Y is assigned to high impedance
end
endmodule

Case Statement
The case statement is a sequential control statement. It has the follow ing format:
syntax
case (control-expression)
test value1 : begin statements1; end
test value2 : begin statements2; end
test value3 : begin statements3; end
default : begin default statements end
endcase
Example:
case (sel)
2’b00 : temp = I1;
2’b01 : temp = I2;
2’b10 : temp = I3;
default : temp = I4;
endcase

Example: BEHAVIORAL DESCRIPTION OF A 4x1 MULTIPLEXER

module mux_4_1(I,SEL,Y);
input[3:0]I;
input[1:0]SEL;
output Y;
reg Y;
always@(I,SEL)
begin
case (SEL)
2’b00 : Y = I[0];

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 5
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

2’b01 : Y = I[1];
2’b10 : Y = I[2];
default : Y = I[3];
endcase
end
endmodule
Example: BEHAVIORAL DESCRIPTION OF A 8x1 MULTIPLEXER
module mux_8_1(I,SEL,Y);
input[7:0]I;
input[2:0]SEL;
output Y;
reg Y;
always@(I,SEL)
begin
case (SEL)
3’b000 : Y = I[0];
3’b001: Y = I[1];
3’b010 : Y = I[2];
3’b011 : Y = I[3];
3’b100 : Y = I[4];
3’b101 : Y = I[5];
3’b110 : Y = I[6];
default: Y = I[7];
endcase
end
endmodule

Verilog casex and casez

Verilog has another two variations of case: casex and casez. casex ig nores the “don’t care”
values of the control expression, and casez ignores the high impedance in the control
expression.
For example, in the code
casex (a) 4’bxxx1: b = 4’d1;
4’bxx10: b = 4’d2;
………………..
endcase;
all occurrences of x are ignored; b = 1 if and only if the least significant bit of a (bit order 0)
is 1, regardless of the value of the higher order bits of a, and b = 2 if the bits of order 0 and 1
are 10, regardless of the value of all other bits. For the Verilog variation casez, all high-
impedance values (z) in control expressions are ignored.
Example:

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 6
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

casez (a) 4’bzzz1 : b = 4’d1;

4’bzz10 : b = 4’d2;
………………..
endcase;
b = 1 if and only if the least significant bit (bit of order 0) of a = 1, and b = 2 if bit 0 of a = 0
and bit 1 of a = 1.
VERILOG DESCRIPTION OF A PRIORITY ENCODER USING CASEX
A priority encoder encodes the inputs according to a priority set by the user, such as when the
input represents interrupt requests. If two or more interrupt requests are issued at the same
time by the devices needing service, and the central processing unit (CPU) can only serve
one device at a time, then one of these requests should be given priority over the others and
be served first. A priority encoder can handle this task. The input to the encoder is the
interrupt requests, and the output of the encoder can be memory addresses where the service
routine is located or an address lead ing to the actual address of the routines. Table shows the
truth table of a four-bit encoder; bit 0 of input a has the highest priority. Listing 3.11 shows
the Verilog description for a four-bit priority encoder. Below Figure shows the simulation
waveform.
Table: Truth Table for Four-Bit Encoder

Verilog Description for a Four-Bit Priority Encoder Using casex

module Encoder_4 (Int_req, Rout_addrs);
input [3:0] Int_req;

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 7
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

output [3:0] Rout_addrs;

reg [3:0] Rout_addrs;
always @ (Int_req)
begin
casex (Int_req)
4’bxxx1 : Rout_addrs=4’d1;
4’bxx10 : Rout_addrs=4’d2;
4’bx100 : Rout_addrs=4’d4;
4’b1000 : Rout_addrs= 4’d8;
default : Rout_addrs=4’d0;
endcase
end
endmodule

Figure: Simulation waveform of a four-bit priority encoder.

The Loop Statement
Loop is a sequential statement that has to appear inside always or initial in Verilog. Loop is
used to repeat the execution of statements written inside its body. The number of repetitions
is controlled by the range of an index parameter. The loop allows the code to be compressed;
instead of writing a block of code as individual statements, it can be written as one general
statement that, if repeated, reproduces all statements in the block. There are several ways to
construct a loop. Some of those ways are discussed here.
for-Loop
The HDL general format for a For-Loop is:
for <lower index value> <upper index value> <step>
statements1; statement2; statement3; ….
end loop

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 8
 Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

If the value of index is between lower and upper, all statements writ ten inside the body of
the loop are executed. For each cycle, the index is modified at the end loop according to the
step. If the value of index is not between the lower and upper values, the loop is terminated.
Example:
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1)
begin
result = result + 2**i ;
end
end
statement1; statement2;
....
While-Loop
The general format of the While-Loop is:
while (condition)
Statement1;
Statement2;
…………
end
Example:
while (i < x)
begin
i = i + 1;
z= i*z ;
end
Verilog repeat
In Verilog, the sequential statement repeat causes the execution of statements between its
begin and end to be repeated a fixed number of times; no condition is allowed in repeat.
Example:
repeat (32)
begin
Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 9
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

#100 i = i + 1;
end
Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common use for forever is
to generate clocks in code-oriented test benches.
Example:
initial
begin
Clk = 1’b0;
forever #20 clk = ~clk;
end
Calculating the Factorial Using Behavioral Description with WHILE-LOOP
The factorial of N is (N!) = Nx(N-1)x(N 2)x(N-3)x ….x1.
For example, 4!=4×34×24×1=24.
Verilog Description
module factr (N, z);
input [5:0] N;
output [15:0] z;
reg [15:0] z;
integer i;
always @ (N)
begin z = 16’d1;
i = 0;
while (i < N)
begin
i = i + 1;
z=z*i;
end
end
endmodule

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 10
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

Structural Descriptions
Highlights of Structural Description
Structural description is best implemented when the digital logic of the details of hardware
components of the system are known. An example of such a system is a 2x1 multiplexer. The
components of the system are known: AND, OR, and NOT gates. Structural description can
easily de scribe these components.
Facts
 Structural description simulates the system by describing its logical components. The
components can be gate level (such as AND gates, OR gates, or NOT gates), or
components can be in a higher logical level, such as register-transfer level (RTL) or
processor level.
 All statements in structural description are concurrent. At any simulation time, all
statements that have an event are executed concurrently.
 In Verilog structural description by primitive gates such as AND, OR, XOR, NOT,
and XNOR gates.

Organization of Structural Description

The following HDL code describes a half adder using structural description.
HDL Structural Description of a Half Adder
module system (a, b, sum, cout);
input a, b;
output sum, cout;
xor X1 (sum, a, b); / X1 is an optional identifier; it can be omitted./
and a1 (cout, a, b); / a1 is optional identifier; it can be omitted./
endmodule
Verilog has a large number of built-in gates. For example, the statement:
xor X1 (sum, a, b);
describes a two-input XOR gate. The inputs are a and b, and the output is sum. X1 is an
optional identifier for the gate; the identifier can be omitted as:
xor (sum, a, b);

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 11
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

Verilog has a complete list of built-in primitive gates. The output of the gate sum has to be
listed before the inputs a and b. Figure shows a list of gates and their code in Verilog.

Figure: Verilog built-in gates.

Structural Description of a Three-Bit Ripple-Carry Adder
Verilog Description
module three_bit_adder (x, y, cin, sum, cout);
input [2:0] x, y;
input cin;
output [2:0] sum;
output cout;
wire [1:0] carry;
full_adder f0 (x[0], y[0], cin, sum[0], carry[0]);
full_adder f1 (x[1], y[1], carry[0], sum[1], carry[1]);

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 12
Module-5 DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)

full_adder f2 (x[2], y[2], carry[1], sum[2], cout);

endmodule
module full_adder ( a ,b ,c ,s ,co );
output s ;
output co ;
input a,b,c ;
assign s = a ^ b ^ c;
assign co = (a&b) | (b&c) | (c&a);
endmodule

Dept.of ECE, RIT, Hassan Prepared by: Mr. Ravi L.S Page 13