Name: Sneh Patel
Registration no: 22BCI0092
Course code: BEEE102P (L35 + L36) Faculty Name:
Dr. Nawaz Shafi
Experiment 3: Simulation of a half-adder
circuit
The half adder adds two single binary digits A and B. It has two outputs, sum
(S) and carry (C). The carry signal represents an overflow into the next digit of
a multi-digit addition. The half-adder design incorporates an XOR gate for S
and an AND gate for C. The Boolean logic for the sum (in this case S) will be
A′B + AB′ whereas for the carry (C) will be AB
INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Simulation diagram:
Transient simulation with 80ms stop time.
Simulation results:
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Experiment 4: Simulation of a full-adder
circuit
A full adder adds binary numbers and accounts for values carried in as
well as out. A one-bit full-adder adds three one-bit numbers into carry
and sum values.
INPUT OUTPUT
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simulation diagram:
Transient simulation with 160ms stop time.
Simulation results:
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Experiment 5: Simulation of a multiplexer
circuit (4:1)
A multiplexer is a device that selects between several analog or digital
input signals and forward the selected input to a single output line. the
selection is directed by a separate set of digital inputs known as
selected lines
INPUT OUTPUT
S0 S1 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Simulation diagram:
Transient simulation with 80ms stop time.
Simulation results:
8:1 multiplexer
INPUT OUTPUT
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
Simulation diagram:
Transient simulation with 80ms stop time.
Simulation results:
