FPGA Implementation of I2C & SPI Protocols:

a Comparative Study
A.K. Oudjida, M.L. Berrandjia, R. Tiar, A. Liacha, K. Tahraoui
Microelectronics and Nanotechnology Division
Centre de Développement des Technologies Avancées, CDTA
Algiers, Algeria
Email: [email protected]

Abstract— I2C and SPI are the most commonly used serial In our attempt to implement universal I2C/SPI IP cores [9],
protocols for both inter-chip and intra-chip low/medium we first made a market study of an important number of recent
bandwidth data-transfers. commercial I2C/SPI devices (datasheets) from different
This paper contrasts and compares physical implementation vendors [10] to look at the requirements and what features are
aspects of the two protocols through a number of recent Xilinx’s to be included to satisfy modern ASIC/SoC applications. The
FPGA families, showing up which protocol features are key features required for I2C/SPI IP cores as a result of the
responsible of substantial area overhead. This valuable market investigation are summarized in table II, and their
information helps designers to make careful and tightly tailored translation into architectures are depicted by figures 1 and 2,
architecture decisions. respectively. It’s noteworthy to mention that only the slave
For a comprehensive comparative study, both protocols are side of the protocols is dealt with in this paper.
implemented as general purpose IP solutions, incorporating all
necessary features required by modern ASIC/SoC applications The paper is organized as follows. In this section, we
according to a recent market investigation of an important showed the requirement specifications of a recent market
number of commercial I2C and SPI devices. investigation for modern I2C/SPI IPs and their corresponding
The RTL code is technology independent, inducing around 25% architectures. Section two contrasts and compares the
area overhead for I2C over SPI, and almost the same delays for implementation results. And finally some concluding remarks.
both designs.
TABLE I. COMPARISON OF I2C AND SPI PROTOCOLS
Keywords— Inter Integrated Circuit (I2C), Serial Peripheral
Interface (SPI), Intellectual Property (IP), System-on-Chip I2C SPI
(SoC). Originator Philips (1982) Motorola (1979)
Plug & Play Yes No
I. INTRODUCTION Serial (2 wires) Serial (3+N wires)*
Interface type
Today, at the low end of the communication protocols we Distance Short (In-box communication)
find two worldwide standards: I2C and SPI [1]. Both protocols Multi-master Transfer of
Application
are well suited for communications between integrated circuits register-access data-streams
for low/medium data transfer speed with on-board peripherals. Protocol Low Lower
The two protocols coexist in modern digital electronics Complexity
systems, and they probably will continue to compete in the Design Cost Low Lower
future, as both I2C and SPI are actually quite complementary Limited (100 & 400 Free (n x MHz to
Transfer rate
for this kind of communication [2][3][4][5][6]. KHz and 3.4 MHz) 10n x MHz)
Power Low
The I2C and SPI protocol specifications are meticulously Consumption (2 pull-up resistors)
Lower
defined in [7] and [8], respectively. Consequently, they will Transfer type Half Duplex Full Duplex
not be discussed here. Instead, a quick overview is provided in
Time Constraint Synchronous
table I.
Multi Master+ Yes No
Although the literature on I2C/SPI protocols is so extensive Multi Slave Yes Yes
and the topic is so old (early 1980), to the best of the authors Open-drain with
I/O constraints No constraint
knowledge there is no comprehensive comparison of I2C/SPI pull-up resistors
problem. By comprehensive comparison we mean a treatment Addressing+ Software (7/10 bits) Hardware (Chip Select)
that start from Philips/Motorola specifications and goes down Flow Control+ Yes No
to the actual ASIC/FPGA implementation, contrasting the two Clock Stretching+ Yes No
designs and then comparing the obtained results based on * : N is the number of devices connected to a single master on the bus.
included protocol features. + : Feature inducing substantial area overhead.
This work was supported by Centre de
Développement des Technologies Avancées
(CDTA) Algiers, in conjunction initially with
Technische Universität (TU) Berlin.

978-1-4244-5091-6/09/$25.00 ©2009 IEEE 507

 TABLE II. KEY FEATURES OF I2C-SLAVE AND SPI-SLAVE IPS

Global Key Features

Features I2C-Slave SPI-Slave
• Data transfer up to 100 Kbps in standard mode, and up • Low/medium (n x MHz to 10n x MHz) data transfer rate
to 400 Kbps in fast-mode; depending on implementation issues;
• Fixed data width of 8 bits; • Variable transfer rate (SCLK rate) depending on the master
Data transfer • Frame data-transfer (unlimited number of bytes); SPI baud rate;
• Bidirectional data transfer; • User defined SPI word length;
• Software programmable acknowledge bit ; • Frame data-transfer (unlimited number of words);
• Repeated START detection; • Bidirectional data transfer (full duplex mode);
• Interrupt & polling mode transfer. • Interrupt & polling mode transfer.
• Software programmable address (to be used in different
application fields); • Hardware addressable (Slave Select input pin nSS).
Addressing
• 7-bit & 10 bit addressing format (reduce the risk of
conflicting slave addresses).
• Serial Clock with data acknowledge; • Serial Clock with programmable polarity and phase;
Synchronization • User defined Wait-states insertion period (clock • Hardware defined outputs (full & empty) for Master wait-
stretching). states insertion period (SCLK clock stretching).

• Transfer error recovery (internal status flags, use of a • Transfer error detection (internal status flags and output
Transfer error
timer). signals for overflow and underrun)

Data integrity • Spike filtering (removing input spikes shorter than a certain number of clock cycles).
Host Side
Interface • Simple and basic handshaking protocol easily adaptable to any standard SoC bus [11] via a wrapper [12].

Performance • User defined multiple-bytes write and read buffer (FIFO) to improve transfer performance (reduce wait state occurrences).
Low power • Power conservative state (stop). The I2C and SPI are disconnected from the system and internal activity turned off except for
consumption I/O interface.
• Transmitter only /Receiver only or both;
Parametrizable • With/without FIFO;
Functionalities • With/Without Digital Filter;
• 7bits/10bits Address modes for I2C only.
Implementation • Strictly synchronous design with positive edge clocking for straightforward scan-path insertion;
& test • No internal three-state elements.

Figure 1. I2C-Slave Transceiver Architecture.

508
 C : user configurable size (8,12, 16, 24, 32)
to cope with various applications

Figure 2. SPI-Slave Transceiver Architecture.

II. COMPARISON OF IMPLEMENTATION RESULTS The mapping of RTL-code including two 4-byte FIFOs
For a more precise comparison, early in the design and digital filters onto Xilinx’s FPGA devices (Table IV),
process, some precautions were taken to put both exhibits a slice utilization average around 500 and 360 for I2C-
implementations under the same conditions. Starting from the Slave and SPI-Slave respectively, except for Virtex 5 devices
initial specifications (Table II), we first built up the I2C-Slave where the utilization is around 185 and 140, respectively. This
architecture [10], from which we derived the SPI-Slave one, difference is due to the number of look-up-tables (LUTs) per
keeping exactly the same architectural topology with minor slice, which is: 2 LUTs of 4 inputs each for Spartan 2-3 and
modifications except for the Low-Level Protocol and FSM Virtex 2-4 devices, and 4 LUTs of 6 inputs each for Virtex 5
units. Afterwards, the I2C-Slave architecture was translated devices. Note that some slices are used only for routing.
into a high-quality technology-independent RTL code. The Nevertheless, whatever the FPGA device used; the I2C-Slave
same code was used for the SPI-Slave with necessary induces an average of 25% area overhead over SPI-Slave,
modifications. Both RTL codes were written by the same which is the counterpart of higher usage flexibility and a more
designer to preserve the same coding style. secure transfer.

The whole design code, either for synthesis or functional It is noteworthy to mention that all results, either for slice
verification, is implemented in Verilog 2001 (IEEE 1365). occupation or delays, are obtained using the default options of
The synthesis design code is technology independent and was the implementation software (Foundation ISE 10.1) with the
simulated at both RTL and gate level (post place & route selection of the fastest speed grade for each FPGA device.
netlist) with timing back annotation using ModelSim SE 6.3f
and mapped onto Xilinx’s FPGAs using Foundation ISE 10.1 TABLE III. COMPARISON OF RTL-CODES
version. Both designs have undergone severe functional
software verification procedure according to our own IP I2C-Slave SPI-Slave
development methodology summarized in [9]. As for physical Architecture Units Number Size Number Size
test, both designs were integrated around Microblaze SoC of Lines (Ko) of Lines (Ko)
environment using V2MB1000 demonstration board [13] with Top Module (HSI + FSM) 598 22 434 15
Xilinx’s EDK 9.1i version. Low-level Protocol 472 19 217 8
FIFO 232 7 232 7
The RTL-Code size of I2C-Slave is about 1.44 times the Filter 67 4 67 4
code size of SPI-Slave (Table III). The 44% extra code size is
Total 1369* 52 950* 34
mainly due to the additional logic required by the I2C-Slave to
* : (1369-950)/950 = 0.44
handle the software addressing (7/10 bits), the control flow,
and clock stretching features (Table I).

509
 There is almost no significant TABLE IV. COMPARISON OF OCCUPIED SLICES
difference in terms of delays (Table
I2C-Slave SPI-Slave
V). Delays are calculated for two
types of paths: Clock-To-Setup and all Xilinx’s FPGA Number of Number of Number of
Utilization Utilization
Device Total Slices Occupied Slices Occupied Slices
paths together (Pad-To-Setup, Clock-
To-Pad and Pad-To-Pad.) The Clock- xc2s50-6tq144 768 + 510 66% 363 47%
To-Setup gives more precise xc3s50-5tq144 768+ 503 65% 354 46%
information on the delays than other xc2v80-6cs144 512+ 504 98% 366 71%
remaining paths, which depend in fact xc4vlx15-12sf363 6114+ 512 8% 360 5%
on I/O Block (IOB) configuration xc5vlx30-3ff324 4800x 187 3% 141 2%
(low/high fanout, CMOS, TTL, + : each slice includes 2 LUTs of 4 inputs
LVDS…) x : each slice includes 4 LUTs of 6 inputs

The transfer rate for I2C-Slave is fixed, while for

SPI-Slave is unlimited, but for both a timing TABLE V. COMPARISON OF DELAYS
relationship between the master clock and the
synchronous transfer clock must be known to enable I2C-Slave SPI-Slave
the sampling of smallest events depending on the Xilinx’s FPGA Clock-To-Setup All Clock-To-Setup All
Device Paths Paths Paths Paths
timing constraints of each protocol [7][8]. The master
clock (clk) must be at least 5 and 4 times faster than xc2s50-6tq144 12.079 ns 19.616 ns 12.234 ns 17.042 ns
the transfer clock (scl, sclk) for I2C-Slave and SPI- xc3s50-5tq144 7.636 ns 14.996 ns 7.835 ns 12.089 ns
Slave respectively. In fact only a ratio of 2 is required xc2v80-6cs144 6.483 ns 12.806 ns 6.604 ns 10.234 ns
for SPI-Slave, but the RTL coding style requires 2 xc4vlx15-12sf363 4.863 ns 9.572 ns 5.006 ns 8.880 ns
additional clock cycles. xc5vlx30-3ff324 3.606 ns 7.998 ns 3.303 ns 6.971 ns

For instance, if we consider the Clock-To-Setup

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