Avionics

Unit – 1

Avionics Technology

Avionics are the electronic systems used on aircraft, artificial satellites, and spacecraft.

Avionic systems include communications, navigation, the display and management of multiple
systems, and the hundreds of systems that are fitted to aircraft to perform individual functions.
These can be as simple as a searchlight for a police helicopter or as complicated as the tactical
system for an airborne early warning platform.

The term avionics is a portmanteau of the words aviation and electronics.

Aircraft avionics

The cockpit of an aircraft is a typical location for avionic equipment, including control, monitoring,
communication, navigation, weather, and anti-collision systems. The majority of aircraft power their
avionics using 14- or 28-volt DC electrical systems; however, larger, more sophisticated aircraft (such as
airliners or military combat aircraft) have AC systems operating at 400 Hz, 115 volts AC. There are
several major vendors of flight avionics, including Panasonic Avionics Corporation, Honeywell (which
now owns Bendix/King), Rockwell Collins, Thales Group, Garmin and Avidyne Corporation.

International standards for avionics equipment are prepared by the Airlines Electronic Engineering
Committee (AEEC) and published by ARINC.

Communications

Communications connect the flight deck to the ground and the flight deck to the passengers. On-board
communications are provided by public address systems and aircraft intercoms.

The VHF aviation communication system works on the airband of 118.000 MHz to 136.975 MHz. Each
channel is spaced from the adjacent ones by 8.33 kHz in Europe, 25 kHz elsewhere. VHF is also used for
line of sight communication such as aircraft-to-aircraft and aircraft-to-ATC. Amplitude modulation (AM)
is used, and the conversation is performed in simplex mode. Aircraft communication can also take place
using HF (especially for trans-oceanic flights) or satellite communication.

Navigation

Navigation is the determination of position and direction on or above the surface of the Earth. Avionics
can use satellite-based systems (such as GPS and WAAS), ground-based systems (such as VOR or
LORAN), or any combination thereof. Navigation systems calculate the position automatically and
display it to the flight crew on moving map displays. Older avionics required a pilot or navigator to plot
the intersection of signals on a paper map to determine an aircraft's location; modern systems calculate
the position automatically and display it to the flight crew on moving map displays.
Monitoring

The Airbus A380 glass cockpit featuring pull-out keyboards and two wide computer screens on the sides
for pilots.

The first hints of glass cockpits emerged in the 1970s when flight-worthy cathode ray tubes (CRT)
screens began to replace electromechanical displays, gauges and instruments. A “glass” cockpit refers to
the use of computer monitors instead of gauges and other analog displays. Aircraft were getting
progressively more displays, dials and information dashboards that eventually competed for space and
pilot attention. In the 1970s, the average aircraft had more than 100 cockpit instruments and controls.

Glass cockpits started to come into being with the Gulfstream G-IV private jet in 1985. One of the key
challenges in glass cockpits is to balance how much control is automated and how much the pilot should
do manually. Generally they try to automate flight operations while keeping the pilot constantly
informed.

Aircraft flight control systems

Aircraft have means of automatically controlling flight. Today automated flight control is common to
reduce pilot error and workload at key times like landing or takeoff. Autopilot was first invented by
Lawrence Sperry during World War II to fly bomber planes steady enough to hit precision targets from
25,000 feet. When it was first adopted by the U.S. military, a Honeywell engineer sat in the back seat
with bolt cutters to disconnect the autopilot in case of emergency. Nowadays most commercial planes
are equipped with aircraft flight control systems in order to reduce pilot error and workload at landing
or takeoff.

The first simple commercial auto-pilots were used to control heading and altitude and had limited
authority on things like thrust and flight control surfaces. In helicopters, auto stabilization was used in a
similar way. The first systems were electromechanical. The advent of fly by wire and electro-actuated
flight surfaces (rather than the traditional hydraulic) has increased safety. As with displays and
instruments, critical devices that were electro-mechanical had a finite life. With safety critical systems,
the software is very strictly tested.
Collision-avoidance systems

To supplement air traffic control, most large transport aircraft and many smaller ones use a traffic alert
and collision avoidance system (TCAS), which can detect the location of nearby aircraft, and provide
instructions for avoiding a midair collision. Smaller aircraft may use simpler traffic alerting systems such
as TPAS, which are passive (they do not actively interrogate the transponders of other aircraft) and do
not provide advisories for conflict resolution.

To help avoid collision with terrain (CFIT), aircraft use systems such as ground-proximity warning
systems (GPWS), which use radar altimeters as a key element. One of the major weaknesses of GPWS is
the lack of "look-ahead" information, because it only provides altitude above terrain "look-down". In
order to overcome this weakness, modern aircraft use a terrain awareness warning system (TAWS).

BlackBoxes

Commercial aircraft cockpit data recorders, commonly known as a “black box”, store flight information
and audio from the cockpit. They are often recovered from a plane after a crash to determine control
settings and other parameters during the incident.

Weather systems

Weather systems such as weather radar (typically Arinc 708 on commercial aircraft) and lightning
detectors are important for aircraft flying at night or in instrument meteorological conditions, where it is
not possible for pilots to see the weather ahead. Heavy precipitation (as sensed by radar) or severe
turbulence (as sensed by lightning activity) are both indications of strong convective activity and severe
turbulence, and weather systems allow pilots to deviate around these areas.

Mission or tactical avionics

Military aircraft have been designed either to deliver a weapon or to be the eyes and ears of other
weapon systems. The vast array of sensors available to the military is used for whatever tactical means
required. As with aircraft management, the bigger sensor platforms (like the E-3D, JSTARS, ASTOR,
Nimrod MRA4, Merlin HM Mk 1) have mission-management computers.

Military communications

While aircraft communications provide the backbone for safe flight, the tactical systems are designed to
withstand the rigors of the battle field. UHF, VHF Tactical (30-88 MHz) and SatCom systems combined
with ECCM methods, and cryptography secure the communications. Data links such as Link 11, 16, 22
and BOWMAN, JTRS and even TETRA provide the means of transmitting data (such as images, targeting
information etc.).

Radar

Airborne radar was one of the first tactical sensors. The benefit of altitude providing range has meant a
significant focus on airborne radar technologies. Radars include airborne early warning (AEW), anti-
submarine warfare (ASW), and even weather radar (Arinc 708) and ground tracking/proximity radar.
The military uses radar in fast jets to help pilots fly at low levels.[citation needed] While the civil market has
had weather radar for a while, there are strict rules about using it to navigate the aircraft.

Aircraft networks

The avionics systems in military, commercial and advanced models of civilian aircraft are interconnected
using an avionics databus. Common avionics databus protocols, with their primary application, include:

 Avionics Full-Duplex Switched Ethernet (AFDX): Specific implementation of ARINC 664 (ADN) for
Commercial Aircraft
 ARINC 429: Generic Medium-Speed Data Sharing for Private and Commercial Aircraft
 ARINC 629: Commercial Aircraft (Boeing 777)
 ARINC 717: Flight Data Recorder for Commercial Aircraft
 MIL-STD-1553: Military Aircraft
 MIL-STD-1760: Military Aircraft
 TTP - Time-Triggered Protocol: Boeing 787 Dreamliner, Airbus A380, Fly-By-Wire Actuation
Platforms from Parker Aerospace.

Introduction of Microprocessor

A Microprocessor is an important part of a computer architecture without which you will not be able
to perform anything on your computer. It is a programmable device that takes in input performs some
arithmetic and logical operations over it and produces the desired output. In simple words, a
Microprocessor is a digital device on a chip that can fetch instructions from memory, decode and
execute them and give results.

Basics of Microprocessor –

A Microprocessor takes a bunch of instructions in machine language and executes them, telling the
processor what it has to do. Microprocessor performs three basic things while executing the
instruction:

1. It performs some basic operations like addition, subtraction, multiplication, division, and some
logical operations using its Arithmetic and Logical Unit (ALU). New Microprocessors also perform
operations on floating-point numbers also.

2. Data in microprocessors can move from one location to another.

3. It has a Program Counter (PC) register that stores the address of the next instruction based on the
value of the PC, Microprocessor jumps from one location to another and takes decisions.

Types of Processor:

Complex Instruction Set Computer (CISC) –

CISC or Complex Instruction Set Computer is a computer architecture where instructions are such that
a single instruction can execute multiple low-level operations like loading from memory, storing into
memory, or an arithmetic operation, etc. It has multiple addressing nodes within a single
instruction.CISC makes use of very few registers.

Example: 1. Intel 386; 2. Intel 486; 3. Pentium; 4. Pentium Pro; 5. Pentium II; 6. Pentium III; 7.
Motorola 68000; 8. Motorola 68020; 9. Motorola 68040 etc.

Reduced Instruction Set Computer (RISC) –

RISC or Reduced Instruction Set Computer is a computer architecture where instruction is simple and
designed to get executed quickly. Instructions get completed in one clock cycle this is because of the
optimization of instructions and pipelining (a technique that allows for simultaneous execution of
parts, or stages, of instructions more efficiently process instructions). RISC makes use of multiple
registers to avoid large interactions with memory. It has few addressing nodes.
Example: 1. IBM RS6000; 2. MC88100; 3. DEC Alpha 21064; 4. DEC Alpha 21164; 5. DEC Alpha 21264

Explicitly Parallel Instruction Computing (EPIC) –

EPIC or Explicitly Parallel Instruction Computing permits computers to execute instructions parallel
using compilers. It allows complex instructions execution without using higher clock frequencies.EPIC
encodes its instruction into 128-bit bundles. each bundle contains three instructions which are
encoded in 41 bits each and a 5-bit template field(contains information about types of instructions in
a bundle and which instructions can be executed in parallel).
Example: IA-64 (Intel Architecture-64)

Internal Architecture of 8085 Microprocessor

Control Unit

Generates signals within uP to carry out the instruction, which has been decoded. In reality causes
certain connections between blocks of the uP to be opened or closed, so that data goes where it is
required, and so that ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc.
Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation
in Accumulator.

Registers

The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as
shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They
are described briefly as follows.

The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H,
and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL - to perform some
16-bit operations. The programmer can use these registers to store or copy data into the registers by
using data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to
store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in
the accumulator. The accumulator is also identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of
the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P),
and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are
shown in the Figure below.

The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test
data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger
than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an
arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure
shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a
register; five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are
stored in the 8-bit register so that the programmer can examine these flags (data

conditions) by accessing the register through an instruction. These flags have critical importance in the
decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested
through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in
writing assembly language programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a memory
pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The
microprocessor uses this register to sequence the execution of the instructions. The function of the
program counter is to point to the memory address from which the next byte is to be fetched. When a
byte (machine code) is being fetched, the program counter is incremented by one to point to the next
memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in
R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the
stack pointer. The stack concept is explained in the chapter "Stack and Subroutines."

Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here from memory
prior to execution. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded
instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of
location of the program under execution.

Control Generator

Generates signals within uP to carry out the instruction which has been decoded. In reality causes
certain connections between blocks of the uP to be opened or closed, so that data goes where it is
required, and so that ALU operations occur.
Register Selector

This block controls the use of the register stack in the example. Just a logic circuit which switches
between different registers in the set will receive instructions from Control Unit.

General Purpose Registers

It requires extra registers for versatility. Can be used to store additional data during a program. More
complex processors may have a variety of differently named registers.

Computer Data Storage (Memory)

Computer data storage, often called storage or memory, refers to computer components and
recording media that retain digital data used for computing for some interval of time. Computer data
storage provides one of the core functions of the modern computer, that of information retention. It is
one of the fundamental components of all modern computers, and coupled with a central processing
unit (CPU, a processor), implements the basic computer model used since the 1940s.

In contemporary usage, memory usually refers to a form of semiconductor storage known as

random-access memory(RAM), typically DRAM (Dynamic-RAM) but many times other forms of fast but
temporary storage. Similarly, storage today more commonly refers to storage devices and their media
not directly accessible by the CPU (secondary or tertiary storage) — typically hard disk drives, optical
disc drives, and other devices slower than RAM, but of a more permanent nature. Historically, memory
has been called main memory, real storage or internal memory while storage devices have been
referred to as secondary storage, external memory or auxiliary/peripheral storage.

Fig.1 Computer Memory Types

Memory Types

 Volatile memory
 Random Access Memory (RAM) – static RAM, dynamic RAM
 Non-Volatile memory
 Read-only memory (ROM) – PROM, EPROM, EEPROM
 Flash memory
Volatile memory

Volatile memory, also known as volatile storage, is computer memory that requires power to
maintain the stored information, unlike non-volatile memory which does not require a maintained
power supply. It has been less popularly known as temporary memory.

Non-volatile memory

Non-volatile memory (NVM or non-volatile storage) is computer memory that can retain the
stored information even when not powered. Examples of non-volatile memory include read-only
memory, flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy disks,
and magnetic tape), optical discs, and early computer storage methods such as paper tape and punched
cards.

Random-access memory (RAM)

Random-access memory (RAM) is a form of computer data storage. Today, it takes the form of
integrated circuits that allow stored data to be accessed in any order (i.e., at random). "Random" refers
to the idea that any piece of data can be returned in a constant time, regardless of its physical location
and whether or not it is related to the previous piece of data.

By contrast, storage devices such as magnetic discs and optical discs rely on the physical
movement of the recording medium or a reading head. In these devices, the movement takes longer
than data transfer, and the retrieval time varies based on the physical location of the next item.

The word RAM is often associated with volatile types of memory (such as DRAM memory
modules), where the information is lost after the power is switched off. Many other types of memory
are RAM, too, including most types of ROM and a type of flash memory called NOR-Flash.

Types of RAM

 Static RAM (SRAM)

 Static random access memory (SRAM) is a type of semiconductor memory where the
word ‘static’ indicates that it does not need to be periodically refreshed, as SRAM uses
bistable latching circuitry to store each bit.
 Dynamic RAM (DRAM)
 Dynamic random access memory (DRAM) is a type of random access memory that
stores each bit of data in a separate capacitor within an integrated circuit.
  Since real capacitors leak charge, the information eventually fades unless the capacitor
charge is refreshed periodically. Because of this refresh requirement, it is a dynamic
memory as opposed to SRAM and other static memory.
 The main memory (the "RAM") in personal computers is Dynamic RAM.
 The advantage of DRAM is its structural simplicity: only one transistor and a capacitor
are required per bit, compared to six transistors in SRAM. This allows DRAM to reach
very high density.
Read-only memory

Read-only memory (usually known by its acronym, ROM) is a class of storage media used in
computers and other electronic devices. Because data stored in ROM cannot be modified (at least not
very quickly or easily), it is mainly used to distribute firmware (software that is very closely tied to
specific hardware, and unlikely to require frequent updates).

Programmable read-only memory (PROM)

A programmable read-only memory (PROM) or field programmable read-only memory (FPROM)

or one-time programmable non-volatile memory (OTP NVM) is a form of digital memory where the
setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently.
The key difference from a strict ROM is that the programming is applied after the device is constructed.

PROMs are manufactured blank and, depending on the technology, can be programmed at
wafer, final test, or in system. The availability of this technology allows companies to keep a supply of
blank PROMs in stock, and program them at the last minute to avoid large volume commitment. These
types of memories are frequently seen in video game consoles, mobile phones, radio-frequency
identification (RFID) tags, implantable medical devices, high-definition multimedia interfaces (HDMI) and
in many other consumer and automotive electronics products.

EPROM

An EPROM, or erasable programmable read only memory, is a type of memory chip that retains
its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-
gate transistors individually programmed by an electronic device that supplies higher voltages than
those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to
strong ultraviolet light from a mercury-vapor light source. EPROMs are easily recognizable by the
transparent fused quartz window in the top of the package, through which the silicon chip is visible, and
which permits exposure to UV light during erasing.

EEPROM

EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of
non-volatile memory used in computers and other electronic devices to store small amounts of data
that must be saved when power is removed, e.g., calibration tables or device configuration.
 When larger amounts of static data are to be stored (such as in USB flash drives) a specific type
of EEPROM such as flash memory is more economical than traditional EEPROM devices. EEPROMs are
realized as arrays of floating-gate transistors.

EEPROM is user-modifiable read-only memory that can be erased and reprogrammed (written
to) repeatedly through the application of higher than normal electrical voltage generated externally or
internally in the case of modern EEPROMs. EPROM usually must be removed from the device for erasing
and programming, whereas EEPROMs can be programmed and erased in circuit. Originally, EEPROMs
were limited to single byte operations which made them slower, but modern EEPROMs allow multi-byte
page operations. It also has a limited life - that is, the number of times it could be reprogrammed was
limited to tens or hundreds of thousands of times. That limitation has been extended to a million write
operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed while the computer is
in use, the life of the EEPROM can be an important design consideration. It is for this reason that
EEPROMs were used for configuration information, rather than random access memory.

Flash memory

Flash memory is a non-volatile computer storage technology that can be electrically erased and
reprogrammed. It is primarily used in memory cards, USB flash drives, and solid-state drives for general
storage and transfer of data between computers and other digital products. It is a specific type of
EEPROM that is erased and programmed in large blocks; in early flash the entire chip had to be erased at
once. Flash memory costs far less than byte-programmable EEPROM and therefore has become the
dominant technology wherever a significant amount of non-volatile, solid state storage is needed.
Example applications include PDAs (personal digital assistants), laptop computers, digital audio players,
digital cameras and mobile phones. It has also gained popularity in console video game hardware, where
it is often used instead of EEPROMs or battery-powered static RAM for game save data.

Since flash memory is non-volatile, no power is needed to maintain the information stored in
the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM
memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These
characteristics explain the popularity of flash memory in portable devices. Another feature of flash
memory is that when packaged in a "memory card," it is extremely durable, being able to withstand
intense pressure, extremes of temperature, and even immersion in water.

Although technically a type of EEPROM, the term "EEPROM" is generally used to refer
specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles
are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over
old-style EEPROM when writing large amounts of data.
Avionics Data Bus

A bus is a data highway that links one LRU (Line Replaceable Unit) to another. In earlier avionic systems,
communication cables are used to transmit the data. To transfer a bit of data at least one pair of wires is
needed for each signal. These wires transmit information over a single twisted and shielded pair of wires
(the data bus) to all other system elements having need of that information (up to as many as 20
receivers). A data bus connects all the internal components of the computer to the CPU and main
memory. When referred to as an aircraft, it is the data highway that links one computer to another
aircraft like the FMC (Flight Management Computer) and the ADC (Air Data Computer).

Based on the type of connection data buses are classified into two types. They are serial bus and parallel
bus.

Serial Bus: As the mentioned in the name, each bit of the data word is transferred via the same wire.
Only one bit of word is sent at a time. Examples of serial data bus are PCIe, USB, ARINC, I2C, etc.
Parallel Bus: In this type, each bit of the data word is transferred via a specific wire. It requires a lot of
wiring. Examples of parallel bus are conventional PCI.

Major Avionics Data Buses

ARINC 429

It is developed to promote interoperability between devices on civil aircraft. Designed to connect a

single transmitter to 10 receivers. Messages are expected to be transmitted between once and up to 50
times a second. Receivers receive their data simultaneously which accomplishes the synchronization.

ARINC 429 uses simplex, twisted shielded pair data bus. It consist of one transmitter and multiple
receiver (up to 20 receiver connected to one twisted pair of wire). It does not have Bus monitor, Remote
terminal or Bus controller as like that of 1553B data Bus. A transmitter may „talk only‟ to a number of
receivers on the bus, up to 20 on one wire pair, with each receiver continually monitoring for its
applicable data, but does not acknowledge receipt of the data. A transmitter may require
acknowledgement from a receiver when large amounts of data have been transferred. This handshaking
is performed using a particular word style, as opposed to a hard wired handshake. When this two way
communication format is required, two twisted pairs constituting two channels are necessary to carry
information back and forth, one for each direction.

Communication on 429 data bus uses 32 bit words with odd parity. The wave form uses is bipolar return
to zero with each bit lasting either 70 or 83 microsec+_2.5 percent or 10microsec+_2.5 percent depends
on operating speed of bus. ARINC-429 data bus operate in two speeds – Low speed (12.5 kHz ) – High
speed (100kHz). Low speed bus is used for general purpose low critical application . High speed bus is
used for transmitting large quantities of data's or flight critical applications.

Transmission from the source LRU is comprised of 32 bit words containing a 24 bit data portion
containing the actual information, and an 8 bit label describing the data itself. LRUs have no address
assigned through ARINC 429, but rather have Equipment ID numbers which allow grouping equipment
into systems, which facilitates system management and file transfers. Sequential words are separated
by at least 4 bit times of null or zero voltage. Transmission rates may be at either a low speed – 12.5 kHz
– or a high speed – 100kHz.

ARINC 429 data words are 32 bit words made up of five primary fields:

• Parity – 1 bit
• Sign/Status Matrix (SSM) – 2 bits
• Data – 19 bits
• Source/Destination Identifier (SDI) – 2 bits
• Label – 8 bits
Parity bit helps to Detect Error in the receiving words. ARINC 429 uses odd parity as error check to
insure accurate data reception. The number of Logic 1s transmitted in each word is an odd number. The
receiver checks the received words having odd logic or not. Odd logic 1s - accept the word. Even logic
1s- reject the word
ARINC 429 data types:
BNR Word Format (Signed Binary Number) – Encoded and transmitted by using 2s complement
fractional binary notation.
BCD Word Format (Binary coded Decimal) - Discrete Data-combination of Both BNR and BCD –
Combination of BNR, BCD or individual bit representation. Maintenance data and Acknowledgement
Data-Requires two way communication – Alphanumeric Data encoded.
File data transfers by using Williamsburg/Buckhorn Protocol – A bit-oriented protocol.
Williamsburg/Buckhorn Protocol
Williamsburg/Buckhorn is a bit oriented protocol used to File Transfer across an ARINC bus. It is updated
version of AIM data (Acknowledge, ISO Alphabet NO.5 and Maintenance Data) which was used in earlier
version of ARINC 429. File transfer are necessary when more than 21 bits of data are required to
transmitted. When initiating a file transfer – the source and receiver need to establish first. Followed by
source initiate a predefined code to determine compatibility with receiver units. A request to send word
(RTS) is Transmitted containing a destination code and word count. The receiver responds with a Clear
to send word (CTS) retransmitting back to the destination and word count information. Upon
confirmation of CTS, the source begins the file transfer. Files are transferred in Link Data Units (LDUs)
format. Means, the entire file is divided into 3 to 255 words of length depends upon size of the file. File
transfer begin with a Start of Transmission word (SOT) which includes file sequence number, general
format identifier(GFI), and LDU sequence Number. After the SOT , the data words are sent, followed by
end of transmission (EOT). The EOT includes a CRC and LDU position in the file being sent. The receiver
decodes the files depends upon their LDU position.
ARINC 629:

ARINC 629 is a specification for a bus on which terminals are connected. There is no controller on the
bus. Each terminal on the bus is able to identify when it is its turn to transmit. Synchronization between
the terminals is ensured by three timers (the transmit interval, the synchronization gap and the terminal
gap). Up to 120 terminals can transmit on one bus. ARINC 629 messages are 31 word strings long
(maximum). Word string is a 20-bit long label word followed by 0 to 256 16-bit long data words. A
maximum of 31 messages can be transmitted by a terminal. Messages are transmitted at a speed of
2Mbps. At the physical layer, it features communication of messages over bidirectional, unshielded,
bipolar electrical interface.

Data is transmitted in groups called Messages. Messsages can have different lengths. After
each message, there is a unique Terminal Gap (TG). Messages are composed of a maximum of
31 wordstrings that can also have variable lenghts. Between each wordstring, there is a 4 bit time
gap. Wordstrings are a label word followed by 0 to 256 data words. Words (label words and data words)
are 20 bit long. Before the first label word of a message comes a one half bit time pulse called pre sync
sync pulse (PSSP).

Transmission and Data Types

Transmission

At the physical layer the data words are transmitted on the data bus the synchronization bits first and
then the data (depends upon word type) followed by the parity bit. The data is transmitted with LSB first
and MSB last.

Data Types

Typically the data types used by ARINC 629 are:

 Binary Number Representation (BNR): In fractional binary two's complement.

BNR encoding stores data as a binary number. BNR is most efficient in terms of bus capacity and
should generally be used. The sign of BNR Numeric Data words should be encoded on bit 19.
Negative BNR numbers are encoded as the two's complements of positive values with the
negative sign denoted as a logic 1 in data bit 19.

 Binary Code Decimal (BCD): Numerical Subset of ISO Alphabet No 5

BCD encodes each decimal value in 4-bit digit.

For instance the value "75839" is encoded in binary as "111 0101 1000 0011 1001" and other less used
data types:

 Alphanumeric Data - Should be coded per ISO Code #5.

  Discrete Data - Should be transmitted in dedicated discrete words.

Block Mode and Independent Mode

 Block Mode:
Useful when a terminal has a small range of data to periodically update.
Messages generated in Block Mode generally have a variable number of wordstring.
One X-modulo and one Y-modulo. Each message is composed of the wordstrings that are on a
same Y line of the XPP.
 Independent Mode: Useful when a terminal has a large range of data with different update
rates. Messages generated in Independent Mode generally have a constant number of word
string. One X-modulo and many Y-moduli. Each column of the XPP works independently. As in
Block Mode, each message transmitted is composed of wordstrings with growing X-indexes in
the XPP. In Independent Mode, for a given column X, the wordstring to transmit is chosen as the
one with a Y-index just above the last wordstring transmitted in this column. Thus, a column X in
the XPP with few wordstrings will have a greater update rate than another column with many
wordstrings.

MIL-STD-1553B

MIL-STD-1553, is a published technical standard that defines the mechanical, electrical, and functional
characteristics of a serial data bus. It features a dual redundant balanced line physical layer, a
(differential) network interface, time division multiplexing, half-duplex command/response protocol,
and up to 31 or 32 remote terminals depending on the version (1553B or 1553A).

MIL-STD-1553 is a military standard created in the early 1970s that defines the concept of operation and
information flow on a multiplexed data bus, and the electrical and functional formats to be employed.
The data bus is used to transfer command/response messages between multiple terminals. It may
interconnect up to 31 or 32 Remote Terminals (RT), multiple Bus Monitors (BM) and a Bus Controller
(BC). In a typical system, a dual redundant bus is used. Usually, only the primary bus (Bus A) is used to
transfer messages; however, the secondary bus (Bus B) may also be used to perform a transfer. If a
transfer fails on one bus, retry options allow the transmitter to try the transmission again on the same
bus or on the alternate bus. Transmission on the bus occurs serially at 1Mbps. It uses a
command/response protocol that transfers a maximum of 32 data words per message with each data
word containing 20 bits. The message transmitted on the data bus follows one of these formats: BC to
RT, RT to BC or RT to RT. Broadcast transmission is also available with 1553B, address 31 is reserved for
that functionality.

Reference: Kindly go through the below link for detailed explanation about data bus systems.

https://www.maxt.com/mxf/mil1553_bm.html
The various avionics architectures in detail

First Generation Architecture ( 1940’s –1950’s)

• Disjoint or Independent Architecture ( MiG-21)

• Centralized Architecture (F-111)
Second Generation Architecture( 1960’s –1970’s)

• Federated Architecture (F-16 A/B)

• Distributed Architecture (DAIS)
• Hierarchical Architecture (F-16 C/D, EAP)
Third Generation Architecture ( 1980’s –1990’s)

• Pave Pillar Architecture ( F-22)

Fourth Generation Architecture (Post 2005)

• Pave Pace Architecture- JSF

• Open System Architecture
FGA - DISJOINT ARCHITECTURE

The early avionics systems were stand alone black boxes where each functional area had separate,
dedicated sensors, processors and displays and the interconnect media is point to point wiring

The system was integrated by the air-crew who had to look at various dials and displays connected to
disjoint sensors correlate the data provided by them, apply error corrections, orchestrate the functions
of the sensors and perform mode and failure management in addition to flying the aircraft

This was feasible due to the simple nature of tasks to be performed and due to the availability of time
FGA-CENTRALIZED ARCHITECTURE

 As the digital technology evolved,a central computer was added to integrate the information
from the sensors and subsystems
 The central computing complex is connected to other subsystems and sensors through
analog,digital, synchro and other interfaces
 When interfacing with computer a variety of different transmission methods , some of which
required signal conversion (A/D) when interfacing with computer
 Signal conditioning and computation take place in one or more computers in a LRU located in an
avionics bay , with signals transmitted over one way data bus
 Data are transmitted from the systems to the central computer and the DATA CONVERSION
TAKES PLACE AT THE CENTRAL COMPUTER

ADVANTAGES:

 Simple design
 Software can be easily written
 Computers are available in readily accessible bay

DISADVANTAGES

 Requirement of long data buses

 Low flexibility in software
 Increased vulnerability to change
 Different conversion techniques needed at Central Computer

Motivated to develop a COMMON STANDARD INTERFACE for interfacing the different avionics systems.
SGA – FEDERATED ARCHITECTURE

Federated : Join together, Become partners

Each system acts independently but united (Loosely Coupled)

 Unlike FGA – CA , Data conversion occurs at the system level and the datas are send as digital
form – called Digital Avionics Information Systems(DAIS)
 Several standard data processors are often used to perform a variety of Low – Bandwidth
functions such as navigation, weapon delivery , stores management and flight control
 Systems are connected in a Time – Shared Multiplex Highway
 Resource sharing occurs at the last link in the information chain – via controls and displays
 Programmability and versatility of the data processors

ADVANTAGES

 Contrast to analog avionics – DDP provide precise solutions over long range
of flight , weapon and sensor conditions

 Sharing of Resources
 Use of TDMA saves hundreds of pounds of wiring
 Standardization of protocol makes the interchangeability of equipments
easier

 Allows Independent system design and optimization of major systems

 Changes in system software and hardware are easy to make
 Fault containment – Failure is not propagated
DISADVANTAGES : Profligate of resources
SGA – DISTRIBUTED ARCHITECTURE

 It has multiple processors throughout the aircraft that are designed for computing takes on a
real-time basis as a function of mission phase and/or system status
 Processing is performed in the sensors and actuators
ADVANTAGES:

 Fewer shorter buses

 Faster program execution
 Intrinsic partitioning
DISADVANTAGES:

 Potentially greater diversity in processor types which aggravates software generation and
validation
SGA – DISTRIBUTED ARCHITECTURE

This architecture is derived from the federated architecture

It is based on the TREE Topology
ADVANTAGES

 Critical functions are placed in a separate bus and Non-Criticalfunctions are placed in
another bus
 Failure in non – critical parts of networks do not generatehazards to the critical parts of
network
 The communication between the subsystems of a particulargroup are confined to their
particular group
 The overload of data in the main bus is reduced
 Most of the military avionics flying today based on HIERARCHICAL ARCHITECTURE
TGA –PAVE PILLAR

The reason for using pave pillar :

Pave Pillar is a USAF program to define the requirements and avionics architecture for fighter aircraft of
the 1990s

The Program Emphasizes

 Increased Information Fusion
 Higher levels and complexity of software
 Standardization for maintenance simplification
 Lower costs
 Backward and growth capability while making use ofemerging technology – VHSIC, Voice
Recognition /synthesisand Artificial Intelligence
 Provides capability for rapid flow of data in, through and fromthe system as well as between
and within the system
 Higher levels of avionics integration and resource sharing ofsensor and computational
capabilities
 Pilot plays the role of a WEAPON SYSTEM MANAGER asopposed to subsystem
operator/information integrator
 Able to sustain operations with minimal support, fly successfulmission day and night in any
type of weather
 Face a numerically and technologically advanced enemyaircraft and defensive systems

ABOUT PAVE PILLR ARCHITECTURE:

 Component reliability gains

 Use of redundancy and resource sharing
 Application of fault tolerance
 Reduction of maintenance test and repair time
 Increasing crew station automation
 Enhancing stealth operation
 Wide use of common modules (HW & SW))
 Ability to perform in-aircraft test and maintenance of avionics
 Use of VHSIC technology and
 Capability to operate over extended periods of time at austere,
 deployed locations and be maintainable without the Avionics
 Intermediate Shop
FTGA – PAVE PACE ARCHITECHTURE

Pilot Vehicle
Interfacing

Integrated RF Sensing

Integrated
Core
Processing

Integrated EO Sensing

Integrated Vehicle
Management

Integrated Stores Management

THE REASON FOR USING PAVE PACE ARCHITECTURE

 Modularity concepts cuts down the cost of the avionics related toVMS, Mission Processing,
PVI and SMS
 The sensor costs accounts for 70% of the avionics cost
 USAF initiated a study project to cut down the cost of sensorsused in the fighter aircraft
 In 1990, Wright Laboratory – McDonnell Aircraft, Boeing aircraft company and Lockheed
launched the Pave Pace Program
 Come with the Concept of Integrated Sensor System(IS2)
 Pave Pace takes Pave Pillar as a base line standard
 The integration concept extends to the skin of the aircraft –Integration of the RF & EO
sensors
 Originally designed for Joint Strike Fighter (JSF)