Sample Multiple Choice questions
1. What does the term "Computer Architecture" refer to?
A) The operational units of a computer
B) The logical structure and behavior as seen by the programmer
C) The physical connections between components
D) The hardware of the computer
Answer: B
2. What is the main role of the ALU in a computer system?
A) Store data temporarily
B) Control all other units
C) Perform arithmetic and logical operations
D) Handle input and output operations
Answer: C
Which of the following is NOT a primary function of a computer?
A) Data processing
B) Data storage
C) Data transformation
D) Data movement
Answer: C
Which bus is primarily responsible for connecting the CPU to main memory?
A) Data bus
B) Address bus
C) System bus
D) Control bus
Answer: C
The concept where both data and instructions are stored in the same memory is
known as:
A) Harvard Architecture
B) Cache memory
C) Von Neumann Architecture
D) Microprogramming
Answer: C
In the hierarchy of memory, which type of memory is closest to the CPU?
A) Main memory
B) Hard disk
C) Cache memory
D) Registers
Answer: D
Which part of the CPU is responsible for fetching and executing instructions?
A) Control unit
B) Memory
C) Arithmetic Logic Unit (ALU)
D) Input/Output system
Answer: A
Which of the following is a non-volatile type of memory?
A) RAM
B) Cache
C) ROM
D) Registers
Answer: C
What is a stored-program computer?
A) A computer where programs are manually loaded for execution
B) A computer where the program is stored in a separate hardware component
C) A computer where instructions and data are stored in memory
D) A computer with built-in programming abilities
Answer: C
Which cache level is the smallest and fastest?
A) L1 Cache
B) L2 Cache
C) L3 Cache
D) Main Memory
Answer: A
In which cycle of instruction execution does the CPU read an instruction from
memory?
A) Execute cycle
B) Fetch cycle
C) Decode cycle
D) Operand fetch cycle
Answer: B
Moore's law is primarily concerned with the increase in:
A) CPU clock speeds
B) Transistor density on a chip
C) Processor efficiency
D) Number of software programs
Answer: B
Which of the following components is responsible for temporarily holding data
being processed?
A) Registers
B) ALU
C) Cache
D) Control unit
Answer: A
Which interrupt type occurs due to errors in program execution?
A) I/O interrupt
B) Program interrupt
C) Timer interrupt
D) Hardware interrupt
Answer: B
The technique where an I/O device directly communicates with memory
bypassing the CPU is called:
A) Programmed I/O
B) Memory-mapped I/O
C) Direct Memory Access (DMA)
D) Interrupt-driven I/O
Answer: C
Which CPU register holds the address of the next instruction to be executed?
A) Accumulator
B) Program Counter (PC)
C) Memory Buffer Register (MBR)
D) Instruction Register (IR)
Answer: B
Which component of a CPU holds instructions to be decoded and executed?
A) Program Counter
B) Instruction Register
C) Memory Address Register
D) Control Unit
Answer: B
What does the term "Instruction Set Architecture" (ISA) refer to?
A) The physical design of the CPU
B) The control signals that govern data flow
C) The interface between hardware and software
D) The connections between the CPU and memory
Answer: C
What is the main advantage of using cache memory?
A) Increases the size of main memory
B) Decreases the cost of memory
C) Speeds up data access
D) Improves data security
Answer: C
Which of the following is a characteristic of RISC (Reduced Instruction Set
Computer) architecture?
A) Large number of instructions
B) Simple instructions with fast execution
C) Complex addressing modes
D) Multiple instruction types
Answer: B
21. Which of the following is an example of an instruction set architecture?
A) Harvard Architecture
B) x86
C) ASCII
D) DRAM
Answer: B
22. What is the significance of the "opcode" in an instruction?
A) It defines the operation to be performed.
B) It specifies the memory address of data.
C) It stores the result of an operation.
D) It determines the data type.
Answer: A
23. A processor has 16 registers, and a 32-bit instruction includes 6 bits for the
opcode. How many bits are required to specify two registers in this instruction
format?
A) 4 bits
B) 5 bits
C) 6 bits
D) 8 bits
Answer: D
24. In von Neumann architecture, the control unit is responsible for:
A) Storing data
B) Arithmetic operations
C) Fetching and decoding instructions
D) I/O operations
Answer: C
25. What is the main advantage of using a stack-based addressing mode in a
processor?
A) Reduces memory access time
B) Provides better access to registers
C) Simplifies function calls and returns
D) Increases instruction length
Answer: C
26. What happens when a computer using big-endian byte ordering stores the
value 0x12345678 in memory?
A) The byte 0x12 is stored at the highest address.
B) The byte 0x78 is stored at the lowest address.
C) The byte 0x12 is stored at the lowest address.
D) The byte 0x78 is stored at the highest address.
Answer: C
27. Which addressing mode involves the calculation of the effective address by
adding a constant value to the contents of a register?
A) Direct addressing
B) Indirect addressing
C) Displacement addressing
D) Immediate addressing
Answer: C
28. What is the primary trade-off when deciding between using many opcodes
versus many addressing modes in an instruction set architecture?
A) Power consumption vs. memory size
B) Instruction length vs. program complexity
C) Register space vs. execution speed
D) Memory access time vs. instruction fetch time
Answer: B
29. Consider a processor with a 32-bit instruction length. The opcode takes 6 bits,
and each register requires 5 bits. If two registers are involved, how many bits are
left for the immediate operand?
A) 10 bits
B) 16 bits
C) 11 bits
D) 16 bits
Answer: B
30. How is an operand specified in indirect addressing mode?
A) Operand is located in a register
B) Address field contains the operand
C) Operand is accessed via a pointer stored in memory
D) Operand is a constant
Answer: C
31. A CPU has 24 registers, and an instruction uses 32 bits. The opcode is 8 bits
long. If an instruction needs to specify three registers, how many bits are left for
other fields?
A) 16 bits
B) 8 bits
C) 12 bits
D) 6 bits
Answer: B
32. A machine has a 48-bit architecture. The memory contains 2^48 addressable
locations. What is the size of each memory address in bits?
A) 8 bits
B) 16 bits
C) 48 bits
D) 32 bits
Answer: C
33. If a program loops through an array of 1000 integers, which addressing mode
would be the most efficient for accessing array elements?
A) Immediate addressing
B) Direct addressing
C) Register indirect addressing
D) Indexed addressing
Answer: D
34. A CPU takes 2 clock cycles to fetch an instruction and 4 clock cycles to
execute it. If there are 500 instructions in a program, what is the total time to
execute the program, assuming no pipelining?
A) 1000 clock cycles
B) 3000 clock cycles
C) 2000 clock cycles
D) 4000 clock cycles
Answer: B
35. Which of the following statements is true about instruction pipelining?
A) It increases instruction execution time.
B) It decreases CPU clock speed.
C) It improves overall CPU throughput.
D) It reduces the number of opcodes required.
Answer: C
36. A 32-bit processor can address up to:
A) 2^16 memory locations
B) 2^32 memory locations
C) 2^48 memory locations
D) 2^64 memory locations
Answer: B
37. In a processor using load/store architecture, which of the following is true?
A) Data can be manipulated directly in memory.
B) Data must be loaded into registers before manipulation.
C) Memory operations are faster than register operations.
D) Only a single operand can be used in each instruction.
Answer: B
38. Which instruction type is responsible for modifying the sequence of execution
in a program?
A) Arithmetic instructions
B) Control instructions
C) I/O instructions
D) Data processing instructions
Answer: B
39. In a pipelined processor, a stall occurs when:
A) A data hazard is detected
B) All instructions are executed in parallel
C) The instruction fetch is faster than execution
D) The CPU reaches its maximum clock speed
Answer: A
