TITLE:

Accurate evaluation of interface

state density in SiC metal-oxide-
semiconductor structures using
surface potential based on
depletion capacitance

AUTHOR(S):

Yoshioka, Hironori; Nakamura, Takashi; Kimoto,

Tsunenobu

CITATION:
Yoshioka, Hironori ...[et al]. Accurate evaluation of interface state density in SiC metal-
oxide-semiconductor structures using surface potential based on depletion capacitance.
JOURNAL OF APPLIED PHYSICS 2012, 111(1): 014502.

ISSUE DATE:
2012-01-01

URL:
http://hdl.handle.net/2433/160637

RIGHT:
Copyright 2012 American Institute of Physics. This article may be downloaded for
personal use only. Any other use requires prior permission of the author and the
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Accurate evaluation of interface state density in SiC metal-oxide-

semiconductor structures using surface potential based on depletion
capacitance
Hironori Yoshioka, Takashi Nakamura, and Tsunenobu Kimoto

Citation: J. Appl. Phys. 111, 014502 (2012); doi: 10.1063/1.3673572

View online: http://dx.doi.org/10.1063/1.3673572
View Table of Contents: http://jap.aip.org/resource/1/JAPIAU/v111/i1
Published by the American Institute of Physics.

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JOURNAL OF APPLIED PHYSICS 111, 014502 (2012)

Accurate evaluation of interface state density in SiC

metal-oxide-semiconductor structures using surface
potential based on depletion capacitance
Hironori Yoshioka,1,a) Takashi Nakamura,2 and Tsunenobu Kimoto1,3
1
Department of Electronic Science and Engineering, Kyoto University, Kyoto 615-8510, Japan
2
New Material Devices R&D Center, Rohm Co. Ltd., Kyoto 615-8585, Japan
3
Photonics and Electronics Science and Engineering Center, Kyoto University, Kyoto 615-8510, Japan
(Received 5 October 2011; accepted 23 November 2011; published online 3 January 2012)
We propose a method to accurately determine the surface potential (wS) based on depletion
capacitance, and the interface state density (DIT) was evaluated based on the difference between
quasi-static and theoretical capacitances in SiC metal-oxide-semiconductor capacitors (CwS
method). We determined that this method gives accurate values for wS and DIT. From the frequency
dependence of the capacitance measured at up to 100 MHz, a significant fast-interface-state response
exists at 1 MHz, which results in the overestimation of wS if it is determined based on the flatband
capacitance at 1 MHz. The overestimation of wS directly affects the accuracy of the energy level. DIT
at a specific energy level is underestimated by the overestimation of wS. Furthermore, the fast interface
states that respond at 1 MHz cannot be detected by the conventional high(1 MHz)-low method. The
CwS method can accurately determine the interface state density including the fast states without
high-frequency measurements. V C 2012 American Institute of Physics. [doi:10.1063/1.3673572]

I. INTRODUCTION determined based on the flatband capacitance in high-

frequency measurements, assuming that the high-frequency
Silicon carbide (SiC) has been recognized as a promis-
capacitance does not include a contribution from the inter-
ing material for high-power devices because of its high
face states. If the probe frequency is not high enough, the
breakdown electric field. SiC power metal-oxide-semicon-
flatband capacitance contains a component of the fast inter-
ductor field effect transistors (MOSFETs) are SiC devices
face states leading to a large error in the surface potential.
that have been commercialized.1 SiC MOSFETs still suffer
The high-low and conductance methods also need an
from low channel mobility probably because of the high den-
accurate surface potential for an evaluation of the interface
sity of interface states. The interface state density is charac-
state density at a specific energy level. Interface state den-
terized by high-low or conductance methods with the
sities in SiC MOS structures, which were evaluated by high-
maximum frequency of 0.1  1 MHz.2–14 The existence of
low4–9 or conductance2,3 methods by different groups, are
fast interface states has been suggested15,16 but the fast inter-
widely distributed even though MOS capacitors undergoing
face states that respond to the maximum probe frequency are
similar processes can be compared. The variations are likely
undetectable by these methods. Although increasing the fre-
partly due to the use of an erroneous surface potential and it
quency is a method to detect fast states, very high-frequency
is important to establish an accurate and standard method to
measurements are not easily obtained because of series re-
determine the surface potential and interface state density.
sistance and inductance. A method based on the difference
In this study, we propose a method to accurately deter-
between quasi-static (low-frequency) and theoretical capaci-
mine the integration constant of the surface potential based
tance is valuable for the detection of fast interface states,17,18
on the depletion capacitance and to evaluate the interface
because measurements are not required at very high frequen-
state density in SiC MOS structures from the quasi-static and
cies. To accurately determine the interface states by this
theoretical capacitance. We refer to the proposed method as
method, a very accurate surface potential and theoretical ca-
the “CwS method” in this paper. Moreover, we increased
pacitance are needed. This may be the main reason why it
the maximum frequency in the high-low and conductance
has not been used for SiC MOS structures to date. The sur-
methods to 100 MHz using a system suitable for high fre-
face potential (wS) can be calculated from quasi-static and
quency measurements. The interface state densities eval-
oxide capacitances (CQS and COX) using17,18
uated by these methods are thus compared.
ð
wS ðVG Þ ¼ ð1  CQS =COX ÞdVG þ A: (1) II. SAMPLE PREPARATION AND MEASUREMENT
DETAILS
A certain ambiguity exists in the determination of the inte- The MOS capacitor that was characterized in this work
gration constant (A). For example, this constant is often consisted of a 32-nm-thick oxide formed by dry oxidation at
1300  C on an n-type 4 H-SiC (0001) epilayer. The SiC epi-
a)
Author to whom correspondence should be addressed. Electronic mail: layer was 8.4 lm thick and was doped with nitrogen to
[email protected]. 1.33  1016 cm3. The thickness and resistivity of the n-type

0021-8979/2012/111(1)/014502/5/$30.00 111, 014502-1 C 2012 American Institute of Physics

V

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014502-2 Yoshioka, Nakamura, and Kimoto J. Appl. Phys. 111, 014502 (2012)

SiC substrate were 335 lm and 0.022 Xcm, respectively. A cir-

cular Ni electrode (gate) with a diameter of 604 lm was used.
Measurements were carried out at room temperature
(T ¼ 304 K) in a dark box. The impedance was measured at
probe frequencies from 1 kHz to 100 MHz with an oscillation
voltage of 25 mV using Precision Impedance Analyzer
(4294 A, Agilent Technologies), which was connected to the
sample through a probe kit (42941 A, Agilent Technologies).
Using the probe kit, the probe and wire impedance can be
effectively eliminated, which greatly improves the accuracy
of the high frequency measurements. The quasi-static capaci-
tance was measured with a delay time of 0.1 s using Quasi-
static CV Meter (595, Keithley). The gate voltage was swept
from depletion (5 V) to accumulation (15 V) at a rate of
about 0.1 V/s for the voltage-sweep measurements.

III. EXPERIMENTAL RESULTS AND ANALYTICAL

PROCEDURE
A. C2V measurements
Figure 1(a) shows the quasi-static capacitance (CQS) and
the parallel-mode capacitance (CP) measured at different fre-
quencies for the fabricated SiC MOS capacitor. Figure 1(b)
shows the parallel-mode conductance (GP) measured at dif-
ferent frequencies. The existence of interface states can be
detected at about 1  2 V as the peak of conductance. Figure
2 shows equivalent circuits for (a) depletion to weak accu-
mulation and (b) strong accumulation where COX, CD, CIT,
GPIT, and Z are the oxide capacitance, the semiconductor FIG. 1. (a) Capacitance-voltage and (b) conductance-voltage characteristics
capacitance, the interface-state capacitance, the interface- of a n-type SiC MOS capacitor measured at different frequencies (parallel
mode). The quasi-static capacitance is also plotted in (a).
state conductance, and the series parasitic impedance,
respectively. For strong accumulation, CD, CIT, and GPIT can
be ignored because of the infinitely large CD, and the meas- and a linear relationship can be established between
ured CP and GP should be independent of gate voltage. At 1/(CD þ CIT)2 and wS,17,18
about 15 V, both CP and GP show very little change against 1 1 2wS
the gate voltage indicating that the MOS capacitor is in 2
 ¼ 2 ðdepletionÞ (2)
ðCD þ CIT Þ C2dep S eSiC eND
the strong-accumulation condition. However, CP and GP
changed significantly depending on the frequency, which is
where S (0.286 mm2) is the area of the gate electrode, eSiC
due to a change in the series parasitic impedance. Therefore,
(9.7e0) is the dielectric constant of SiC, and ND is the donor
the quasi-static capacitance at 15 V is assumed to be COX,
concentration of the SiC epilayer. Based on Eq. (2), the con-
and the values of Z(x) are determined for each frequency
stant A was determined so that the extrapolation of the
from the impedance measured at 15 V and COX, assuming
straight line should intersect the origin of the plot, as shown
strong accumulation (Fig. 2(b)).
in Fig. 3. The donor concentration was also determined from
the slope of the straight line (ND ¼ 1.33  1016 cm3).
B. Determination of the surface potential by the
C2ws method
Taking into account the COX and Z values, CD þ CIT at
less than 15 V can be determined by assuming the equivalent
circuit shown in Fig. 2(a). On the other hand, the surface
potential wS(VG) can be obtained using Eq. (1), except for
the integration constant A. The integration constant A can
be uniquely determined, as shown in Fig. 3, where
1/(CD þ CIT)2 is plotted against wS. In Fig. 3, a linear correla-
tion is evident for the sufficiently negative wS (depletion
region). At a sufficiently high frequency and upon depletion, FIG. 2. Equivalent circuits for a MOS capacitor in (a) depletion to weak
accumulation and (b) strong accumulation where COX, CD, CIT, GPIT, and Z
the interface states do not respond and no inversion carriers are the oxide capacitance, the semiconductor capacitance, the interface-state
are generated at the SiC MOS interface. Therefore, CD þ CIT capacitance, the interface-state conductance, and the series parasitic imped-
can be approximated as the depletion capacitance (Cdep) ance, respectively.

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014502-3 Yoshioka, Nakamura, and Kimoto J. Appl. Phys. 111, 014502 (2012)

ðCD þ CIT ÞQS  CD;theory

DIT ¼ ; (4)
Se2
where (CD þ CIT)QS is the CD þ CIT measured under quasi-
static conditions.

D. Evaluation of the interface state density by the

high-low method
For the high-low method, the interface state density is
given by17,18

ðCD þ CIT ÞQS  ðCD þ CIT ÞHF

DIT ¼ ; (5)
Se2
where (CD þ CIT)HF is the CD þ CIT measured at high fre-
FIG. 3. 1/(CD þ CIT)2 versus surface potential wS for depletion at various
frequencies of a n-type SiC MOS capacitor, which was determined from the
quency and is assumed to be CD. Because CD þ CIT approaches
results given in Fig. 1. CD,theory with an increase in the frequency, as shown in Fig. 4,
using (CD þ CIT)HF at higher frequency gives a more accu-
C. Evaluation of interface state density in the C2ws rate interface state density. Therefore, we used (CD þ CIT)HF
method at 100 MHz while a (CD þ CIT)HF of 0.1  1 MHz is usually
used in the conventional high-low method.
Using the obtained surface potential, the theoretical
semiconductor capacitance (CD,theory) can be calculated E. Evaluation of the interface state density by the
by17,18 conductance method
   
  Figure 5(a) shows the frequency dependence of GPIT/x
SeND exp ew kT
S
 1 
CD;theory ðwS Þ ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
n   o; (3) at various surface potentials. Bell-shaped peaks originate
2kTND ewS
exp kT  kT  1 ewS from the interface states, and the interface state density is
eSiC
related to GPIT/x by10,17
 
assuming that there are no holes in the n-type SiC. Figure 4 ð þ1 ln 1 þ ðxs expðgÞÞ2
shows the CD þ CIT values plotted against wS at different fre- GPIT =x ¼ e2 SDIT
quencies, where the CD,theory calculated from Eq. (3) is also 1 2xs expðgÞ
 
plotted. The measured CD þ CIT approached CD,theory with an 1 g2
increase in the frequency because the carriers trapped at the  pffiffiffiffiffiffiffiffiffiffi exp  2 dg; (6)
2pr2 2r
interface states hardly respond to a sufficiently high frequency
(CIT  0). A significant difference exists between CD þ CIT at where the interface state density (DIT), the time constant of
1 MHz and CD,theory indicating that a significant portion of the the interface states (s), and the standard deviation (r) are fit-
fast interface states respond at 1 MHz. In contrast, 100 MHz ting parameters. The bold lines in Fig. 5(a) are GPIT/x calcu-
seems to be almost sufficient for the interface carriers not to lated from Eq. (6) to fit the experimental results. It is noted
respond. The interface state density is given by17,18 that the measurement at up to about 10 MHz is necessary to
fit correctly because the peaks exist up to about 1 MHz. The
values of s and r obtained by fitting are shown in Fig. 5(b)
where EC  ET was calculated by

EC  ET ¼ eð0:19V  wS Þ; (7)

taking into account the Fermi level of the SiC epilayer

(EC  0.19 eV). The values of s and r are reasonable com-
pared to earlier reports.10,19,20

IV. DISCUSSION
Figure 6 shows the interface state densities obtained by
the CwS method (CwS), the high-low method using a
high frequency of 100 MHz (high100MlowwS), and the
conductance method (conductancewS), where the ECET
of the horizontal axis was calculated from Eq. (7) using the
FIG. 4. CD þ CIT versus surface potential wS at various frequencies for a n-
surface potential determined by the proposed method. The
type SiC MOS capacitor, which was determined from the results given in use of the correct surface potential is denoted by adding
Fig. 1. The theoretical semiconductor capacitance CD,theory is also plotted. the term “wS.” The DIT distribution obtained by the CwS

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014502-4 Yoshioka, Nakamura, and Kimoto J. Appl. Phys. 111, 014502 (2012)

method underestimated the density 2  3 times because of

the following two factors. First, the fast interface states that
respond to higher than 1 MHz are not detected. Second, the
surface potential error results in an error of ECET.
For the conventional high-low method, the integration
constant of the surface potential was determined so that the
surface potential is zero at the gate voltage at which the
capacitance of 1 MHz is equal to the theoretical flatband-
capacitance. If the conventional method is employed, the
integration constant is erroneously determined because the
capacitance of 1 MHz includes CIT. The surface potential
determined by the conventional method was overestimated
by 0.077 V for the MOS capacitor characterized in this study,

wS ðconventionalÞ ¼ wS ðproposedÞ þ 0:077V; (8)

which results in the underestimation of ECET,

EC  ET ðconventionalÞ ¼ EC  ET ðproposedÞ  0:077 eV:

(9)

Because the interface state density of the SiC MOS struc-

tures increases exponentially toward the conduction band
edge, a small shift in ECET results in a large change in the
interface state density at specific energy levels. Therefore,
the correct determination of the surface potential and ECET
is very important.
FIG. 5. (a) Interface-state conductance GPIT normalized by angular fre-
quency x at various surface potentials wS, where the symbols are experi- It should be emphasized that the CwS method is supe-
mental results and the bold lines are theoretical results fitted to the rior to the other methods from two points of view. First, the
experimental results. (b) Time constant s and standard deviation r obtained CwS method can detect fast interface states without fre-
by fitting GPIT/x. quency limits. Second, the CwS method requires simple
measurements as only capacitance measurements with one
method agrees very well with that by the conductancewS voltage sweep is enough, while the conductance method
method indicating the validity of the proposed method. needs more time-consuming Gf measurements at different
The surface potential and the theoretical semiconductor voltages. The CwS method can be applied to not only SiC
capacitance (CD,theory) were correctly determined. The MOS structures but also other metal-insulator-semiconductor
high100M  lowwS method also gave an accurate interface structures. The requirements are that the doping concentra-
state density because 100 MHz was almost sufficient for the tion (ND) is uniform near the MOS interface and no inversion
fast states not to respond. (minority) carriers are collected at the interface.
The DIT distribution obtained by the conventional high-
low method using a high frequency of 1 MHz, which was
evaluated by the surface potential determined by a conven- V. CONCLUSIONS
tional method (refer to the next paragraph), is also plotted in We propose a method to accurately determine the sur-
Fig. 6 (conventional high-low). The conventional high-low face potential based on depletion capacitance and evaluated
the interface state density based on the difference between
quasi-static and theoretical capacitances in SiC MOS capaci-
tors (CwS method). We confirmed by an agreement with
the conductance methods that the proposed method gives an
accurate surface potential and interface state density. Signifi-
cant fast-interface-states exist that respond to 1 MHz, which
results in an overestimation of the surface potential if it is
determined by the flatband capacitance of 1 MHz. The over-
estimation of surface potential results in the interface state
density at a specific energy level being underestimated by
the underestimation of ECET. The high-low method using a
high frequency of 1 MHz underestimated the interface state
density because the fast interface states cannot be detected.
The high-low method using a high frequency of 100 MHz
FIG. 6. Distributions of the interface state density evaluated by various gave an accurate interface state density because 100 MHz is
methods for the same n-type SiC MOS capacitor. almost sufficient for the fast states not to respond.

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014502-5 Yoshioka, Nakamura, and Kimoto J. Appl. Phys. 111, 014502 (2012)

5
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