IC低功耗设计技术概览

─ 2023微电之光芯片低功耗设计系列课程
—2023微电之光芯片低功耗设计系列课程

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 讲师介绍

操亚华
联发科技（合肥）有限公司 芯片设计部门 技术经理
拥有超过8年的芯片设计整合经验
熟悉RTL->GDSII芯片设计及实现流程
擅长芯片开发中低功耗相关规划, 设计及实现流程

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 课时安排
课程内容：IC系统设计之低功耗的挑战及设计方法 授课形式

Day 1 (10/16): 软件系统的功耗分析与优化

1 MTK智能设备电源管理概述 方兴 (13:30~14:10, 40mins) 面授

2 MTK低功耗软件技术探讨 方兴 (14:20~15:00, 40mins) 面授

Day 1 (10/16): IC模拟设计中的低功耗技术

1 SerDes Trends and Key Technologies In Consumer Electronics 马昭鑫 (15:20~16:00, 40mins) 面授

2 Reliability and ESD Introduction 马昭鑫 (16:10~16:50, 40mins) 面授

Day 2 (10/17): IC低功耗技术概览及UPF简介

1 IC低功耗设计技术概览 操亚华 (9:30~10:20, 50mins) 面授

2 IC 低功耗设计之UPF简介 操亚华 (10:30~11:20, 50mins) 面授

Day 2 (10/17): IC低功耗设计的静态规则检查和动态仿真验证

1 基于CLP的IC低功耗设计规则的静态检查 陈飞 (14:00~14:50, 50mins) 面授

2 MVSim在IC低功耗动态验证中的应用 马健 (15:00~15:50, 50mins) 面授

Day 3 (10/18): IC 低功耗设计Training Lab

1 IC低功耗设计Training Lab (练习) 操亚华/马健/陈飞 9:00~12:00, 180mins) 面授

2 Training Ending (结业评比, 培训调查表…) TBD (12:00~12:30, 30mins) 面授

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 Agenda

High Demands of Low Power

Low Power Design Techniques Overview

Low Power Design Flow Introduction

Summary

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 High Demands of Low Power

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 Mediatek Dimensity 9200

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 高耗电: 运算服务器

2021：
中国数据中心耗电量：2166亿Kwh
三峡大坝一年发电量：1036亿Kwh

中国移动 在中国贵州的数据中心
2023 Copyright © MediaTek Inc. All rights reserved. Facebook 在美国俄勒冈州的数据中心 7
 低功耗: 物联网

2023 Copyright © MediaTek Inc. All rights reserved. 联发科技占据70%共享单车芯片市场份额 8

 Moore’s Law and IC Scaling
◆ In 1965 Moore’s law was observed, according to which the number of transistors in ICs
doubles every 18 months
◆ At present, the number of transistors in ICs has reached dozens of billions
◆ Moore's law will cease to apply? Never stop innovating!

20um

10um

5um

2um

1um

0.25um

0.18um

0.13um

90nm

65nm

45nm

32nm
28nm
22nm FinFET!!!
20nm
14nm
7nm
5nm
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 IC Scaling Impact on Power Density

Watts/cm2
1000

Sun’s
Intel* core* I7 Processor® Surface
Intel* core* I5 Processor®
Atom® Rocket
100
water cooling > $100 Nuclear Nozzle
Itanium®
2

air cooling  $10 Reactor

Xeon®
Pentium® 4
Pentium® III
10
Pentium® II
Pentium® Pro
Pentium®
i486
i386
1
500nm 350nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm 14nm 7nm 5nm

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 Power Consumption Affected Problems
Low Power Power Efficiency Reliability

<90nm
Technology
Application

• Wireless • Microprocessors • All design<90nm

• Handheld • Graphics/multimedia
• Embedded systems • Networking/telecom
Concern

Battery life Thermal management Leakage power

Leakage power Packaging, cooling IR-drop
Dynamic power cost Electromigration

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 High Demands of Low Power

Consumer Demand Performance and Reliability Thermal Management

• Longer battery lifetime • 25C -> 105C loss of 30% performance • Package cost
• Less heat • Junction temp> 125c quickly reduces • Cooling cost
device reliability

Low Power is also a way for Low-Carbon Life

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 IC Design Challenges

Timing closure 49%

Power management 45%
Meeting timing and area goals 37%
Performance Tapeout on schedule 33%
Power estimation at the RTL level 20%
Generation and validation of… 19%
Analog/mixed-signal implementation 15%
IP integration 14%
Power Reducing time for sign-off physical verification 13%
Signal integrity 13%
IR drop 10%
Implementing ECOs 8%
Increasing yield 7%
Area Equivalence checking 4%
Meeting manufacturing test goals 3%
Other 2%
0% 10% 20% 30% 40% 50% 60%

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 Low Power Design Technology

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 Low Power Design Approach
System Design
algorithms, IP...

Architecture
Design multi-voltage islands, sleep mode...

Implementation RTL Synthesis

clock gating, multi-Vt

Physical Implementation
clock tree, gate-level

Production
Power reduction percentage
tapers down further in the • Power analysis must be considered very early in the
flow design cycle. Typically, 80% of a chip’s power can be
determined at the RTL stage or before
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 Power Consumption Sources
Power

1.Dynamic 2.Static (Leakage)

Isw
IInt
Cload ILeakage

1.1.Switching 1.2.Short Circuit 2.1.Gate Oxide 2.2..Sub Threshold

Isw
IInt
Igate oxide
Cload Cload Isubtreshold

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 Power Consumption Sources
— Dynamic Power

▪ Dissipated when the circuit is active

▪ Consist of Switching Power and Internal Power
— charging and discharging of the load capacitance at the output of the cell
— charging or discharging of capacitances internal to the cell during switching
— momentary short circuit between the P and N transistors of a gate while both are turned on

Pdyn = a.f.Ceff .Vdd2 + Isc .Vdd.f

▪ Switching Power
 Minimize activity
 Reduce effective capacitance
 Lower supply voltage
 Reduce Frequency
▪ Internal Power
• Avoid slow input slew

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 Power Consumption Sources
— Static Power (Leakage Power)

▪ Dissipated by a cell when it is not switching

▪ Primary Components
— Subthreshold leakage: transistors don’t turn off completely
— Gate-oxide tunneling current: electrons tunneling across gate oxide
— Reverse biased junction leakage current: leakage between the diffusion layers and the substrate

Plkg = F(Vdd, Vth, W/L)

▪ Leakage Power
• Use high voltage threshold cell
• Proportional to device width
• Drops with increasing channel length

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 Power Reduction Methods
▪ Basic Techniques
Clock Gating Operand Isolation Gate-level Power Optimization Multi-Threshold

Leakage Current
a a Low V TH
EN b c
FF
LT c b
CLK ICG d d Nominal V TH
High V TH
Delay

▪ Advanced Techniques

Multi-Voltage (MV) MTCMOS Power Gating Dynamic Voltage &

(Shutdown) Frequency Scaling
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 Clock Gating
― A very simple and readily available technique to reduce power and area
― Stop the clock of those sequential elements whose data is not toggling

▪ Enable flops are optimized into a clock gating structure

▪ Saving mux area and reducing the overall switching
activity of the clock net
▪ No change to RTL, simple to implement
▪ Rely on the logic synthesis tool to perform this
optimization

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 Operand Isolation
▪ Shut down (isolate) the function unit (operand) when its results are not used
▪ No dynamic power is dissipated when the result of the multiplier is not needed

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 Vector Driven Dynamic Optimization
Combinational dynamic power taking an important role on total power
– Combinational power: 15%~51% of total power
– If consider glitch(non-stable state transition), combinational power becomes 2~3X

Resize gates or move a high-activity signal later Reconnect nets to match high-activity nets to the
in a path so that it affects fewer gates when it pins with lesser capacitance
switches

Use complex gates to consume a high-frequency Selectively buffering certain critical paths to
net within a complex gate as shown here improve input slew which can reduce dynamic
power dissipation
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 Multi-VT
Threshold Vt Cell Delay(ps) Leakage Power(nW)
Ultra high Vt (uHVt) 46.9 0.146
High Vt (HVt) 36.7 0.667
Standard Vt (SVt) 26.4 1.99
Low Vt (LVt) 18.9 12.15
Ultra low Vt (uLVt) 17.1 41.2

Delay vs Leakage for different Vt of 32nm

Low-Vth cells on timing critical paths

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 Multi Voltage
▪ Lowering the voltage has a squared effect on active power consumption
▪ Use different supply voltages for different blocks of the chip based on their
performance requirements

— Extra IO pins to supply the different power rails

— More complex power grid SOC
0.9V
— Need level shifters on signals operating at
different voltages

LS

LS
LS

LS
LS
CPU CACHE RAMS
1.0V LS 1.2V

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 DVFS (Dynamic Voltage & Frequency Scaling)
▪ Reducing the supply voltage and clock frequency based on workload

— Requires a multilevel power supply

— Need a logic block to determine the best
voltage level to use for a given task
— More challenges in design, implementation,
verification, and testing
DVS DVFS

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 Power Gating
▪ Power reduction technique to save leakage power by shutting off, or power
down unnecessary logics

ARM
— Design of power gating controller ARMv8 Context A53
— Need isolation cell on the output of shut I- D-
down block Cache Cache Core0
1
23
— Some important information may need ACP SCU L2 w/ECC
retention PM
128 -bit AMBA ACE Bus
U

RR RR

GPU Display

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 Power Reduction Techniques Summary

Power Methodology Impact

Power Timing
reduction Area Penalty
Benefit Penalty
technique Architecture Design Verification Implementation

Multi-VT
Medium Little Little Low Low Low Low
Optimization

Clock Gating Medium Little Little Low Low None Low

Multi-Voltage Large Some Little High Medium Low Medium

MTCMOS
Huge Some Some High High High High
Power Gating

DVFS Large Some Some High High High High

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 Low Power Design Flow Introduction

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 Low Power Design Flow Overview

Verification
Power Intent with
SPEC a Power Implementation GDSII
Specification File
Design

• Define power architecture early in the design flow

• Preserve the power intent through the entire design flow
─ Verification: Comprehensive low-power simulation and formal verification
─ Design: Power-aware synthesis, equivalence checking, and design for test(DFT)
─ Implementation: Automated power-aware physical implementation
─ Signoff: Ensure the power intent is correct and preserved through the flow

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 Low Power Design Verification

▪ Power aware simulation

— Give stimulus and measures the response Test bench RTL or Gate Power Intent
Level Netlist (UPF)
— Generally, target on RTL design
▪ Low power structure checking
— Ensure design is implemented the way the
designers think it is
— Full-chip verification of designs optimized for VCS-NLP Verdi PA CLP
low power
Reports Reports
Log files Log files
FSDB
Dynamic Simulation Static Checking

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 Power Analysis
Design Phase
Design RTL Synthesis Netlist Post-Layout Netlist
Parasitic WL DCG.spef ICC.spef StarRC.spef
CTS No CTS CTS

• RTL stage:
Faster feedback to improve design and finding early on power bugs (e.g
Design
Data clock gating efficiency)
• Synthesis netlist:
Gap in power related to capacitance, clock tree power can be improved
Turn with calibration, but should not be used as reference for signoff
around
Time (TaT) • Post-layout Netlist:
Most accurate power, but due to long TaT too slow to give timely
Accuracy feedback to optimize design

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*Involved Tools: PowerArtist / PrimePower 31
 Low Power Design Implementation

▪ Multiple power domains in Multi-Voltage and Power Gating techniques require the insertion, placement, and
connection of specialized power structures
─ Power domains must be shaped and placed
─ Power pads and switches must be placed and optimized
─ Power grid synthesis, power plane implementation, and insertion of level shifters, switch cells, isolation cells,
and state-retention cells
─ Power routing must be planned
2023 Copyright © MediaTek Inc. All rights reserved. *Involved Tools: Genus/Innovus, Fusion Compiler/IC Compiler2 32
 Power Signoff
IR drop: Voltage drop on the power network
• Static IR drop
• Dynamic IR drop
• Impact timing, function and power
Electromigration: Electromigration is the movement of atoms based on the flow of current through a material
• Decreases the reliability of chips

High current from factory

low voltage

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 Summary

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 Summary

▪ Summarizes the various low-power design techniques commonly

used by designers today
▪ Provides an in-depth look the design, implementation, and
verification tools and flows and methodologies

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 Low Power Methodology Manual
Moving Aggressive Power Management Into the Mainstream

• Based on extensive experience & silicon technology

demonstrators with real data
• Balanced: theory ↔practical
• Supports industry standards

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 INTERNAL USE
Thank you
Questions and Discussions

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