Introduction to

CMOS VLSI
Design

MOS devices: static and

dynamic behavior
 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase decrease not change
MOS equations CMOS VLSI Design Slide 2
 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum
transistor current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase decrease not change
MOS equations CMOS VLSI Design Slide 3
 DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

MOS equations CMOS VLSI Design Slide 4

 Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

MOS equations CMOS VLSI Design Slide 5

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn

MOS equations CMOS VLSI Design Slide 6

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout
Idsn

MOS equations CMOS VLSI Design Slide 7

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

MOS equations CMOS VLSI Design Slide 8

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

MOS equations CMOS VLSI Design Slide 9

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn

MOS equations CMOS VLSI Design Slide 10

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn

MOS equations CMOS VLSI Design Slide 11

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

MOS equations CMOS VLSI Design Slide 12

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

MOS equations CMOS VLSI Design Slide 13

 I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp
Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

MOS equations CMOS VLSI Design Slide 14

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

MOS equations CMOS VLSI Design Slide 15

 Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn

VDD
Vout

MOS equations CMOS VLSI Design Slide 16

 Load Line Analysis
 Vin = 0

Vin0

Idsn, |Idsp|

Vin0
VDD
Vout

MOS equations CMOS VLSI Design Slide 17

 Load Line Analysis
 Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout

MOS equations CMOS VLSI Design Slide 18

 Load Line Analysis
 Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout

MOS equations CMOS VLSI Design Slide 19

 Load Line Analysis
 Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

MOS equations CMOS VLSI Design Slide 20

 Load Line Analysis
 Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout

MOS equations CMOS VLSI Design Slide 21

 Load Line Analysis
 Vin = VDD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

MOS equations CMOS VLSI Design Slide 22

 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

MOS equations CMOS VLSI Design Slide 23

 DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

MOS equations CMOS VLSI Design Slide 24

 Operating Regions
 Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A
Vout
B C
C
D D
E
0
E Vtn VDD/2 VDD+Vtp
VDD
Vin

MOS equations CMOS VLSI Design Slide 25

 Operating Regions
 Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin

MOS equations CMOS VLSI Design Slide 26

 Beta Ratio
 If bp / bn  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
p
 10
n
Vout 2
1
0.5
p
 0.1
n

0
VDD
Vin

MOS equations CMOS VLSI Design Slide 27