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LAB 7

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meera naaj
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52 views4 pages

LAB 7

Uploaded by

meera naaj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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German Jordanian University

School of Electrical Engineering and Information Technology


Department of Computer Engineering
CE2120-Digital Systems Lab
Lab 6
Name: Meera Mohammed
ID: 20219302057

I. Preparations:
1. Consider the logic diagram below for a circuit that adds 3 bits (X, Y, Cin) and
produces two outputs (S, Cout).

Figure 1: Full adder

a. Fill the truth table for the full adder.

X Y Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
German Jordanian University
School of Electrical Engineering and Information Technology
Department of Computer Engineering

b. From the circuit, derive the Boolean expression that describes each
output (S and Cout) in terms of the inputs (X, Y, and Cin).

S=X ⊕ Y ⊕ Cin
Cout=(X⋅Y)+(Y⋅Cin)+(X⋅Cin)

2. A 2n :1 MUX has 2n data input, n control input, and 1 data output. It selects one of the data
inputs and connects to its output depending on the value of the control input.
a. Design a 2:1 MUX using logic gates.

F= D0.S’ + D1.S

b. Build a 4:1 MUX which has 4 data inputs, 2 control inputs, and 1 output
using an appropriate number of the 2:1 MUX(s) you have designed in
part (a).

F= X3.C0.C1 + X2.C0’.C1 + X1.C0.C1’ + X0.C0’.C1’


F= C1(X3.C0 + X2.C0’) + C1’(X1.C0 + X0.C0’)
German Jordanian University
School of Electrical Engineering and Information Technology
Department of Computer Engineering

C0 C1 F
0 0 X0
0 1 X2
1 0 X1
1 1 X3

For each part, show the truth table and provide a Boolean expression for the MUX output. Also, draw
the logic circuit for each part.

3. An n :1 multiplexer can be used to implement a logic function with (n+1) variables without
additional gates. Implement the function F using a 4:1 MUX (74LS153)

F (X,Y,Z) = X’Z’ +X’YZ +XY’Z

Show the design of your logic circuit and obtain the truth table for this function.

X Y Z F F(Z)
0 0 0 1 Z’
0 0 1 0 Z’
0 1 0 1 1
0 1 1 1 1
1 0 0 0 Z
1 0 1 1 Z
1 1 0 0 0
1 1 1 0 0
German Jordanian University
School of Electrical Engineering and Information Technology
Department of Computer Engineering

4. Design a 3:8 decoder using 2:4 decoders (74LS139). Provide the truth table and the logic
circuit of your design

X Y Z I0 I1 I2 I3 I4 I5 I6 I7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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