oe x I Chalapathi Institute of Engineering & Technology (Autonomous) == Chalapathi Nagar, Lam - 522034, Guntur District, AP. I ppject Code: R20/ ECE - 213 JVIV B.Tech I Semester Regular Examinations, March-2022 SWITCHING THEORY AND LOGIC DESIGN (ECE Only) ‘shoe: 3 Hours Maximaum Marks: 70 er question no.1 from Part— A compulsory. Each question carries one mark 10x1=10M one question from each unit in Part-B. Each question carries 12marks 5x12 = 60M ~ PART -A ‘BL [| CO | Marks [a | Find binary equivalent of (B4D)ig Li_|cor{ iM le ‘What are the properties of XOR gates? Lr |co1| 1M © | Draw the logic circuit for Y=AB'C+ABC [-_[a | Draw the logie diagram of full subtractor e | Draw the truth table for positive edge trigzered JK flip flop [f | How many flip flops are required to design MOD- 10 counter? le h i i PART-B UNIT-1 2 |a | Convert (2022)0t0( 7 Ja (2 Ya( ? dis Define state diagram. ‘What is a synchronous sequential circuit? “Apply the 1°s complement and 2°s complement method for given subtraction operation (1000110101), - (0111001001) — ‘What is the major limitation of an FSM?. Define Moore model for a sequential circuit? + OR 3 |q | Convert the following numbers t6 decimal (.625.736)s Gi) (10111100), Gi) B4D)is. col] oM Simplify the equation Y=(A' + B+ C)(A +B +C) using Boolean ap > | algebra and draw the corresponding logic circuit. [44 foot ‘_ : UNIT-1 4 | | Simplify the following Boolean function using K-map method, F(AB,C,D) =. m(1,2,3,6,8,9,10,12,13,14) 12 | coz Construct a full-adder with two half-adders and basic gates. ‘Tas [oa : OR Make use of K-map technique to reduce “T F(A,B,C,D)=IIM(L,2,3,5,6,7;8:9,12,13)hor" vr Aeon CE -213 ‘halapathi Institut, i * Chala cytes Engineering & Technology (Autonomous) Pathi Nagar, Lam - $22034, Guntur District, AP. jet Cade: R20 / ECE ~213 JIIV B.Tech IS SWircanes et Supply Examinations, July-2022 THEORY AND LOGIC DESIGN (ECE Only) eS Hours Maximum Marks: 70 question no.1 from Part~ A compulsory. Each questi =10M Seguin fomechuintareREan fee ae siaeet OATS PART -A BL | CO | Marks 7 Ta | Find the decimal equivalent of (10101); Li} cor] IM | |b | Mention one method each for error detecting and correcting codes? | LI cor] 1M ¢ [Draw the logic circuit for Y-(A"+B+)(A+B+C) Li | co2] 1M [a] Draw the logic diagram of fall adder, Ti | coz] 1M |} Te [Draw the truth table for D flip flop Li | co3s| IM |]]TE | What is race around condition in JK flip flop? Li [cos] IM ||] Te | Define sequence detector. ||] [Whats the use of party bit generator? |||] | Wet ae the blocks in ASM chart? IIT [i [Define Mealy model fora sequential crouit? _ Li [cos] IM It PART=B : | BE | CO | Mans \ = UNIT -I i ‘Convert the following numbers to hexadecimal | 218] @ 101012 i) 65535)10 Gi) 4673) Li |co1} 6M IT Design a logic cireuit that produces a high output whenever the ies » | equivalent decimal input is greater than 12, The digital system hes 2| 12 |Co1| 6M 4-bit input from 0000 to 1111. ' OR 5 Ja | S2Ne the following Boolean finction to & minimum number of] IE [* [literals F(A, B, ©) = 5(1,4,5,6,7). cor) 6M Wentify the dual and complement of the following fimnction: | 5] app'+B(C+ D)+A'C _ | 13 |eor) ow UNIT-0 14 |, [Develop the fimetion Fw, # ». 2) = (13,711.13), which has the te don’t care conditions aw, x,y, 2) = (02.5) using Kamaugh map 13 }coz) om | |p | Constmiet the Togic diagram of a 3 to 8 line decoder with enable input) 15 | Co Ty ~~L_|and explain its operation with the help of truth table. A. Page 1 of2/ OR Develop the following Boolean expression using K-map ang/~——~ | 5 | | implement t by using NOR gates. LB L F(A,B,CD) = AB’C’ + AC+A’CD’ _ Coy Make use of 4X1 multiplexer and external gates to implement the b | following Boolean function 13 ay F(A, B,C, D-XA(1, 3,4, 11, 12, 13, 14, 15). Cy ‘UNIT =I 6 [2 | Compare combinational and sequential circuits. Bea p | Liste different types of esters? Explain the Parallel Input Serial = [ rH Output shift register. 1H | cos : OR — 7 _|a | Explain about shift registers. L2 [co “Analyze the circuit diagram of FX fip flop with NAND gates with b | positive edge triggering and explain its operation with the help of trth | L2 | co3 table. How race around condition is eliminated. UNIT-1V ‘| 8 | a | Explain about sequence detector with an example. 12 | cou) b | Design a3 bit parity generator. 12 | cor OR 9 [a [Design a sequence detector which detects the sequence 0111. 12 [cor b, | Explain about synthesis of synchronous sequential ciruits. 12 [cos UNIT-V 10 | [Compare Mealy and Moore machines. 12 [cos Build the following Moore machine into a corresponding Mealy Machine: PS |S. Zz X=0 _Xsi A |D Bit A BTA _E-Jo] 13 | Cos Cla Ee 1) pic A |0 EJF DB io FF 1 L me OR 11 [a-| Explain sbout incompletely specified sequential machines with an] 1 | cos | example, L} b | Explain about partition technique with an example, "i 12 [cos ee ‘Page 2of2[answer question no.1 from Part — ppject ‘Code: R20/ ECE_313 22034, Guntur District, ap. HAV B.Tech I Semester R Pek ae : ul SWITCHING THEQR ss 'D LOGIC 3 tine: 3 Hours CE Oniy) oe minations, December-2022 A oc Maximum Marks: 70 aswer one question from each unit fr Pare grace Gvestion carries one mark 10x 1= 10 M ~ Each question carries 12marke Sx12= 60M s PART-A 8 _| Draw the logic symbol and truth table of NAND. = b | What is a Logic gate? : ie . = IM ¢ | Write the advantages of Tabulation method over K-Map method. IM bs | What is priority encoder? Mention its Operation ; ¢ | Differentiate a Latch with a Flip flop. 7 Give th is nati + [| & ive te comparison between ‘combinational circuits and sequential IM g | How many flip flops are required to desigti MOD-05 counter 1M h | Define mealy machines? 1M i_| Define in brief minimal cover table, 1M j_| What is Merger chart method? 1M PART-B Marks 5 UNIT-1 Solve the following using BCD arithmetic 6M (i) (79)10 + (17710 _Gix(48 1) 10 + (178)10 Write the Rules for subtraction using I's and 2's compliment with wi example -OR Subtract the given binary numbers 111001-1010 by using 2s 6M complement form. b | Explain about error detection and error correction codes ™ UNIT -1I What is meant by half adder and full adder explain with circuit diagram 6M Design a conibinational circuit for 2-bit magnitude comparator Mt. 1 | Design a conibinational circuit for 2-bit magnitude comp__—_—— Geral eo binary encoder

| Conver the given desimal number 351 to binary, oot, hexadecimal and | BCD equivalent. ; OR a | Convert following numbers (1) (2387) )io 2) L010111101)»= ¢ yes} L p | Solve the following by using k-map 4 | (A.B.CD) 3m 3,7,10,1, 14,15)? | i UNIT = | Ta | What is decoder and design 2x4 and 3x8/decader ] (Po [What is mux and design @xl mux : Soca | + - Aeee Page 2 of 3 5 [a | Design & implemeiit Full Adder using Decoder. mi a {4 b | Construct a 2-bit comparator using logic gates. B lel i UNIT-I 7 6 | | Dia the Johnson counter and explain the operation with relevant out] 7" wave form 1} co_ b | Explain the operation of SISO and SIPO registers with neat logic niet diagram |} cor oR 7 7 |a | Design D Flip Flop by using SR Flip Flop and draw the timing diagram. | Lé Jog) bp | What is race around problem in JK Flip-Flop? Explain how itis lal eliminated in master slave JK Flop-Flop. oH UNIT-IV ] 8 | | Provide the analysis of synchronous Sequential circuits in detail. 14] oy | Interpret the detailed procedure for Design of synchronous modulo N— b 15 con counters. | OR | Prepare state diagram for given state table? | Present | NextState [Present Output | State ie eet zt 2 | 10 | x=0 x21] x=0 | a 0 fo o fo 2 L1 | col a fo | oa | ee | 7 ECan a ee eee _| Draw the merger table and graph for given state table? \ PS SSSS*C*UNS, i a | B uu ll c | D | E | fF }UNIT-V ‘Wit an éxample demonstrate the Merger thart methods in detail. £2|COS| 6M Explain the importance ith ees iM open ce ap (of Mealy and Moore models with necessary [15] co5| ont | OR 1 Define ASM? Draw ASM chart for a sequence to detect 010 12|cos| 6M ] Prepare the circuit by using the state diagram given below by using D- | ip flop Li} Cos} 6M Page 30f3