The Typical Embedded System

FPGA/ASIC/DSP/SoC
Microprocessor/controller Embedded
Firmware

Memory

Communication Interface

System
I/p Ports Core O/p Ports
(Sensors)
(Actuators)

Other supporting
Integrated Circuits &
subsystems

Embedded System

Real World 1
 The Typical Embedded System

The Core of the Embedded Systems

The core of the embedded system falls into any one of the following
categories.

 General Purpose and Domain Specific Processors

Microprocessors
Microcontrollers
Digital Signal Processors
 Programmable Logic Devices (PLDs)
 Application Specific Integrated Circuits (ASICs)
 Commercial off the shelf Components (COTS) 2
 The Typical Embedded System

General Purpose Processor (GPP) Vs Application Specific Instruction Set Processor

(ASIP)

 General Purpose Processor or GPP is a processor designed for general computational tasks
 GPPs are produced in large volumes and targeting the general market. Due to the high volume
production, the per unit cost for a chip is low compared to ASIC or other specific ICs
 A typical general purpose processor contains an Arithmetic and Logic Unit (ALU) and Control Unit
(CU)
 Application Specific Instruction Set processors (ASIPs) are processors with architecture and
instruction set optimized to specific domain/application requirements like Network processing,
Automotive, Telecom, media applications, digital signal processing, control applications etc.
 ASIPs fill the architectural spectrum between General Purpose Processors and Application Specific
Integrated Circuits (ASICs)
 The need for an ASIP arises when the traditional general purpose processor are unable to meet the
increasing application needs
 Some Microcontrollers (like Automotive AVR, USB AVR from Atmel), System on Chips, Digital
Signal Processors etc are examples of Application Specific Instruction Set Processors (ASIPs)
 ASIPs incorporate a processor and on-chip peripherals, demanded by the application requirement,
program and data memory
3
 The Typical Embedded System

Microprocessor
 A silicon chip representing a Central Processing Unit (CPU), which is capable
of performing arithmetic as well as logical operations according to a pre-defined
set of Instructions, which is specific to the manufacturer
 In general the CPU contains the Arithmetic and Logic Unit (ALU), Control Unit
and Working registers
 Microprocessor is a dependant unit and it requires the combination of other
hardware like Memory, Timer Unit, and Interrupt Controller etc for proper
functioning.
 ntel claims the credit for developing the first Microprocessor unit Intel 4004, a 4
bit processor which was released in Nov 1971

4
 The Typical Embedded System

Microcontroller
 A highly integrated silicon chip containing a CPU, scratch pad RAM, Special
and General purpose Register Arrays, On Chip ROM/FLASH memory for
program storage, Timer and Interrupt control units and dedicated I/O ports
 Microcontrollers can be considered as a super set of Microprocessors
 Microcontroller can be general purpose (like Intel 8051, designed for generic
applications and domains) or application specific (Like Automotive AVR from
Atmel Corporation. Designed specifically for automotive applications)
 Since a microcontroller contains all the necessary functional blocks for
independent working, they found greater place in the embedded domain in place
of microprocessors
 Microcontrollers are cheap, cost effective and are readily available in the market
 Texas Instruments TMS 1000 is considered as the world’s first microcontroller

5
 The Typical Embedded System
Microprocessor Vs Microcontroller

Microprocessor Microcontroller
A silicon chip representing a Central A microcontroller is a highly integrated chip that
Processing Unit (CPU), which is capable of contains a CPU, scratch pad RAM, Special and
performing arithmetic as well as logical General purpose Register Arrays, On Chip
operations according to a pre-defined set of ROM/FLASH memory for program storage, Timer
Instructions and Interrupt control units and dedicated I/O ports
It is a dependent unit. It requires the It is a self contained unit and it doesn’t require
combination of other chips like Timers, external Interrupt Controller, Timer, UART etc for its
Program and data memory chips, Interrupt functioning
controllers etc for functioning
Most of the time general purpose in design Mostly application oriented or domain specific
and operation
Doesn’t contain a built in I/O port. The I/O Most of the processors contain multiple built-in I/O
Port functionality needs to be implemented ports which can be operated as a single 8 or 16 or 32
with the help of external Programmable bit Port or as individual port pins
Peripheral Interface Chips like 8255
Targeted for high end market where Targeted for embedded market where performance is
performance is important not so critical (At present this demarcation is invalid)
Limited power saving options compared to Includes lot of power saving features
microcontrollers
6
 The Typical Embedded System
Digital Signal Processors (DSPs)
 Powerful special purpose 8/16/32 bit microprocessors designed specifically to meet the
computational demands and power constraints of today's embedded audio, video, and
communications applications
 Digital Signal Processors are 2 to 3 times faster than the general purpose
microprocessors in signal processing applications
 DSPs implement algorithms in hardware which speeds up the execution whereas general
purpose processors implement the algorithm in firmware and the speed of execution
depends primarily on the clock for the processors
 DSP can be viewed as a microchip designed for performing high speed computational
operations for ‘addition’, ‘subtraction’, ‘multiplication’ and ‘division’
 A typical Digital Signal Processor incorporates the following key units
 Program Memory
 Data Memory
 Computational Engine
 I/O Unit
 Audio video signal processing, telecommunication and multimedia applications are
typical examples where DSP is employed 7
 The Typical Embedded System
RISC V/s CISC Processors/Controllers

RISC CISC
Lesser no. of instructions Greater no. of Instructions
Instruction Pipelining and increased Generally no instruction pipelining feature
execution speed
Orthogonal Instruction Set (Allows each Non Orthogonal Instruction Set (All instructions are
instruction to operate on any register and use not allowed to operate on any register and use any
any addressing mode) addressing mode. It is instruction specific)
Operations are performed on registers only, Operations are performed on registers or memory
the only memory operations are load and depending on the instruction
store
Large number of registers are available Limited no. of general purpose registers
Programmer needs to write more code to Instructions are like macros in C language. A
execute a task since the instructions are programmer can achieve the desired functionality
simpler ones with a single instruction which in turn provides the
effect of using more simpler single instructions in
RISC
Single, Fixed length Instructions Variable length Instructions
Less Silicon usage and pin count More silicon usage since more additional decoder
logic is required to implement the complex
instruction decoding.
8
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
 The Typical Embedded System
Harvard V/s Von-Neumann Processor/Controller Architecture

 The terms Harvard and Von-Neumann refers to the processor architecture design.
 Microprocessors/controllers based on the Von-Neumann architecture shares a single
common bus for fetching both instructions and data. Program instructions and data are
stored in a common main memory
 Microprocessors/controllers based on the Harvard architecture will have separate data
bus and instruction bus. This allows the data transfer and program fetching to occur
simultaneously on both buses
 With Harvard architecture, the data memory can be read and written while the program
memory is being accessed. These separated data memory and code memory buses allow
one instruction to execute while the next instruction is fetched (“Pre-fetching”)

I/O CPU Memory

Program
CPU Data Memory
Memory

Single shared Bus

Harvard Architecture
Von-Neumann Architecture
9
 The Typical Embedded System

Harvard V/s Von-Neumann Processor/Controller Architecture

Harvard Architecture Von-Neumann Architecture

Separate buses for Instruction and Single shared bus for Instruction and Data
Data fetching fetching
Easier to Pipeline, so high Low performance Compared to Harvard
performance can be achieved Architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes†
Since data memory and program Since data memory and program memory
memory are stored physically in are stored physically in same chip,
different locations, no chances for chances for accidental corruption of
accidental corruption of program program memory
memory

10
 The Typical Embedded System
Big-endian V/s Little-endian processors

 Endianness specifies the order in which the data is stored in the memory by
processor operations in a multi byte system (Processors whose word size is
greater than one byte). Suppose the word length is two byte then data can be
stored in memory in two different ways
 Higher order of data byte at the higher memory and lower order of data byte at
location just below the higher memory
 Lower order of data byte at the higher memory and higher order of data byte at
location just below the higher memory
 Little-endian means the lower-order byte of the data is stored in memory at the
lowest address, and the higher-order byte at the highest address. (The little end
comes first)
 Big-endian means the higher-order byte of the data is stored in memory at the
lowest address, and the lower-order byte at the highest address. (The big end
comes first.)

11
 The Typical Embedded System
Big-endian V/s Little-endian processors

Base Address + 0 Byte 0 Byte 0 0x20000 (Base Address)

Base Address + 1 Byte 1 Byte 1 0x20001 (Base Address + 1)

Base Address + 2 Byte 2 Byte 2 0x20002 (Base Address + 2)

Base Address + 3 Byte 3 Byte 3 0x20003 (Base Address + 3)

Little-endian Operation

Base Address + 0 Byte 3 Byte 3 0x20000 (Base Address)

Base Address + 1 Byte 2 Byte 2 0x20001 (Base Address + 1)

Base Address + 2 Byte 1 Byte 1 0x20002 (Base Address + 2)

Base Address + 3 Byte 0 Byte 0 0x20003 (Base Address + 3)

Big-endian Operation
12
 The Typical Embedded System
Load Store Operation & Instruction Pipelining

The RISC processor instruction set is orthogonal and it operates on registers. The
memory access related operations are performed by the special instructions load
and store. If the operand is specified as memory location, the content of it is
loaded to a register using the load instruction. The instruction store stores data
from a specified register to a specified memory location

R1 R2 R3
1 3 3 1
load R1, x
load R2, y 2
x 00 add R3, R1, R2 3
y 7F ALU 3
store R3, z 4
z 23

Load Store Operation

13
 The Typical Embedded System
Instruction Pipelining
 The conventional instruction execution by the processor follows the fetch-decode-execute
sequence
 The ‘fetch’ part fetches the instruction from program memory or code memory and the
decode part decodes the instruction to generate the necessary control signals
 The execute stage reads the operands, perform ALU operations and stores the result. In
conventional program execution, the fetch and decode operations are performed in sequence
 During the decode operation the memory address bus is available and if it possible to
effectively utilize it for an instruction fetch, the processing speed can be increased
 In its simplest form instruction pipelining refers to the overlapped execution of instructions

Clock Pulses Clock Pulses Clock Pulses

Machine Cycle 1 Machine Cycle 2 Machine Cycle 3

Fetch (PC)
Execute (PC - 1) Fetch (PC+1)
Execute (PC) Fetch (PC+2)
PC : Program Counter Execute (PC+1)

The Single stage pipelining concept 14

 The Typical Embedded System
Programmable Logic Devices (PLDs)

 Logic devices provide specific functions, including device-to-device

interfacing, data communication, signal processing, data display, timing and
control operations, and almost every other function a system must perform.
 Logic devices can be classified into two broad categories - Fixed and
Programmable. The circuits in a fixed logic device are permanent, they
perform one function or set of functions - once manufactured, they cannot be
changed
 Programmable logic devices (PLDs) offer customers a wide range of logic
capacity, features, speed, and voltage characteristics - and these devices can be
re-configured to perform any number of functions at any time
 Designers can use inexpensive software tools to quickly develop, simulate, and
test their logic designs in PLD based design. The design can be quickly
programmed into a device, and immediately tested in a live circuit
 PLDs are based on re-writable memory technology and the device is
reprogrammed to change the design
15
 The Typical Embedded System
Programmable Logic Devices (PLDs) – CPLDs and FPGA
 Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic
Devices (CPLDs) are the two major types of programmable logic devices
 FPGAs offer the highest amount of logic density, the most features, and the highest
performance.
 These advanced FPGA devices also offer features such as built-in hardwired
processors (such as the IBM Power PC), substantial amounts of memory, clock
management systems, and support for many of the latest, very fast device-to-device
signaling technologies
 FPGAs are used in a wide variety of applications ranging from data processing and
storage, to instrumentation, telecommunications, and digital signal processing
 CPLDs, by contrast, offer much smaller amounts of logic - up to about 10,000 gates
 CPLDs offer very predictable timing characteristics and are therefore ideal for critical
control applications
 CPLDs such as the Xilinx CoolRunner series also require extremely low amounts of
power and are very inexpensive, making them ideal for cost-sensitive, battery-
operated, portable applications such as mobile phones and digital handheld assistants
16
 The Typical Embedded System
Application Specific Integrated Circuit (ASIC)
 A microchip designed to perform a specific or unique application. It is used as
replacement to conventional general purpose logic chips.
 ASIC integrates several functions into a single chip and thereby reduces the system
development cost
 Most of the ASICs are proprietary products. As a single chip, ASIC consumes very
small area in the total system and thereby helps in the design of smaller systems with
high capabilities/functionalities.
 ASICs can be pre-fabricated for a special application or it can be custom fabricated by
using the components from a re-usable ‘building block’ library of components for a
particular customer application
 Fabrication of ASICs requires a non-refundable initial investment (Non Recurring
Engineering (NRE) charges) for the process technology and configuration expenses
 If the Non-Recurring Engineering Charges (NRE) is born by a third party and the
Application Specific Integrated Circuit (ASIC) is made openly available in the market,
the ASIC is referred as Application Specific Standard Product (ASSP)

17
 The Typical Embedded System
Commercial off the Shelf Component (COTS)
 A Commercial off-the-shelf (COTS) product is one which is used ‘as-is’
 COTS products are designed in such a way to provide easy integration and
interoperability with existing system components
 Typical examples for the COTS hardware unit are Remote Controlled Toy Car
control unit including the RF Circuitry part, High performance, high frequency
microwave electronics (2 to 200 GHz), High bandwidth analog-to-digital
converters, Devices and components for operation at very high temperatures,
Electro-optic IR imaging arrays, UV/IR Detectors etc
 A COTS component in turn contains a General Purpose Processor (GPP) or
Application Specific Instruction Set Processor (ASIP) or Application Specific
Integrated Chip (ASIC)/Application Specific Standard Product (ASSP) or
Programmable Logic Device (PLD)
 The major advantage of using COTS is that they are readily available in the
market, cheap and a developer can cut down his/her development time to a
great extend
18
 The Typical Embedded System

Memory
 Memory is an important part of an embedded system. The memory used in embedded
system can be either Program Storage Memory (ROM) or Data memory (RAM)
 Certain Embedded processors/controllers contain built in program memory and data
memory and this memory is known as on-chip memory

19
 The Typical Embedded System
Memory – Program Storage Memory
 Stores the program instructions
 Retains its contents even after the power to it is turned off. It is generally
known as Non volatile storage memory
 Depending on the fabrication, erasing and programming techniques they are
classified into

FLASH Code Memory NVRAM

(ROM)

PROM Masked ROM

EPROM EEPROM
(OTP) (MROM)

20
 The Typical Embedded System

Memory – Program Storage Memory – Masked ROM (MROM)

 One-time programmable memory. Uses hardwired technology for storing
data. The device is factory programmed by masking and metallization
process according to the data provided by the end user
 The primary advantage of MROM is low cost for high volume production.
They are the least expensive type of solid state memory
 Different mechanisms are used for the masking process of the ROM, like
 Creation of an enhancement or depletion mode transistor through channel implant
 By creating the memory cell either using a standard transistor or a high threshold
transistor. In the high threshold mode, the supply voltage required to turn ON the
transistor is above the normal ROM IC operating voltage. This ensures that the
transistor is always off and the memory cell stores always logic 0.
 The limitation with MROM based firmware storage is the inability to
modify the device firmware against firmware upgrades. Since the MROM
is permanent in bit storage, it is not possible to alter the bit information 21
 The Typical Embedded System

Memory – Program Storage Memory – Programmable Read Only

Memory (PROM) / (OTP)
 Unlike MROM it is not pre-programmed by the manufacturer
 PROM/OTP has nichrome or polysilicon wires arranged in a matrix,
these wires can be functionally viewed as fuses
 It is programmed by a PROM programmer which selectively burns the
fuses according to the bit pattern to be stored
 Fuses which are not blown/burned represents a logic “1” where as fuses
which are blown/burned represents a logic “0”.The default state is logic
“1”
 OTP is widely used for commercial production of embedded systems
whose proto-typed versions are proven and the code is finalized
 It is a low cost solution for commercial production. OTPs cannot be
reprogrammed 22
 The Typical Embedded System

Memory – Program Storage Memory – Erasable Programmable

Read Only Memory (EPROM)
 Erasable Programmable Read Only (EPROM) memory gives the flexibility to
re-program the same chip
 EPROM stores the bit information by charging the floating gate of an FET
 Bit information is stored by using an EPROM Programmer, which applies high
voltage to charge the floating gate
 EPROM contains a quartz crystal window for erasing the stored information. If
the window is exposed to Ultra violet rays for a fixed duration, the entire
memory will be erased
 Even though the EPROM chip is flexible in terms of re-programmability, it
needs to be taken out of the circuit board and needs to be put in a UV eraser
device for 20 to 30 minutes

23
 The Typical Embedded System

Memory – Program Storage Memory – Electrically Erasable

Programmable Read Only Memory (EEPROM)
 Erasable Programmable Read Only (EPROM) memory gives the flexibility to
re-program the same chip using electrical signals
 The information contained in the EEPROM memory can be altered by using
electrical signals at the register/Byte level
 They can be erased and reprogrammed within the circuit
 These chips include a chip erase mode and in this mode they can be erased in a
few milliseconds
 It provides greater flexibility for system design
 The only limitation is their capacity is limited when compared with the
standard ROM (A few kilobytes).

24
 The Typical Embedded System

Memory – Program Storage Memory – FLASH

 FLASH memory is a variation of EEPROM technology
 It combines the re-programmability of EEPROM and the high capacity
of standard ROMs
 FLASH memory is organized as sectors (blocks) or pages
 FLASH memory stores information in an array of floating gate
MOSFET transistors
 The erasing of memory can be done at sector level or page level without
affecting the other sectors or pages
 Each sector/page should be erased before re-programming

25
 The Typical Embedded System

Memory – Read-Write Memory/Random Access Memory (RAM)

 RAM is the data memory or working memory of the controller/processor
 RAM is volatile, meaning when the power is turned off, all the contents are
destroyed
 RAM is a direct access memory, meaning we can access the desired memory
location directly without the need for traversing through the entire memory
locations to reach the desired memory position (i.e. Random Access of
memory location)

Read/Write
Memory (RAM)

SRAM DRAM NVRAM

26
 The Typical Embedded System
Memory – RAM – Static RAM (SRAM)
 Static RAM stores data in the form of Voltage. They are made up of flip-flops
 In typical implementation, an SRAM cell (bit) is realized using 6 transistors (or
6 MOSFETs). Four of the transistors are used for building the latch (flip-flop)
part of the memory cell and 2 for controlling the access.
 Static RAM is the fastest form of RAM available. SRAM is fast in operation
due to its resistive networking and switching capabilities

Bit Line B\ Bit Line B

Q1 Q3

Q5 Q6

Q2 Q4
Vcc

Word Line
SRAM cell implementation 27
 The Typical Embedded System
Memory – RAM – Dynamic RAM (DRAM)
 Dynamic RAM stores data in the form of charge. They are made up of MOS
transistor gates
 The advantages of DRAM are its high density and low cost compared to
SRAM
 The disadvantage is that since the information is stored as charge it gets leaked
off with time and to prevent this they need to be refreshed periodically
 Special circuits called DRAM controllers are used for the refreshing operation.
The refresh operation is done periodically in milliseconds interval
Bit Line B

Word Line

+
-

DRAM cell implementation 28

 The Typical Embedded System
Memory – RAM – SRAM Vs DRAM)

SRAM Cell DRAM Cell

Made up of 6 CMOS transistors Made up of a MOSFET and a capacitor
(MOSFET)
Doesn’t Require refreshing Requires refreshing
Low capacity (Less dense) High Capacity (Highly dense)
More expensive Less Expensive
Fast in operation. Typical access Slow in operation due to refresh
time is 10ns requirements. Typical access time is 60ns.
Write operation is faster than read
operation.

29
 The Typical Embedded System

Memory – RAM – Non Volatile RAM (NVRAM)

 Random access memory with battery backup
 It contains Static RAM based memory and a minute battery for
providing supply to the memory in the absence of external power
supply
 The memory and battery are packed together in a single package
 NVRAM is used for the non volatile storage of results of operations or
for setting up of flags etc
 The life span of NVRAM is expected to be around 10 years
 DS1744 from Maxim/Dallas is an example for 32KB NVRAM

30
 The Typical Embedded System
Sensors & Actuators
Sensor:
A transducer device which converts energy from one form to another for any
measurement or control purpose. Sensors acts as input device

Eg. Hall Effect Sensor which measures the distance between the cushion and
magnet in the Smart Running shoes from adidas

Actuator:
A form of transducer device (mechanical or electrical) which converts signals to
corresponding physical action (motion). Actuator acts as an output device
Eg. Micro motor actuator which adjusts the position of the cushioning element in
the Smart Running shoes from adidas

31
 The Typical Embedded System

The I/O Subsystem

 The I/O subsystem of the embedded system facilitates the interaction of
the embedded system with external world
 The interaction happens through the sensors and actuators connected to
the Input and output ports respectively of the embedded system
 The sensors may not be directly interfaced to the Input ports, instead
they may be interfaced through signal conditioning and translating
systems like ADC, Optocouplers etc

32
 The Typical Embedded System

The I/O Subsystem – I/O Devices - Light

Emitting Diode (LED)
 Light Emitting Diode (LED) is an output device for visual
indication in any embedded system
 LED can be used as an indicator for the status of various Vcc
signals or situations. Typical examples are indicating the

R
presence of power conditions like ‘Device ON’, ‘Battery
low’ or ‘Charging of battery’ for a battery operated
handheld embedded devices
 LED is a p-n junction diode and it contains an anode and a
cathode. For proper functioning of the LED, the anode of it GND
should be connected to +ve terminal of the supply voltage
and cathode to the –ve terminal of supply voltage
 The current flowing through the LED must limited to a
value below the maximum current that it can conduct. A
resister is used in series between the power supply and the
resistor to limit the current through the LED 33
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 7-Segment LED

Display
 The 7 – segment LED display is an output device for
displaying alpha numeric characters
 It contains 8 light-emitting diode (LED) segments arranged
in a special form. Out of the 8 LED segments, 7 are used
for displaying alpha numeric characters
 The LED segments are named A to G and the decimal point
LED segment is named as DP
 The LED Segments A to G and DP should be lit
accordingly to display numbers and characters
 The 7 – segment LED displays are available in two
different configurations, namely; Common anode and
Common cathode
 In the Common anode configuration, the anodes of the 8
segments are connected commonly whereas in the Common
cathode configuration, the 8 LED segments share a 34
common cathode line
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 7-Segment LED Display

 Based on the configuration of the 7 – segment LED unit, the LED segment
anode or cathode is connected to the Port of the processor/controller in the
order ‘A’ segment to the Least significant port Pin and DP segment to the
most significant Port Pin.
 The current flow through each of the LED segments should be limited to
the maximum value supported by the LED display unit
 The typical value for the current falls within the range of 20mA
 The current through each segment can be limited by connecting a current
limiting resistor to the anode or cathode of each segment
Anode Common Cathode LED Display
DP G F E D C B A

DP G F E D C B A
Common Anode LED Display Cathode 35
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Optocoupler

 Optocoupler is a solid state device to isolate two parts of a circuit. Optocoupler
combines an LED and a photo-transistor in a single housing (package)
 In electronic circuits, optocoupler is used for suppressing interference in
data communication, circuit isolation, High voltage separation,
simultaneous separation and intensification signal etc
 Optocouplers can be used in either input circuits or in output circuits

Vcc

LED AT89C51 LED

LED I/p interface
I/O interface Port Pin
O/p interface
I/O interface Port Pin
Photo-transistor Photo-transistor
Photo-transistor
Opto-Coupler Microcontroller Opto-Coupler
Optocoupler IC MCT2M IC MCT2M
36
Optocoupler in input and output circuit
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Stepper Motor

 Stepper motor is an electro mechanical device which generates discrete

displacement (motion) in response to dc electrical signals
 It differs from the normal dc motor in its operation. The dc motor produces
continuous rotation on applying dc voltage whereas a stepper motor
produces discrete rotation in response to the dc voltage applied to it
 Stepper motors are widely used in industrial embedded applications,
consumer electronic products and robotics control systems
 The paper feed mechanism of a printer/fax makes use of stepper motors for
its functioning.
 Based on the coil winding arrangements, a two phase stepper motor is
classified into
 Unipolar
 Bipolar
37
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Stepper Motor

Unipolar: A unipolar stepper motor contains two windings per
phase. The direction of rotation (clockwise or anticlockwise) of a A

GND
M
stepper motor is controlled by changing the direction of current C
flow. Current in one direction flows through one coil and in the
B D
opposite direction flows through the other coil. It is easy to shift
the direction of rotation by just switching the terminals to which GND
the coils are connected

Bipolar: A bipolar stepper motor contains single winding per

phase. For reversing the motor rotation the current flow through
the windings is reversed dynamically. It requires complex
circuitry for current flow reversal

38
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 2 Phase Unipolar Stepper Motor –

Stator Winding

A C B D

GND

N
GND
M
M

39
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 2 Phase Unipolar Stepper Motor –

Stepping Sequence

Full Step:
In the full step mode both the phases are energized simultaneously. The coils A,
B, C and D are energized in the order

Step Coil A Coil B Coil C Coil D

1 H H L L
2 L H H L
3 L L H H
4 H L L H

Only one winding of a phase is energized at a time

40
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 2 Phase Unipolar Stepper Motor –

Stepping Sequence

Wave Step:
only one phase is energized at a time and each coils of the phase are energized
alternatively. The coils A, B, C and D are energized in the order

Step Coil A Coil B Coil C Coil D

1 H L L L
2 L H L L
3 L L H L
4 L L L H

Only one winding of a phase is energized at a time

41
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 2 Phase Unipolar Stepper Motor –

Stepping Sequence

Half Step:
Half step uses the combination of wave and full step. It has the highest torque and
stability. The coils A, B, C and D are energized in the order

Step Coil A Coil B Coil C Coil D

1 H L L L
2 H H L L
3 L H L L
4 L H H L
5 L L H L
6 L L H H
7 L L L H
8 H L L H

The rotation of the stepper motor can be reversed by reversing the order in
42
which the coil is energized
 The Typical Embedded System

The I/O Subsystem – I/O Devices – 2 Phase Unipolar Stepper Motor –

Interfacing

 Depending on the current and voltage requirements, special driving circuits are
required to interface the stepper motor with microcontroller/processors.
 Stepper motor driving ICs like ULN2803 or simple transistor based driving
circuit can be used for interfacing stepper motors with processor/controller

Port Pins A
M

Driver IC C
Microcontroller
ULN2803 B D

Vcc
GND Vcc

43
 The Typical Embedded System
The I/O Subsystem – I/O Devices – Relay
 An electro mechanical device which acts as dynamic path selectors for signals and
power
 The ‘Relay’ unit contains a relay coil made up of insulated wire on a metal core and a
metal armature with one or more contacts.
 ‘Relay’ works on electromagnetic principle. When a voltage is applied to the relay coil,
current flows through the coil, which in turn generates a magnetic field. The magnetic
field attracts the armature core and moves the contact point. The movement of the
contact point changes the power/signal flow path

Relay Coil
Relay Coil

Relay Coil

Single Pole Single Single Pole Single Single Pole Double

Throw Normally Throw Normally Throw
Open Closed
44
 The Typical Embedded System
The I/O Subsystem – I/O Devices – Relay Driver Circuit

 The Relay is normally controlled using a relay driver circuit connected to the
port pin of the processor/controller
 A transistor can be used as the relay driver. The transistor can be selected
depending on the relay driving current requirements

Vcc

Freewheeling Diode

Relay Coil Load

Port Pin

Relay Unit

45
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Push button

switch
 Push Button switch is an input device
 Push button switch comes in two configurations, namely
‘Push to Make’ and ‘Push to Break’
 The switch is normally in the open state and it makes a
circuit contact when it is pushed or pressed in the ‘Push
to Make’ configuration
 In the ‘Push to Break’ configuration, the switch is
normally in the closed state and it breaks the circuit
contact when it is pushed or pressed
 The push button stays in the ‘closed’ (For Push to Make
type) or ‘open’ (For Push to Break type) state as long as
it is kept in the pushed state and it breaks/makes the
circuit connection when it is released
 Push button is used for generating a momentary pulse
46
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Keyboard

 Keyboard is an input device for user interfacing

 If the number of keys required is very limited, push button switches can be
used and they can be directly interfaced to the port pins for reading
 Matrix keyboard is an optimum solution for handling large number of key
requirements
 Matrix keyboard greatly reduces the number of interface connections
 Matrix keyboard connects the keys in a row column fashion
 For example, for interfacing 16 keys, in the direct interfacing technique 16
port pins are required, where as in the matrix keyboard only 4 columns and 4
rows are required for interfacing 16 keys
 The key press in matrix keyboard is identified with row-column scanning
technique

47
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Matrix Keyboard

Vcc

4.7K

4.7K
4.7K

4.7K
Row 0
To Microcontroller/processor Port

Row 1

Row 2

Row 3
Column 1
Column 0

Column 3
Column 2

48
To Microcontroller/processor Port
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Programmable Peripheral Interface

(PPI)

 Programmable Peripheral Interface (PPI) devices are used for extending the
I/O capabilities of processors/controllers
 8255A is a popular PPI device for 8 bit processors/controllers
 8255A supports 24 I/O pins ad these I/O pins can be grouped as either three
8-bit parallel ports (Port A, Port B and Port C) or two 8 bit parallel ports (Port
A and Port B) with Port C in any one of the following configuration
 As 8 individual I/O pins
 Two 4bit Ports namely Port CUPPER (CU) and Port CLOWER (CL)
 The Configuration of ports is done through the Control Register of 8255A

D7 D6 D5 D4 D3 D2 D1 D0

Control Register 49
 The Typical Embedded System
The I/O Subsystem – I/O Devices – Programmable Peripheral Interface (PPI)

Bit Description
Port C Lower (CL) I/O mode selector
D0 D0 = 1; Sets CL as Input Port
D0 = 0; Sets CL as Output Port
Port B I/o mode selector
D1 D1 = 1; Sets Port B as Input Port
D1 = 0; Sets Port B as Output Port
Mode Selector for Port C lower and Port B
D2 D2 = 0; Mode 0 – Port B functions as 8bit I/O Port. Port C Lower
functions as 4 bit Port.
D2 = 1; Mode 1 – Handshake Mode. Port B uses 3 bits of
Port C as handshake signals
Port C Upper (CU) I/o mode selector
D3 D3 = 1; Sets CU as Input Port
D3 = 0; Sets CU as Output Port
Port A I/o mode selector
D4 D4 = 1; Sets Port A as Input Port
D4 = 0; Sets Port A as Output Port
D5, D6 Mode Selector for Port C upper and Port A
D6 D5 = 00; Mode 0 – Simple I/O mode
D6 D5 = 01; Mode 1 – Handshake Mode. Port A uses 3 bits of
Port C as handshake signals
D6 D5 = 1X; Mode 2. X can be 0 or 1 – Port A functions as Bi-
directional Port
D7 Control/Data mode selector for Port C
D7 = 1; I/O mode.
D7 = 0; Bit Set/Reset (BSR) mode. Functions as the control/status lines for Port A and B. The bits of Port C 50
can be set or reset just as if they were output ports.
 The Typical Embedded System

The I/O Subsystem – I/O Devices – Programmable Peripheral Interface

(PPI) Interfacing

Processor/
82C55A
Controller Data Bus D0….D7 D0….D7
Data Bus Port
Pins 34 to 27
Latch
A0 Pin 9
(Eg: 74LS373) PA0….PA7
A1 Pin 8
Port A
ALE
A2….A7 PB0….PB7
Port B
Higher Order
Address Bus Address Bus Address
(A8….A15) CS\ Pin 6
decoder PC0….PC7
Port C
RD\ RD\ Pin 5
WR\ WR\ Pin 36
RESET OUT RESET Pin 35

51
 The Typical Embedded System

Communication Interface
 Communication interface is essential for communicating with various subsystems of the
embedded system and with the external world
 For an embedded product, the communication interface can be viewed in two different
perspectives; namely; Device/board level communication interface (Onboard Communication
Interface) and Product level communication interface (External Communication Interface)
 Embedded product is a combination of different types of components (chips/devices)
arranged on a Printed Circuit Board (PCB). The communication channel which interconnects
the various components within an embedded product is referred as Device/board level
communication interface (Onboard Communication Interface)
 Serial interfaces like I2C, SPI, UART, 1-Wire etc and Parallel bus interface are examples of
‘Onboard Communication Interface’
 The ‘Product level communication interface’ (External Communication Interface) is
responsible for data transfer between the embedded system and other devices or modules
 The external communication interface can be either wired media or wireless media and it can
be a serial or parallel interface. Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio
Frequency waves (RF), GPRS etc are examples for wireless communication interface
 RS-232C/RS-422/RS 485, USB, Ethernet (TCP-IP), IEEE 1394 port, Parallel port, CF-II Slot,
SDIO, PCMCIA etc are examples for wired interfaces 52
 The Typical Embedded System
On-board Communication Interface - I2C
 Inter Integrated Circuit Bus (I2C - Pronounced ‘I square C’) is a synchronous bi-directional half
duplex (one-directional communication at a given point of time) two wire serial interface bus
 The concept of I2C bus was developed by ‘Philips Semiconductors’ in the early 1980’s. The
original intention of I2C was to provide an easy way of connection between a
microprocessor/microcontroller system and the peripheral chips in Television sets
 The I2C bus is comprised of two bus lines, namely; Serial Clock – SCL and Serial Data – SDA.
SCL line is responsible for generating synchronization clock pulses and SDA is responsible for
transmitting the serial data across devices.
 I2C bus is a shared bus system to which many number of I2C devices can be connected. Devices
connected to the I2C bus can act as either ‘Master’ device or ‘Slave’ device
 The ‘Master’ device is responsible for controlling the communication by initiating/terminating
data transfer, sending data and generating necessary synchronization clock pulses
 ‘Slave’ devices wait for the commands from the master and respond upon receiving the
commands
 ‘Master’ and ‘Slave’ devices can act as either transmitter or receiver
 Regardless whether a master is acting as transmitter or receiver, the synchronization clock signal
is generated by the ‘Master’ device only
 I2C supports multi masters on the same bus
53
The Typical Embedded System
On-board Communication Interface - I2C

SCL SDA Vcc

2.2K

SDA
2.2K
Port Pins SCL
Slave 1
SCL I2C Device
Master SDA (Eg: Serial
(Microprocessor/ EEPROM)
Controller)

SCL Slave 2
SDA I2C Device

I2C Bus

54
 The Typical Embedded System
On-board Communication Interface - I2C
The sequence of operation for communicating with an I2C slave device is:
1. Master device pulls the clock line (SCL) of the bus to ‘HIGH’
2. Master device pulls the data line (SDA) ‘LOW’, when the SCL line is at logic ‘HIGH’ (This is the ‘Start’
condition for data transfer)
3. Master sends the address (7 bit or 10 bit wide) of the ‘Slave’ device to which it wants to communicate, over the
SDA line. Clock pulses are generated at the SCL line for synchronizing the bit reception by the slave device.
The MSB of the data is always transmitted first. The data in the bus is valid during the ‘HIGH’ period of the
clock signal
4. Master sends the Read or Write bit (Bit value = 1 Read Operation; Bit value = 0 Write Operation) according to
the requirement
5. Master waits for the acknowledgement bit from the slave device whose address is sent on the bus along with the
Read/Write operation command. Slave devices connected to the bus compares the address received with the
address assigned to them
6. The Slave device with the address requested by the master device responds by sending an acknowledge bit (Bit
value =1) over the SDA line
7. Upon receiving the acknowledge bit, master sends the 8bit data to the slave device over SDA line, if the
requested operation is ‘Write to device’. If the requested operation is ‘Read from device’, the slave device sends
data to the master over the SDA line
8. Master waits for the acknowledgement bit from the device upon byte transfer complete for a write operation and
sends an acknowledge bit to the slave device for a read operation
9. Master terminates the transfer by pulling the SDA line ‘HIGH’ when the clock line SCL is at logic ‘HIGH’
(Indicating the ‘STOP’ condition) 55
 The Typical Embedded System

On-board Communication Interface – Serial Peripheral Interface (SPI) Bus

The Serial Peripheral Interface Bus (SPI) is a synchronous bi-directional full duplex four
wire serial interface bus. The concept of SPI is introduced by Motorola. SPI is a single
master multi-slave system. It is possible to have a system where more than one SPI device
can be master, provided the condition only one master device is active at any given point
of time, is satisfied. SPI requires four signal lines for communication. They are:

Master Out Slave In (MOSI): Signal line carrying the data from master to slave device.
It is also known as Slave Input/Slave Data In (SI/SDI)
Master In Slave Out (MISO): Signal line carrying the data from slave to master device.
It is also known as Slave Output (SO/SDO)
Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low
signal

56
 The Typical Embedded System

On-board Communication Interface – Serial Peripheral Interface (SPI) Bus

MOSI SCL MISO

MISO
SCL
MOSI MOSI Slave 1
SCL SPI Device
Master
MISO (Eg: Serial
(Microprocessor/
SS\ EEPROM)
Controller)
SS1\
SS2\
MOSI
Slave 2
SCL
SPI Device
MISO
(Eg: LCD)
SS\

SPI Bus 57
 The Typical Embedded System

On-board Communication Interface – Serial Peripheral Interface (SPI) Bus

 The master device is responsible for generating the clock signal. Master device selects
the required slave device by asserting the corresponding slave device’s slave select
signal ‘LOW’. The data out line (MISO) of all the slave devices when not selected
floats at high impedance state
 The serial data transmission through SPI Bus is fully configurable. SPI devices
contain certain set of registers for holding these configurations. The Serial Peripheral
Control Register holds the various configuration parameters like master/slave
selection for the device, baudrate selection for communication, clock signal control
etc. The status register holds the status of various conditions for transmission and
reception.
 SPI works on the principle of ‘Shift Register’. The master and slave devices contain a
special shift register for the data to transmit or receive. The size of the shift register is
device dependent. Normally it is a multiple of 8. During transmission from the master
to slave, the data in the master’s shift register is shifted out to the MOSI pin and it
enters the shift register of the slave device through the MOSI pin of the slave device.
At the same time the shifted out data bit from the slave device’s shift register enters
the shift register of the master device through MISO pin 58
 The Typical Embedded System
On-board Communication Interface –
Universal Asynchronous Receiver Transmitter (UART)
 Universal Asynchronous Receiver Transmitter (UART) based data transmission is an
asynchronous form of serial data transmission
 The serial communication settings (Baudrate, No. of bits per byte, parity, No. of start
bits and stop bit and flow control) for both transmitter and receiver should be set as
identical
 The start and stop of communication is indicated through inserting special bits in the
data stream
 While sending a byte of data, a start bit is added first and a stop bit is added at the end
of the bit stream. The least significant bit of the data byte follows the start bit.
 The ‘Start’ bit informs the receiver that a data byte is about to arrive. The receiver
device starts polling its ‘receive line’ as per the baudrate settings
 If parity is enabled for communication, the UART of the transmitting device adds a
parity bit
 The UART of the receiving device calculates the parity of the bits received and
compares it with the received parity bit for error checking
 The UART of the receiving device discards the ‘Start’, ‘Stop’ and ‘Parity’ bit from the59
received bit stream and converts the received serial bit data to a word
 The Typical Embedded System

On-board Communication Interface – Universal Asynchronous Receiver

Transmitter (UART)

TXD TXD
UART UART
RXD RXD

TXD: Transmitter Line

RXD: Receiver Line

60
 The Typical Embedded System

On-board Communication Interface – 1-Wire Interface

 An asynchronous half-duplex communication protocol developed by Maxim Dallas
Semiconductor (http://www.maxim-ic.com)
 It is also known as Dallas 1-Wire® protocol. It makes use of only a single signal line
(wire) called DQ for communication and follows the master-slave communication
model
 The 1-Wire interface supports a single master and one or more slave devices on the
bus
 The 1-Wire is capable of carrying power to the slave device apart from carrying the
signals. Slave devices incorporate internal capacitor to generate power to operate the
device from the 1-Wire
 Every 1-Wire device contains a globally unique 64 bit identification number stored
within it. This unique identification number can be used for addressing individual
devices present in the bus in case there are multiple slave devices connected to the 1-
Wire bus
 The identifier has three parts: an 8 bit family code, a 48 bit serial number and an 8 bit
CRC computed from the first 56 bits
61
 The Typical Embedded System

On-board Communication Interface – 1-Wire Interface

Vcc

4.7K

DQ Slave 1
Port Pin
1-Wire Device
(Eg: DS2760 Battery
GND
monitor IC )
Master
(Microprocessor/
Controller) DQ Slave 2
1-Wire Device
(Eg: DS2431 1024
GND GND
Bit EEPROM )
62
 The Typical Embedded System

On-board Communication Interface – 1-Wire Interface

The sequence of operation for communicating with a 1-Wire slave
device is:
1. Master device sends a ‘Reset’ pulse on the 1-Wire bus.
2. Slave device(s) present on the bus respond with a ‘Presence’
pulse.
3. Master device sends a ROM Command (Net Address Command
followed by the 64 bit address of the device). This addresses the
slave device(s) to which it wants to initiate a communication
4. Master device sends a read/write function command to
read/write the internal memory or register of the slave device.
5. Master initiates a Read data /Write data from the device or to the
device 63
 The Typical Embedded System
On-board Communication Interface – 1-Wire Interface
 All communication over the 1-Wire bus is master initiated
 The communication over the 1-Wire bus is divided into timeslots of 60 microseconds
 The ‘Reset’ pulse occupies 8 time slots. For starting a communication, the master
asserts the reset pulse by pulling the 1-Wire bus ‘LOW’ for at least 8 time slots (480µs)
 If a ‘Slave’ device is present on the bus and is ready for communication it should
respond to the master with a ‘Presence’ pulse, within 60µs of the release of the ‘Reset’
pulse by the master
 The slave device(s) responds with a ‘Presence’ pulse by pulling the 1-Wire bus ‘LOW’
for a minimum of 1 time slot (60µs)
 For writing a bit value of 1 on the 1-Wire bus, the bus master pulls the bus for 1 to 15µs
and then releases the bus for the rest of the time slot
 A bit value of ‘0’ is written on the bus by master pulling the bus for a minimum of 1
time slot (60µs) and a maximum of 2 time slots (120µs)
 To Read a bit from the slave device, the master pulls the bus ‘LOW’ for 1 to 15µs
 If the slave wants to send a bit value ‘1’ in response to the read request from the slave, it
simply releases the bus for the rest of the time slot
 If the slave wants to send a bit value ‘0’, it pulls the bus ‘LOW’ for the rest of the time64
slot.
 The Typical Embedded System

On-board Communication Interface – Parallel Interface

 Parallel interface is normally used for communicating with peripheral devices which are
memory mapped to the host of the system
 The host processor/controller of the embedded system contains a parallel bus and the
device which supports parallel bus can directly connect to this bus system
 The communication through the parallel bus is controlled by the control signal interface
between the device and the host
 The ‘Control Signals’ for communication includes ‘Read/Write’ signal and device select
signal
 The device normally contains a device select line and the device becomes active only
when this line is asserted by the host processor
 The direction of data transfer (Host to Device or Device to Host) can be controlled
through the control signal lines for ‘Read’ and ‘Write’
 Only the host processor has control over the ‘Read’ and ‘Write’ control signals

65
 The Typical Embedded System

On-board Communication Interface – Parallel Interface

D0 to Data Bus
Dx-1 Peripheral Device
RD\ RD\ (Eg: ADC)
WR\ WR\
Host Control Signals CS\
(Microprocessor/
Controller) Chip Select

A0 to Address Bus Address De-coder

Ay-1 Circuit

x: Data bus width

y: Address Bus width
66
 The Typical Embedded System
External Communication Interface – RS-232 C & RS-485
 RS-232 C (Recommended Standard number 232, revision C from the Electronic
Industry Association) is a legacy, full duplex, wired, asynchronous serial
communication interface
 RS-232 extends the UART communication signals for external data communication.
 UART uses the standard TTL/CMOS logic (Logic ‘High’ corresponds to bit value 1
and Logic ‘LOW’ corresponds to bit value 0) for bit transmission whereas RS232 use
the EIA standard for bit transmission. As per EIA standard, a logic ‘0’ is represented
with voltage between +3 and +25V and a logic ‘1’ is represented with voltage between
-3 and -25V. In EIA standard, logic ‘0’ is known as ‘Space’ and logic ‘1’ as ‘Mark’.
 The RS232 interface define various handshaking and control signals for
communication apart from the ‘Transmit’ and ‘Receive’ signal lines for data
communication. RS-232 supports two different types of connectors, namely; DB-9: 9-
Pin connector and DB-25: 25-Pin connector.
1 13
1 5

6 9 14 25
DB-25
DB-9 67
 The Typical Embedded System
External Communication Interface – RS-232 C & RS-485

Pin No:
Pin Name (For DB-9 Description
Connector)
TXD 3 Transmit Pin. Used for Transmitting Serial Data
RXD 2 Receive Pin. Used for Receiving serial Data
RTS 7 Request to send.
CTS 8 Clear To Send
DSR 6 Data Set ready
GND 5 Signal Ground
DCD 1 Data Carrier Detect
DTR 4 Data Terminal Ready
RI 9 Ring Indicator

68
 The Typical Embedded System
External Communication Interface – RS-232 C & RS-485
 RS-232 is a point-to-point communication interface and the devices involved in RS-232
communication are called ‘Data Terminal Equipment (DTE)’ and ‘Data Communication
Equipment (DCE)’
 If no data flow control is required, only TXD and RXD signal lines and ground line (GND) are
required for data transmission and reception. The RXD pin of DCE should be connected to the
TXD pin of DTE and vice versa for proper data transmission.
 If hardware data flow control is required for serial transmission, various control signal lines of
the RS-232 connection are used appropriately. The control signals are implemented mainly for
modem communication and some of them may be irrelevant for other type of devices
 The Request To Send (RTS) and Clear To Send (CTS) signals co-ordinate the communication
between DTE and DCE. Whenever the DTE has a data to send, it activates the RTS line and if the
DCE is ready to accept the data, it activates the CTS line
 The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data. The
Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication
link. DTR should be in the activated state before the activation of DSR
 The Data Carrier Detect (DCD) is used by the DCE to indicate the DTE that a good signal is
being received
 Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line
69
 The Typical Embedded System
External Communication Interface – RS-232 C & RS-485
 As per the EIA standard RS-232 C supports baudrates up to 20Kbps (Upper limit 19.2Kbps) The
commonly used baudrates by devices are 300bps, 1200bps, 2400bps, 9600bps, 11.52Kbps and
19.2Kbps
 The maximum operating distance supported in RS-232 communication is 50 feet at the highest
supported baudrate.
 Embedded devices contain a UART for serial communication and they generate signal levels
conforming to TTL/CMOS logic. A level translator IC like MAX 232 from Maxim Dallas
semiconductor is used for converting the signal lines from the UART to RS-232 signal lines for
communication. On the receiving side the received data is converted back to digital logic level by
a converter IC. Converter chips contain converters for both transmitter and receiver
 RS-232 uses single ended data transfer and supports only point-to-point communication and not
suitable for multi-drop communication
 RS-422 is another serial interface standard from EIA for differential data communication. It
supports data rates up to 100Kbps and distance up to 400 ft
 RS-422 supports multi-drop communication with one transmitter device and receiver devices up
to 10
 RS-485 is the enhanced version of RS-422 and it supports multi-drop communication with up to
32 transmitting devices (drivers) and 32 receiving devices on the bus. The communication
between devices in the bus makes use of the ‘addressing’ mechanism to identify slave devices
70
 The Typical Embedded System
External Communication Interface – Universal Serial Bus (USB)

 Universal Serial Bus (USB) is a wired high speed serial

bus for data communication
 The USB communication system follows a star topology Peripheral
Device 2
with a USB host at the center and one or more USB
peripheral devices/USB hosts connected to it
Peripheral
 A USB host can support connections up to 127, including Peripheral
Device 1
USB Host
Device 3
(Hub)
slave peripheral devices and other USB hosts
 USB transmits data in packet format. Each data packet has
a standard format. The USB communication is a host USB Host
(Hub)
initiated one
 The USB Host contains a host controller which is Peripheral Peripheral
Device 4 Device 5
responsible for controlling the data communication,
including establishing connectivity with USB slave devices,
packetizing and formatting the data packet. There are
different standards for implementing the USB Host Control
interface; namely Open Host Control Interface (OHCI) and
Universal Host Control Interface (UHCI) 71
 The Typical Embedded System

External Communication Interface – Universal Serial Bus (USB)

 The Physical connection between a USB peripheral device and master device is
established with a USB cable
 The USB cable supports communication distance of up to 5 meters
 The USB standard uses two different types of connectors namely ‘Type A’ and ‘Type
B’ at the ends of the USB cable for connecting the USB peripheral device and host
device
 ‘Type A’ connector is used for upstream connection (connection with host) and ‘Type
B’ connector is used for downstream connection (connection with slave device)

Pin No: Pin Name Description

1 VBUS Carries power (5V)
2 D- Differential data carrier line
3 D+ Differential data carrier line
4 GND Ground signal line
72
 The Typical Embedded System
External Communication Interface – Universal Serial Bus (USB)
 Each USB device contains a Product ID (PID) and a Vendor ID (VID)
 The PID and VID are embedded into the USB chip by the USB device manufacturer
 The VID for a device is supplied by the USB standards forum
 PID and VID are essential for loading the drivers corresponding to a USB device for
communication
 USB supports four different types of data transfers, namely; Control, Bulk, Isochronous and
Interrupt
 Control transfer is used by USB system software to query, configure and issue commands to the
USB device
 Bulk transfer is used for sending a block of data to a device. Bulk transfer supports error
checking and correction. Transferring data to a printer is an example for bulk transfer.
 Isochronous data transfer is used for real time data communication. In Isochronous transfer,
data is transmitted as streams in real time. Isochronous transfer doesn’t support error checking
and re-transmission of data in case of any transmission loss
 Interrupt transfer is used for transferring small amount of data. Interrupt transfer mechanism
makes use of polling technique to see whether the USB device has any data to send
 The frequency of polling is determined by the USB device and it varies from 1 to 255
milliseconds. Devices like Mouse and Keyboard, which transmits fewer amounts of data, uses 73
Interrupt transfer.
 The Typical Embedded System
External Communication Interface – IEEE 1394 (Firewire)
 A wired, isochronous high speed serial communication bus. It is also known as High
Performance Serial Bus (HPSB)
 The research on 1394 was started by Apple Inc in 1985 and the standard for this was
coined by IEEE.
 The Apple Inc’s (www.apple.com) implementation of 1394 protocol is popularly
known as Firewire.
 i.LINK is the 1394 implementation from Sony Corporation (www.sony.net) and
Lynx is the implementation from Texas Instruments (www.ti.com)
 1394 supports peer-to-peer connection and point-to-multipoint communication allowing 63
devices to be connected on the bus in a tree topology
 The 1394 standard supports a data rate of 400 to 3200Mbits/Second
 IEEE 1394 uses differential data transfer and the interface cable supports 3 types of connectors,
namely; 4-pin connector, 6-pin connector (alpha connector) and 9 pin connector (beta
connector)
 The 6 and 9 pin connectors carry power also to support external devices. It can supply
unregulated power in the range of 24 to 30V (The Apple implementation is for battery operated
devices and it can supply a voltage in the range 9 to 12V)
74
 The Typical Embedded System
External Communication Interface – IEEE 1394 (Firewire)

Pin Pin No: Pin No: Pin No:

Name (4 Pin (6 Pin (9 Pin Description
Connecto Connect Connector)
r) or)
Power 1 8 Unregulated DC supply. 24 to 30V
Signal 2 6 Ground connection
Ground
TPB- 1 3 1 Differential Signal line for Signal Line B
TPB+ 2 4 2 Differential Signal line for Signal Line B
TPA- 3 5 3 Differential Signal line for Signal Line A
TPA+ 4 6 4 Differential Signal line for Signal Line A
Shield for the differential signal line A. Normally
TPA(S) 5 grounded
Shield for the differential signal line B. Normally
TPB(S) 9 grounded
NC 7 No connection

75
 The Typical Embedded System

External Communication Interface – IEEE 1394 (Firewire)

 The IEEE 1394 connector contains two differential data transfer lines
namely A and B
 The differential lines of A are connected to B (TPA+ to TPB+ and TPA- to
TPB-) and vice versa
 Unlike USB interface (Except USB OTG), IEEE 1394 doesn’t require a host
for communicating between devices. Example, a scanner can be directly
connected to a printer for printing
 The data rate supported by 1394 is far higher than the one supported by
USB2.0 interface
 1394 is a popular communication interface for connecting embedded devices
like ‘Digital Camera’, ‘Camcorder’, ‘Scanners’ with desktop Computers for
data transfer and storage

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 The Typical Embedded System
External Communication Interface – Infrared (IrDA)
 A serial, half duplex, line of sight based wireless technology for data communication
between devices
 Infrared communication technique makes use of Infrared waves of the electromagnetic
spectrum for transmitting the data
 IrDA supports point-point and point-to-multipoint communication, provided all devices
involved in the communication are within the line of sight
 The typical communication range for IrDA lies in the range 10cm to 1 m
 IR supports data rates ranging from 9600bits/second to 16Mbps. Depending on the
speed of data transmission IR is classified into Serial IR (SIR), Medium IR (MIR), Fast
IR (FIR), Very Fast IR (VFIR) and Ultra Fast IR (UFIR)
 SIR supports transmission rates ranging from 9600bps to 115.2kbps. MIR supports data
rates of 0.576Mbps and 1.152Mbps. FIR supports data rates up to 4Mbps. VFIR is
designed to support high data rates up to 16Mbps. The UFIR specs are under
development and it is targeting a data rate up to 100Mbps
 IrDA communication involves a transmitter unit for transmitting the data over IR and a
receiver for receiving the data. Infrared Light Emitting Diode (LED) is used as the IR
source for transmitter and at the receiving end a photodiode is used as the receiver
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 The Typical Embedded System
External Communication Interface – Bluetooth
 Low cost, low power, short range wireless technology for data and voice communication
 Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency Hopping
Spread Spectrum (FHSS) technique for communication.
 Bluetooth supports a theoretical maximum data rate of up to 1Mbps and a range of approximately
30 feet for data communication
 Bluetooth communication has two essential parts; a physical link part and a protocol part. The
physical link is responsible for the physical transmission of data between devices supporting
Bluetooth communication and protocol part is responsible for defining the rules of communication
 The physical link works on the Wireless principle making use of RF waves for communication
 Bluetooth enabled devices essentially contain a Bluetooth wireless radio for the transmission and
reception of data
 The rules governing the Bluetooth communication is implemented in the ‘Bluetooth protocol
stack’. The Bluetooth communication IC holds the stack
 Each Bluetooth device will have a 48 bit unique identification number. Bluetooth communication
follows packet based data transfer
 Bluetooth supports point-to-point (device to device) and point-to-multipoint (device to multiple
device broadcasting) wireless communication. The point-to-point communication follows the
master-slave relationship. A Bluetooth device can function as either master or slave
 A network formed with one Bluetooth device as master and more than one device as slaves is
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known as Piconet
 The Typical Embedded System
External Communication Interface – Wi-Fi
 The popular wireless communication technique for networked communication of devices
 Wi-Fi follows the IEEE 802.11 standard
 Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication
 Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless Access
point to manage the communications
 The Wi-Fi router is responsible for restricting the access to a network, assigning IP address to
devices on the network, routing data packets to the intended devices on the network
 Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the form
of radio signals through an antenna
 Wi-Fi operates at 2.4GHZ or 5GHZ of radio spectrum and they co-exist with other ISM band
devices like Bluetooth
 A Wi-Fi network is identified with a Service Set Identifier (SSID). A Wi-Fi device can connect
to a network by selecting the SSID of the network and by providing the credentials if the
network is security enabled
 Wi-Fi networks implements different security mechanisms for authentication and data transfer
 Wireless Equivalency Protocol (WEP), Wireless Protected Access (WPA) etc are some of the
security mechanisms supported by Wi-Fi networks in data communication
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 The Typical Embedded System
External Communication Interface – Wi-Fi

Wi-Fi Router

Device 1
Device 2 Device 3

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 The Typical Embedded System
External Communication Interface – ZigBee
 Low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard
 ZigBee is targeted for low power, low data rate and secure applications for Wireless
Personal Area Networking (WPAN)
 The ZigBee specifications support a robust mesh network containing multiple nodes.
This networking strategy makes the network reliable by permitting messages to travel
through a number of different paths to get from one node to another.
 ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at
2.400 to 2.484 GHz, 902 to 928 MHz and 868.0 to 868.6 MHz
 ZigBee Supports an operating distance of up to 100 meters and a data rate of 20 to
250Kbps
 ZigBee is primarily targeting application areas like Home & Industrial Automation,
Energy Management, Home control/security, Medical/Patient tracking, Logistics &
Asset tracking and sensor networks & active RFID
 Automatic Meter Reading (AMR), smoke and detectors, wireless telemetry, HVAC
control, heating control, Lighting controls, Environmental controls, etc are examples
for applications which can make use of the ZigBee technology 81
 The Typical Embedded System

External Communication Interface – ZigBee

In the ZigBee terminology, each ZigBee device falls
under any one of the following ZigBee device category
ZED ZED
ZigBee Coordinator (ZC)/Network Coordinator:
The ZigBee coordinator acts as the root of the ZigBee
network. The ZC is responsible for initiating the ZED
ZigBee network and it has the capability to store
information about the network
ZR ZC ZR
ZigBee Router (ZR)/Full function Device (FFD):
Responsible for passing information from device to
another device or to another ZR ZED ZED

ZigBee End Device (ZED)/Reduced Function

Device (RFD): End device containing ZigBee
functionality for data communication. It can talk only
with a ZR or ZC and doesn’t have the capability to act
as a mediator for transferring data from one device to 82
another.
 The Typical Embedded System

External Communication Interface – General Packet Radio Service

(GPRS)
 A communication technique for transferring data over a mobile communication network
like GSM
 Data is sent as packets. The transmitting device splits the data into several related packets.
At the receiving end the data is re-constructed by combining the received data packets
 GPRS supports a theoretical maximum transfer rate of 171.2kbps
 In GPRS communication, the radio channel is concurrently shared between several users
instead of dedicating a radio channel to a cell phone user. The GPRS communication
divides the channel into 8 timeslots and transmits data over the available channel
 GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25 protocols
for communication.
 GPRS is mainly used by mobile enabled embedded devices for data communication. The
device should support the necessary GPRS hardware like GPRS modem and GPRS radio
 GPRS is an old technology and it is being replaced by new generation data communication
techniques like EDGE, High Speed Downlink Packet Access (HSDPA) etc which offers
higher bandwidths for communication
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