Basics of Verilog HDL

HDL – Hardware Description Language

Two Competing HDL’s

VHDL – VHSIC HDL
VHSIC – Very High Speed Integrated Circuit
Verilog HDL
Verilog HDL is most widely used HDL – IEEE industry standard HDL used to
describe a digital system.
Provides comprehensive support for low level design.
Verilog was designed primarily for digital H/W designers developing
FPGA’s/ASICs

Terminologies
Simulation => check if design works fine
Synthesis => Conversion of RTL to gate level (implement the design on real
hardware)

History of Verilog HDL

 Originated in 1983 @ Gateway Design Automation.

 In 1989 Cadence design systems, purchased Gateway and made Verilog language to
be available to the public.
 Verilog language then became IEEE standard 1364, referred to as Verilog-95.
 Extension to Verilog-95 were introduced in 2001 referred to as Verilog - 2001 and
minor revisions introduced in 2005.
 In 2009, the SystemVerilog and Verilog language standards were merged.
 The current version is IEEE standard 1800-2017

Verilog Module
 In Verilog, the basic unit of hardware is called module.
 Modules cannot contain the definitions of other module
 A Module can, however, be instantiated with in another module.
  Allows the creation of a hierarchy in a Verilog description.
 Semicolon : Statement terminator
 // - Single line comment
 /* */ - Multi-line comment
 Case sensitive

Module Structure

Example:: simple XOR Gate

module simplexor (f,a,b);

input a, b;
output f;

assign f = a^b;

endmodule

Identifier & Keywords

Identifier
 User-provided names for Verilog objects in the descriptions
 Legal characters are “a-z”, “A-Z”, “0-9”, “_”, and “$”
 First character has to be a letter or an “_”
 Example: Count, _R2D2, FIVE$
 Keywords
 Predefined identifiers to define the language constructs
 All keywords are defined in lower case
 Cannot be used as identifiers
 Example: initial, assign, module, always….

Ports
Three types of ports
 Input (keyword - input)
 Output (keyword – output)
 Inout (keyword – inout)
Port declarations example
input a;
input a, b;
input [3:0] c, d;
output [4:0] y;
inout x;

Data Types
Two basic data types
 Nets and
 Registers
Nets represent physical wires in the design.(wire, tri)
 Default initial value for a wire is “Z”
Registers represent storage in the Verilog model. (reg, integer, real, time)
 Register data type may or may not result in physical registers.
 Registers are manipulated within procedural blocks (always and initial) only.
 Default initial value for a reg is “X”
 Data Types – Examples
reg a; // a scalar register
reg [3:0] v; // a 4-bit vector register from msb to lsb
reg [7:0] m, n; // two 8-bit register m and n
tri [15:0] busa; // a 16-bit tri-state bus
wire [31:0] w1, w2; // Two 32-bit wires w1 and w2 with msb being the 31st bit

Register Types
reg - any size, unsigned
integer (not synthesizable)
Ex: integer a,b; // declaration(a = 10, b = -10)
real (not synthesizable)
Ex: real a,b; // declaration(a = 3.14, b = 3e6)
time (not synthesizable) - 64-bit unsigned, behaves like a 64-bit reg

Numbers & Negative Numbers

A number may be sized or unsized
Ex: h12_unsized = ‘h12; h12_sized = 6’h12;
Ex: PA = -12, PB = -’d12, PC= -32’d12;
Sized numbers are written as width ‘radix value
The radix indicates the type of number
Decimal (d or D)
Hex (h or H)
Octal (o or O)
Binary (b or B)
Unsized numbers are written as ‘radix value

Levels of Abstraction – Four Levels

 Behavioural - Module can be implemented in terms of design algorithm without

concern for the hardware implementation (similar to C programing)
 Dataflow - Module is designed by specifying the data flow. Designer is aware on
how the data flows between different nodes and how it is processed.
  Gate/Structural - Module is designed in terms of logic gates/predefined verilog
modules and interconnections between the gates/modules.
 Switch - Low level of abstraction. Module is designed in terms of
switches/transistors and hence the designer needs to know about the switch level
implementation details.

Gate Level Modeling

 A Gate level description is based on the structure of the logic circuit.

 A gate level description uses the verilog primitive gates to produce the desired output

Verilog Primitive Gates

Gate Level Modeling – Half Adder

//Half Adder : Structural Verilog Description

module ha_gate_level (x,y,s,c);
input x,y;
output s,c;
xor x1(s, x, y);
and a1(c, x, y);
endmodule
Gate Level Modeling – Full Adder

//Full Adder : Structural Description

module fa_gate_level(x,y,z,s,c);
input x,y,z;
output s,c;
wire w1,w2,w3;
xor xor1(w1,x,y);
xor xor2(s,w1,z);
and A1(w2, x,y);
and A2(w3,w1,z);
or O1(c, w3,w2);
endmodule

Gate Level Modeling – Full Adder using Half adder

//Full Adder using 2 Half Adder : Structural Description
module fa_gate_level(x,y,z,s,c);
input x,y,z;
output s,c;

wire s_ha1,c_ha1,c_ha2;

//port mapping by order

ha_gate_level HA1(x,y,s_ha1,c_ha1);

//port mapping by name

//ha_gate_level HA1( .a(a), .b(b), .s(s_ha1), .c(c_ha1) );

ha_gate_level HA2(z, s_ha1, s, c_ha2);

or O1(c, c_ha1, c_ha2);

endmodule
Dataflow Modeling

 A dataflow description is based on function rather than structure.

 A dataflow uses a number of operators that act on operands to produce the desired
function
 Boolean equations are used in place of logic schematics.
 Continuous assignment(assign) is the most basic statement used in dataflow
modelling

Dataflow Modeling – Half Adder

//Half Adder : Dataflow description

module ha_df (x,y,s,c);
input x,y;
output s,c;
assign s = x^y;
assign c = x & y;
//assign {c,s} = x + y; //Alternate Method
endmodule

Operators
Continuous Assignment Examples

Ripple Carry Adder

Behavioral Modeling

 Specifies how a particular design should respond to a given set of input.

 Behavioral modeling uses structured procedures to specify the behaviour of the
circuit.
 May be specified by
• Boolean expressions
• Algorithms written in standard HLL like C
Ex : {Carry,Sum} = a+b+c;

Structured Procedures
 Two basic structured procedure statements or procedural blocks are
• always (synthesizable)
• initial (non-synthesizable)
 All behavioral statements can appear only inside these blocks
 Each always or initial block has a separate activity flow (concurrency)
 There can be multiple always and initial blocks in a module
 All procedural blocks start from simulation time 0
 Cannot be nested
 Execute the statements in a looping fashion
 Multiple always blocks, execute in parallel and all start at time 0
Syntax:
always @(sensitivity list)
begin
// behavioral statements
end
Behavioral Modeling – Half Adder
//Half Adder : Behavioral description
module ha_beh (x,y,s,c);
input x,y;
output s,c;
reg s, c;
always @(a or b)
begin
s = x ^ y;
c = x & y;
//{c,s} = x + y;
end
endmodule

Reference Books
 Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, 2009, 2 nd
edition, Prentice Hall of India Pvt. Ltd.
 Stuart Sutherland, “Verilog® HDL Quick Reference Guide” based on the Verilog-2001
standard
 Modelsim

 ModelSim is a simulation and verification tool by Siemens (previously developed by

Mentor Graphics) for the designs developed using the hardware description languages
such as VHDL, Verilog, System Verilog
 ModelSim can be used independently, or in conjunction with Intel Quartus Prime.
 Simulation is performed using the graphical user interface (GUI), or automatically
using scripts
 Tool: https://tinyurl.com/modelsimtool

Simulation Flow
 Though you don’t have to use projects in ModelSim, they may ease interaction with
the tool and are useful for organizing files and specifying simulation settings

Method 1 Aternative method

 We shall follow Method 1

Method I
Create a New Project
1. Open the Modelsim tool.
2. If any project is already opened, the close the previously opened project File > Close
project

3. Create one directory for you to work with the project and change the directory to your
working directory File > Change directory
  Browse for your working directory and click OK

4. Select File > New > Project (Main window) from the menu bar.
5. This opens the Create Project dialog where you can enter a Project Name, Project
Location (i.e., directory), and Default Library Name

 Type the Project Name

 Click the Browse button for the Project Location field to select a directory
where the project file will be stored
 Leave the Default Library Name set to work.
 Click OK.

6. Once you click OK to accept the new project settings, a blank Project window and the
“Add items to the Project” dialog will appear

 Click Create New File if file has to be created or click Add Existing File
if the file is available.
 7. Once you click Create New File, Create Project File dialog will appear.

 Type the File name to be created

 Select Add file as type as Verilog from the drop down menu (By default it will be
VHDL).
 Click OK.

8. The new file will be added to the project.

9. Close the Add items to the Project window.
10. Select the file added to the project window and double click/right click and select
edit to type the code in the editor window.

Compilation and Simulation

1. New files status will be shown as ?
2. Select the file, right click – compile – Compile selected.

3. If compilation is successful, status changes to green colour tick mark.

4. Select the Library window, expand work library and select the module to be
simulated, right click and select Simulate. Once you click simulate, sim window,
Objects window, Wave window may be opened and the design will be loaded and the
status will be displayed in the Transcript window.
5. To view the output in the wave window, select the design module in the sim window,
right click and select Add Wave [or] select all the signals from the Objects window,
right click and select Add Wave. Multiple signals can be selected by selecting the
signals using the cursor and holding the CTRL key.
6. Signals will be added to the wave window.

7. There are two methods to force values to the input signals. In method 1, we use the
Force option. Select the input signals alone, right click and select Force

8. In the appearing pop up window, provide the Value of the input as 0 or 1 based on
what value to apply as input. Then, select the Kind to be as Drive and click OK.
9. Repeat the step 8 for all the inputs and then run the simulation using the Run icon or
by pressing F9 key Run icon

10. Repeat Steps 7 to 9 and force all the possible input combinations and check the output
11. In method 2, we use the Clock option. Select the input signals alone, right click and
select Clock.

12. In the pop-up box, define the input signal as clock by specifying the Period and select
the first edge as falling and then click OK.

13. Repeat step 12, for all the input signals with different time periods. Usually, specify
half the time period of the previously defined input signal. For example for the first
input signal if the Period defined is 200, then for the second signal give the Period as
100 and for the third signal give the Period as 50.

14. After defining all the input signals as clock, run the simulation by pressing F9/ by
clicking the run icon.
15. At any point of time, if you want to simulate your design from the start, select the
restart icon and then click OK in the Restart pop-up window
Restart icon

16. Enabling or disabling the view of any window (Library, Project, Sim, Object,
Transcript, Wave) can be done using the View Tab and enable/disable the window.
Opening an existing Project
1. To open/reopen an existing project, select File->Open. In the pop-up window, select
the file type as Project Files(*.mpf)

2. Select the project that has to be opened and double click/select open.
To add new/existing files to the project
1. To add new files to the project, open/reopen an existing project by following the steps
given under Opening an existing Project, and then right click in the Project window
select Add to Project->New File to add a new file to the project or select Add to
Project->Existing File to add an existing file to the project. To add an existing file, in
the pop-up window, browse for the existing *.v file and select Copy to project
directory and click OK.