Unit- 4

Sequential Logic Circuits

Dr. V S M Srinivasavarma,
Assistant Professor,
Computer Science and Engineering,
Shiv Nadar University Chennai.
Introduction
• A sequential circuit consists of a feedback path, and employs some
memory elements.
Combinational
outputs Memory outputs

Combinational Memory
logic elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Introduction
▪ There are two types of sequential circuits:
❖synchronous: outputs change only at specific time
❖asynchronous: outputs change at any time
▪ Multivibrator: a class of sequential circuits. They can be:
❖bistable (2 stable states)
❖monostable or one-shot (1 stable state)
❖astable (no stable state)
▪ Bistable logic devices: latches and flip-flops.
▪ Latches and flip-flops differ in the method used for changing their
state.
Memory Elements
• Memory element: a device which can remember value indefinitely, or
change value on command from its inputs.

Memory Q
command element stored value

• Characteristic table: Command Q(t) Q(t+1)

(at time t) Q(t): current state
Set X 1 Q(t+1) or Q+: next state
Reset X 0
Memorise / 0 0
No Change 1 1

Memory Elements
Memory Elements
▪ Memory element with clock. Flip-flops are memory elements that
change state on clock signals.
Memory Q
command element stored value

clock
▪ Clock is usually a square wave.
Positive pulses

Positive edges Negative edges

Memory Elements
▪ Two types of triggering/activation:
❖pulse-triggered
❖edge-triggered
▪ Pulse-triggered
❖latches
❖ON = 1, OFF = 0
▪ Edge-triggered
❖flip-flops
❖positive edge-triggered (ON = from 0 to 1; OFF = other time)
❖negative edge-triggered (ON = from 1 to 0; OFF = other time)
S-R Latch
▪ Complementary outputs: Q and Q'.
▪ When Q is HIGH, the latch is in SET state.
▪ When Q is LOW, the latch is in RESET state.
▪ For active-HIGH input S-R latch (also known as NOR gate latch),
R=HIGH (and S=LOW)  RESET state
S=HIGH (and R=LOW)  SET state
both inputs LOW  no change
both inputs HIGH  Q and Q' both LOW (invalid)!
S-R Latch
• Characteristics table for active-high input S-R latch:
S R Q Q'
0 0 NC NC No change. Latch
remained in present state. S Q
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET. R Q'
1 1 0 0 Invalid condition.

S R Q Q'
R
Q 1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
Q' 0 0 0 1 (after S=0, R=1)
S 1 1 0 0 invalid!
Gated S-R Latch

E S R Q 𝑸′
0 0 0 Latch Latch
0 0 1 Latch Latch
0 1 0 Latch Latch
0 1 1 Latch Latch Gated SR Latch
1 0 0 Latch Latch
S
1 0 1 0 1
Q
1 1 0 1 0
1 1 1 0 0 EN

Characteristic Table Q'

R
Latch Circuits: Not Suitable

▪ Latch circuits are not suitable in synchronous logic circuits.

▪ When the enable signal is active, the excitation inputs are gated
directly to the output Q. Thus, any change in the excitation input
immediately causes a change in the latch output.
▪ The problem is solved by using a special timing control signal called a
clock to restrict the times at which the states of the memory
elements may change.
▪ This leads us to the edge-triggered memory elements called flip-flops.
Edge-Triggered Flip-flops

▪ Flip-flops: synchronous bistable devices

▪ Output changes state at a specified point on a triggering input called
the clock.
▪ Change state either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

S-R Flipflop
▪ S-R flip-flop: on the triggering edge of the clock pulse,
❖S=HIGH (and R=LOW)  SET state
❖R=HIGH (and S=LOW)  RESET state
❖both inputs LOW  no change
❖both inputs HIGH  invalid
▪ Characteristic table of positive edge-triggered S-R flip-flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH
S-R Flip-flop

▪ It comprises 3 parts:
❖a basic NAND latch
❖a pulse-steering circuit
❖a pulse transition detector (or edge detector) circuit
▪ The pulse transition detector detects a rising (or falling) edge and
produces a very short-duration spike.
S-R Flipflop
The pulse transition detector:
S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)
Gated D Latch
▪ Make R input equal to S' → gated D latch.
▪ D latch eliminates the undesirable condition of invalid state in the S-R
latch.

D
Q D Q
EN EN

Q' Q'
Gated D Latch
▪ When EN is HIGH,
❖ D=HIGH → latch is SET
❖ D=LOW → latch is RESET
▪ Hence when EN is HIGH, Q ‘follows’ the D (data) input.
▪ Characteristic table:
EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

When EN=1, Q(t+1) = D

D Flip-flop
▪ D flip-flop: single input D (data)
❖D=HIGH  SET state
❖D=LOW  RESET state
▪ Q follows D at the clock edge.
▪ Convert S-R flip-flop into a D flip-flop: add an inverter.
D S D CLK Q(t+1) Comments
Q
C 1  1 Set
CLK
R 0  0 Reset
Q'

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

J-K Flip-flop
▪ J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
▪ No invalid state.
▪ Include a toggle state.
❖ J=HIGH (and K=LOW)  SET state
❖ K=HIGH (and J=LOW)  RESET state
❖ both inputs LOW  no change
❖ both inputs HIGH  toggle
J-K Flip-flop
▪ J-K flip-flop.
J
Q
Pulse
CLK transition
detector
Q'
K

▪ Characteristic table.
Q J K Q(t+1)
J K CLK Q(t+1) Comments 0 0 0 0
0 0  Q(t) No change 0 0 1 0
0 1  0 Reset 0 1 0 1
1 0  1 Set 0 1 1 1
1 1  Q(t)' Toggle 1 0 0 1
1 0 1 0
1 1 0 1
Q(t+1) = J.Q' + K'.Q 1 1 1 0
T Flip-flop
▪ T flip-flop: single-input version of the J-K flip flop, formed by tying
both inputs together.

T
Q T J
Pulse Q
transition C
CLK CLK
▪
detector K
Q' Q'

▪ Characteristic table.
T CLK Q(t+1) Comments Q T Q(t+1)
0  Q(t) No change 0 0 0
1  Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q' + T'.Q
Edge-Triggered Flip-flops
• S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the
clock input.

S Q D Q J Q
C C C
R K
Q' Q' Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R K
Q' Q' Q'

Negative edge-triggered flip-flops

Counters
• Counters are circuits that cycle through a specified number of states.
• Two types of counters:
• synchronous (parallel) counters
• asynchronous (ripple) counters
• Ripple counters allow some flip-flop outputs to be used as a source of clock for
other flip-flops.
• Synchronous counters apply the same clock to all flip-flops.
Asynchronous (Ripple) Counters
• Asynchronous counters: the flip-flops do not change states at exactly the same
time as they do not have a common clock pulse.
• Also known as ripple counters, as the input clock pulse “ripples” through the
counter – cumulative delay is a drawback.
• n flip-flops → a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles
through x states.)
• Output of the last flip-flop (MSB) divides the input clock frequency by the MOD
number of the counter, hence a counter is also a frequency divider.
Asynchronous (Ripple) Counters
• Example: 2-bit ripple binary counter.
• Output of one flip-flop is connected to the clock input of the next more-significant
flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00 → 01 → 10 → 11 → 00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0
Asynchronous (Ripple) Counters
• Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
Asynchronous (Ripple) Counters
• Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 n
Asyn. Counters with MOD no. < 2
▪ States may be skipped resulting in a truncated sequence.
▪ Technique: force counter to recycle before going through all of the states in the
binary sequence.
▪ Example: Given the following circuit, determine the counting sequence (and hence
the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C
 n
Asyn. Counters with MOD no. < 2
• Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12 MOD-6 counter
Clock produced by
A clearing (a MOD-8
B binary counter)
C
when count of six
(110) occurs.
NAND 1
Output 0
 n
Asyn. Counters with MOD no. < 2
• Example (cont’d): Counting sequence of circuit (in CBA order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A
B
C
NAND 1
Output 0

111 000
Temporary 001
state
Counter is a MOD-6 counter.
110 010

101 011
100
 n
Asyn. Counters with MOD no. < 2
• Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter?
MOD-12 counter?
• Question: The following is a MOD-? counter?

F E D C B A
Q J Q J Q J Q J Q J Q J

Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR

C
D
E All J = K = 1.
F
 n
Asyn. Counters with MOD no. < 2
• Decade counters (or BCD counters) are counters with 10 states (modulus-10) in
their sequence. They are commonly used in daily life (e.g.: utility meters,
odometers, etc.).
• Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C

K K K K
CLR CLR CLR CLR
 n
Asyn. Counters with MOD no. < 2
• Asynchronous decade/BCD counter (cont’d).

HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D

C
B
A
NAND
output
Asynchronous Down Counters
• So far we are dealing with up counters. Down counters, on the other hand, count
downward from a maximum value to zero, and repeat.
• Example: A 3-bit binary (MOD-23) down counter.

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K
Asynchronous Down Counters
• Example: A 3-bit binary (MOD-8) down counter.
000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
Q' K Q' K Q'
K
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0
Cascading Asynchronous Counters
• Larger asynchronous (ripple) counter can be constructed by cascading smaller
ripple counters.
• Connect last-stage output of one counter to the clock input of next counter so as
to achieve higher-modulus operation.
• Example: A modulus-32 ripple counter constructed from a modulus-4 counter and
a modulus-8 counter.

Q0 Q1 Q2 Q3 Q4

J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K

Modulus-4 counter Modulus-8 counter

Cascading Asynchronous Counters
• Example: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-bit
counters.

A0 A1 A2 A3 A4 A5

Count 3-bit 3-bit

binary counter binary counter
pulse

A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :
Cascading Asynchronous Counters
• If counter is a not a binary counter, requires additional output.
• Example: A modulus-100 counter using two decade counters.

freq/10
1 CTENDecade CTENDecade freq/100
counter TC counter TC
CLK C Q3 Q2 Q1 Q0 C Q3 Q2 Q1 Q0
freq

TC = 1 when counter recycles to 0000

Synchronous (Parallel) Counters
• Synchronous (parallel) counters: the flip-flops are clocked at the same time by a
common clock pulse.
• We can design these counters using the sequential logic design process (covered
in Lecture #12).
• Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with
identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
11 10 0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
Synchronous (Parallel) Counters
• Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with
identical J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1 TA0 = 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
Q' K Q'
K

CLK
Synchronous (Parallel) Counters Design
• Before studying the design of counters, it is important to understand the following
about FFs.

They are:
1. Truth Table
2. Characteristic Table
3. Excitation Table
JK Flipflop
Characteristic Table Excitation Table
• Truth Table
Clk J K 𝑸𝒏+𝟏 𝑸𝒏 J K 𝑸𝒏+𝟏 𝑸𝒏 𝑸𝒏+𝟏 J K

↓ X X 𝑸𝒏 0 0 0 0 0 0 0 X

↑ 0 0 𝑸𝒏 0 0 1 0 0 1 1 X
↑ 0 1 0 0 1 0 1 1 0 X 1
↑ 1 0 1 0 1 1 1 1 1 X 0
↑ 1 1 𝑸𝒏 1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
 SR Flipflop
Characteristic Table Excitation Table
• Truth Table
Clk S R 𝑸𝒏+𝟏 𝑸𝒏 S R 𝑸𝒏+𝟏 𝑸𝒏 𝑸𝒏+𝟏 S R

↓ X X 𝑸𝒏 0 0 0 0 0 0 0 X

↑ 0 0 𝑸𝒏 0 0 1 0 0 1 1 0

↑ 0 1 0 0 1 0 1 1 0 0 1
↑ 1 0 1 0 1 1 1 1 1 X 0
↑ 1 1 Invalid 1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Invali
d
 T Flipflop
Characteristic Table Excitation Table
• Truth Table
Clk T 𝑸𝒏+𝟏 𝑸𝒏 T 𝑸𝒏+𝟏 𝑸𝒏 𝑸𝒏+𝟏 T
0 0 0 0 0 0
↓ X 𝑸𝒏
0 1 1
↑ 0 𝑸𝒏 0 1 1
1 0 1
↑ 1 𝑸𝒏 1 0 1
1 1 0
1 1 0
Design of Synchronous (Parallel) Counters:
Steps:
1. Decide the no. of FFs and the type of the flipflop as well
2. Excitation table of FF
3. State diagram and circuit excitation table
4. Obtain simplified equations using K-map
5. Draw the logic diagram
Practice Examples:
• Design a 2-bit synchronous Up-Counter using JK Flipflop
• Design a 3-bit synchronous down-counter using T-Flipflop
• Design a 2-bit synchronous Down-Counter using JK Flipflop
• Design a 3-bit synchronous Up-counter using T-Flipflop
Registers
Registers
• Group of storage elements read/written as a unit.
• Store related values (e.g. a binary word)
• Collection of flip-flops with common control
• Share clock, reset, set lines
• Example:
• Storage registers
• Shift registers
Storage Registers
• Basic storage registers uses flip flops
• Example: 4 bit storage register

OUT1 OUT2 OUT3 OUT4

"0"
R S R S R S R S
D Q D Q D Q D Q
CLK

IN1 IN2 IN3 IN4

Shift Registers
• Hold successively sampled input values
• Delays values in time
• Example: 4-bit shift register
• Stores 4 input values in sequence

OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q
CLK
Shift-register applications
• Parallel-to-serial conversion for signal transmission
serial transmission
parallel outputs
CLK CLK

parallel inputs

• Pattern recognition (circuit recognizes 1001)

OUT

IN D Q D Q D Q D Q
CLK
Shift-register Types
4-types:
1. Serial-In-Serial-Out
2. Serial-In-Parallel-Out
3. Parallel-In-Serial-Out
4. Parallel-In-Parallel-Out

Universal Shift Register

Serial-In-Serial-Out
Serial-In-Parallel-Out
Parallel-In-Serial-Out
Parallel-In-Parallel-Out
Bidirectional Shift Register
 Universal Shift Register
• It has both right shift and left shift capabilities along with parallel load capabilities

Basic connections –

1. The first input (zeroth pin of multiplexer) is connected to the output pin of the corresponding flip-
flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-previous flip flop
which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the very-next flip-flop
which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of the input data which
facilitates parallel loading.
Universal Shift Register

Operation Truth Table

S1 S0 Register
Operation
0 0 No Changes
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load
Universal Shift Register- Applications
Advantages:
• This register can perform 3 operations such as shift-left, shift-right, and parallel loading.
• It can perform serial to parallel, parallel to serial, parallel to parallel and serial to serial
operations.
• It can perform input-output operations in both the modes serial and parallel.
• This register acts as an interface between one device to another device to transfer the data.
Applications:
• Used in Micro-Controllers for I/O expansion
• Used as a memory element in computers.
• Used in time delay applications
• Used as frequency counters, binary counters, and Digital clocks
Thank You