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Notes - Unit 6

Digital Logic and Microprocessor Design (Oakland University)

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

Notes - Unit 6
SYNCHRONOUS SEQUENTIAL CIRCUITS
ASYNCHRONOUS CIRCUITS: LATCHES

SR LATCH:
R S R Qt+1 Qt+1
Q
0 0 Qt Qt
0 1 0 1

S Q 1 0 1 0
restricted
1 1 0 0

S
SR Latch
R
S Q
Q
R Q
Q

SR LATCH WITH ENABLE:

R
E S R Qt+1 Qt+1
R'
0 x x Qt Qt
Q
1 0 0 Qt Qt
E
1 0 1 0 1

S' Q 1 1 0 1 0
S
1 1 1 0 0

D LATCH WITH ENABLE:

 This is essentially an SR Latch, where 𝑅 = 𝑛𝑜𝑡(𝐷), 𝑆 = 𝐷

D
R' E D Qt+1
Q
0 x Qt
E
1 0 0

S' Q
1 1 1

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

SYNCHRONOUS CIRCUITS:

FLIP FLOPS
 Flip flops are made out of:
o A Latch with an enable input.
o An Edge detector circuit.

 The figure depicts an SR Latch, where the enable is connected to the output of an Edge Detector Circuit. The input to the
Edge Detector is a signal called 'clock'. A clock signal is a square wave with a fixed frequency.

clock

T Period Frequency = 1/T

SR Flip Flop
R
R'
Q

clock Edge E
Detector

S' Q
S or

 The edge detector circuit generates short-duration pulses during rising (or falling) edges. These pulses act as enable of the
Latch.
 The behavior of the flip flops can be described as that of a Latch that is only enabled during rising (or falling edges).

 Flip flops classification:

o Positive-edge triggered flip flop: The edge detector circuit generates pulses during rising edges.
o Negative-edge triggered flip flop: The edge detector circuit generates pulses during falling edges.

S Q S Q
clock clock

Q Q
R R
Positive Negative
edge-triggered edge-triggered

SR Flip Flop

clock S R Qt+1 Qt+1

0 0 Qt Qt S Q
0 1 0 1 clock

1 0 1 0 Q
R
1 1 0 0

𝑄𝑡+1 = 𝑆𝑅̅ + 𝑄𝑡 𝑆̅𝑅̅ = 𝑅̅(𝑆 + 𝑄𝑡 𝑆̅) = 𝑅̅(𝑆 + 𝑆̅)(𝑆 + 𝑄𝑡 ) = 𝑅̅𝑆 + 𝑅̅ 𝑄𝑡 (on the edge)

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D Flip Flop
clock D Qt+1
D Q
0 0
clock
1 1 Q
D Flip Flop
D

clock Edge E
Detector

𝑄𝑡+1 = 𝐷 (on the edge)

T Flip Flop

clock T Qt+1
T D Q T Q
0 Qt
clock clock
Q Q 1 Qt

𝑄𝑡+1 = 𝑇𝑄𝑡 (on the edge)

JK Flip Flop

J clock J K Qt+1
J Q
K 0 0 Qt
D Q
clock
0 1 0
clock K Q
Q 1 0 1

1 1 Qt
̅̅̅𝑡 + 𝐾
𝑄𝑡+1 = 𝐽𝑄 ̅ 𝑄𝑡 (on the edge)

Synchronous/Asynchronous Inputs
 So far, the flip flops can only change their outputs on the rising (or falling edge). The outputs are usually changed due to a
change in the inputs. These inputs are known as synchronous inputs, as the inputs' state is only checked on the rising (or
falling) edges.
 However, in many instances, it is useful to have inputs that force the outputs to a value prn
immediately, disregarding the rising (or falling edges). These inputs are known as
asynchronous inputs.
D Q
 In the example, we see a D Flip Flop with two asynchronous inputs:
o prn: Preset (active low). When prn='0', the output q becomes 1.
o clrn: Clear (active low). When clrn='0', the output q becomes 0.
clock
Q
 If prn and clrn are both 0, usually clrn is given priority. clrn
 A Flip flop could have more than one asynchronous inputs, or none.

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

PRACTICE EXERCISES
1. Complete the timing diagram of the circuit shown below:

clk

clrn
0
D D Q Q
1 D
E
E
clk Q

clrn Q

2. Complete the VHDL description of the circuit shown below:

library ieee;
use ieee.std_logic_1164.all; a
0
entity circ is D Q Q
b
port ( a, b, s, clk, clrn: in std_logic; 1
q: out std_logic);
end circ;
s

architecture a of circ is clk Q

begin clrn
-- ???

end a;

3. Complete the timing diagram of the circuit shown below. If the frequency of the signal clock is 25 MHz, what is the frequency
(in MHz) of the signal Q?

clrn
clock
'1' T Q
clrn
clock
Q Q

4. Complete the timing diagram of the circuit whose VHDL description is shown below:

library ieee; elsif (clk’event and clk = ‘1’) then

use ieee.std_logic_1164.all; if x = ‘1’ then
qt <= not (qt);
entity circ is end if;
port ( clrn, x, clk: in std_logic; end if;
q: out std_logic); end process;
end circ; q <= qt
end a;
architecture a of circ is
signal qt: std_logic; clk
begin
process (clrn, clk, x)
begin
clrn
if clrn = ‘0’ then
qt <= ‘0’;
x

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

5. Complete the timing diagram of the circuit shown below:

Full Adder
a s
x s clk
b
y FA
cin cout clrn
D Q

clk a
Q
b
clrn
s

6. Complete the VHDL description of the synchronous sequential circuit whose truth table is shown below:

library ieee;
use ieee.std_logic_1164.all;
clrn clk A B Qt+1

entity circ is 1 0 0 1
port ( A, B, C: in std_logic;
clrn, clk: in std_logic; 1 0 1 C
q: out std_logic);
end circ;
1 1 0 Qt
architecture a of circ is
begin 1 1 1 Qt
-- ???

end a; 0 X X X 0

7. Complete the timing diagram of the circuit shown below:

clk
Q
J Q
clrn
clk

K Q
x
clrn y
y
x Q

8. Complete the timing diagram of the circuit shown below:

clrn
clock
D Q
D Q clrn
clk
Q
D
Latch
Q
QL
D Q
QL
E Q

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

REGISTERS:
resetn

N-BIT REGISTER: This is a collection of 'n' D-type flip Dn-1 D Q Qn-1

flops, where each flip flop independently stores one bit. The
flip flops are connected in parallel. They also share the same
resetn and clock signals.
resetn
Dn-2 D Q Qn-2
D n D Q n Q

...

...

...
clk

D0 D Q Q0

clk

N-BIT SHIFT REGISTER: This is a collection of 'n' D-type flip flops, connected serially. The flip flops share the same resetn
and clock signals. The serial input is called 'din', and the serial output is called 'dout'. The flip flop outputs (also called the
parallel output) are called 𝑄 = 𝑄𝑛−1 𝑄𝑛−2 ⋯ 𝑄0 . Depending on how we label the bits, we can have:
 Right shift register: The input bit moves from the MSB to the LSB, and
 Left shift register: The input bit moves from the LSB to the MSB.
RIGHT SHIFT REGISTER: Qn-1 Qn-2 Qn-3 Q0
resetn
resetn
din din dout dout
din D Q D Q D Q ... D Q dout
clk
Qn-1
Qn-2
Qn-3

...
Q0

clk

LEFT SHIFT REGISTER: Q0 Q1 Q2 Qn-1

resetn
resetn
din din dout dout
din D Q D Q D Q ... D Q dout
clk
Qn-1

...
Q0
Q1
Q2

clk

Timing Diagram example:

Q3 Q2 Q1 Q0
resetn

x D Q D Q D Q D Q

clk

clk

resetn

Q3

Q2

Q1

Q0

Q 0000 0000 0000 1000 0100 0010 1001 0100 1010 1101 1110 0111 0011 0001

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

Parallel access shift register:

 This is a shift register in which we can write data on the flip flops in parallel. 𝑠_𝑙 = 0  shifting operation, 𝑠_𝑙 = 1  parallel
load. The figure below shows a 4-bit parallel access shift register.
Q3 Q2 Q1 Q0

resetn

D Q D Q D Q D Q

clk

0 1 0 1 0 1 0 1

din D3 s_l D2 D1 D0

clk

resetn

s_l

din

D 0000 1101 1001 1100

Q 0000 0000 1000 1100 0110 0011 1001 1101 1110 0111 1011 1100 0110 0011 1100 1110 0111 0011

Adding enable to flip flops:

 In many instances, it is very useful to have a signal that controls whether the value of the flip flop is kept. The following
circuit represent a flip flop with synchronous enable. When E = ‘0’, the flip flop keeps its value. When E = ‘1’, the flip flop
grabs the value at the input D.
 We can thus create n-bit registers and n-bit shift registers with enable. Here, all the flip flops share the same enable input.

clk

resetn
0
D D Q Q
1
D
E
clk
E
resetn
Q

REGISTER: RIGHT SHIFT REGISTER: LEFT SHIFT REGISTER:

resetn resetn resetn

n D Q n Q din din dout dout din din dout dout

D
E E E E
E
clk clk
clk
Qn-1
Qn-1
Qn-2
Qn-3

...
Q0
Q1
Q2

...
Q0

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

Parallel access shift register with enable

 All the flip flops share the same enable input.
Q3 Q2 Q1 Q0

resetn

D Q D Q D Q D Q
E E E E E

clk

0 1 0 1 0 1 0 1

din D3 s_l D2 D1 D0

clk

resetn

s_l

din

D 0000 1101 1001 1100

Q 0000 0000 1000 1100 0110 1011 1101 1101 0110 1101 0110 1100 0110 0011 1001 1100 0110 0011

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

SYNCHRONOUS COUNTERS
 Counters are useful for: counting the number of occurrences of a certain event, generate time intervals for task control,
track elapsed time between two events, etc. Counters are made of flip flops and combinatorial logic. They are usually
designed using Finite State Machines (FSM).
 Synchronous counters change their output on the clock edge (rising or falling). Each flip flop shares the same clock input
signal. If the initial count is zero, each flip flop shares the resetn input signal.

COUNTER CLASSIFICATION:
a) Binary counter: An 𝑛 − 𝑏𝑖𝑡 counter counts from 0 to 2𝑛 − 1. The figure depicts a 2-bit counter.

resetn

D Q Q0 clk

resetn

D Q Q1
Q 00 00 01 10 11 00 01 10 11
clk

b) Modulus counter: A counter 𝑚𝑜𝑑𝑢𝑙𝑜 − 𝑁 counts from 0 to N-1. Special case: BCD (or decade) counter: Counts from 0
to 9.
resetn
clk
Q 4
resetn

clk Q 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001
BCD counter
c) Up/down counter: Counts both up and down, under command of a control input.
d) Parallel load counter: The count can be given an arbitrary value.
e) Counter with enable: If enable = 0, the count stops. If enable = 1, the counter counts. This is usually done by
connecting the enable inputs of the flip flops to a single enable.
f) Ring counter: Also called one-hot counter (only one bit is 1 at a time). It can be constructed using a shift register. The
output of the last stage is fed back to the input to the first stage, which creates a ring-like structure. The asynchronous
signal startn sets the initial count to 100…000 (first bit set to 1). Example (4-bits): 1000, 0100, 0010, 0001, 1000, …
The figure below depicts an 𝑛 − 𝑏𝑖𝑡 ring counter.
Q0 Q1 Q2 Qn-1

startn

D Q D Q D Q ... D Q
prn

clk

g) Johnson counter: Also called twisted ring counter. It can be constructed using a shift register, where the 𝑄̅ output of
the last flip flop is fed back to the first stage. The result is a counter where only a single bit has a different value for two
consecutive counts. All the flip flops share the asynchronous signal ‘resetn’, which sets the initial count to 000…000.
Example (4 bits): 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, … The figure below depicts
an 𝑛 − 𝑏𝑖𝑡 Johnson counter.
Q0 Q1 Q2 Qn-1

resetn

D Q D Q D Q ... D Q

clk

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

RANDOM ACCESS MEMORY EMULATOR

 The following sequential circuit represents a memory with 8 addresses, where each address holds a 4-bit data. The memory
positions are implemented by 4-bit registers. The reset and clock signals are shared by all the registers. Data is written or
read onto/from one of the registers (selected by the signal ‘address’).

 Writing onto memory (wr_rd = 1): The 4-bit input data (D_in) is written into one of the 8 registers. The address signal
selects which register is to be written. Here, the 7-segment display must show 0. For example: if address = “101”, then D_in
is written into register 5.

 Reading from memory (wr_rd = 0): The MUX output appears on the 7-segment display (hexadecimal value). The address
signal selects the register from which data is read.
For example: If address = “010”, then data in register 2 must appear on the 7-segment display. If data in register 2 is ‘1010’,
then the symbol ‘A’ appears on the 7-segment display.

wr_rd
reset

E
4
D_in[3..0] D 0 Q

E
clock D 1 Q

E
D 2 Q

E
E
address[2..0] 3
Decoder D 3 Q Decoder:
4

MUX
HEX to 7
E segments
wr_rd
E D 4 Q

E
7
D 5 Q
3
E
D 6 Q

E
D 7 Q

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

FINITE STATE MACHINES:

 Sequential circuits are also called Finite State Machines (FSMs), because the functional behavior of these circuits can be
represented using a finite number of states (flip flop outputs).
 The signal ‘resetn’ sets the flip flops to an initial state.
 Classification:
- Moore machine: Outputs depend solely on the current state of the flip flops.
- Mealy machine: Outputs depend on the current state of the flip flops as well as on the input to the circuit.
Only for Mealy Machine

Inputs Combinatorial Flip n Q(states) Combinatorial Outputs

Circuit Flops Circuit

clock
resetn

 Any general sequential circuit can be represented by the figure above (Finite State Machine model).
 A sequential circuit with certain behavior and/or specification can be formally designed using the Finite State Machine
method: drawing a State Diagram and coming up the Excitation Table.
 Designing sequential circuits using the Finite State Machine method is a powerful in Digital Logic Design.

Example: 2-bit gray-code counter with enable and ‘z’ output: 00, 01, 11, 10, 00, … The output ‘z’ is 1 when the present count
is ‘10’. The count is the same as the states encoded in binary.
 First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only
step we need.

E/z
resetn = 0 E PRESENT NEXT NEXT
0/0
STATE STATE COUNT z
1/0
0/0 S1 S2 0 S1 S1 00 0
0 S2 S2 01 0
1/1 1/0 0/0 0 S3 S3 11 0
0 S4 S4 10 1
1/0
0/1 S4 S3 1 S1 S2 01 0
1 S2 S3 11 0
1 S3 S4 10 0
1 S4 S1 00 1
 Second step: State Assignment. We assign unique flip flop states to our state labels (S1, S2, S3, S4). Notice that this is
arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output ‘count’ is
just the flip flops’ outputs.

 S1: Q = 00
 S2: Q = 01
 S3: Q = 11
 S4: Q = 10

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

 Third step: Excitation table. Here, we replace the state labels by the flip flop states:
PRESENT STATE NEXTSTATE

E Q1(t) Q0(t) Q1(t+1) Q0(t+1) z

0 0 0 0 0 0
0 0 1 0 1 0
0 1 1 1 1 0
0 1 0 1 0 1
1 0 0 0 1 0
1 0 1 1 1 0
1 1 1 1 0 0
1 1 0 0 0 1
 Fourth step: Excitation equations and minimization. 𝑄1 (𝑡 + 1) and 𝑄0 (𝑡 + 1) are the next state of the flip flops, i.e. these
signals are to be connected to the inputs of the flip flops.
Q1(t+1) EQ Q0(t+1) EQ z EQ
1 1 1
00 01 11 10 00 01 11 10 00 01 11 10
Q0 Q0 Q0
0 0 1 0 0 0 0 0 0 1 0 0 1 1 0

1 0 1 1 1 1 1 1 0 1 1 0 0 0 0

𝑄1 (𝑡 + 1) = 𝐸̅ 𝑄1 + 𝐸𝑄0
𝑄0 (𝑡 + 1) = 𝐸𝑄 ̅̅̅1 + 𝐸̅ 𝑄0
̅̅̅0̅
𝑧 = 𝑄1 𝑄

 Fifth step: Circuit implementation:

resetn
clk clock

D Q Q0 resetn

E
E
state S1 S1 S2 S3 S3 S4 S4 S1 S2 S2
D Q Q1

Q 00 00 01 11 11 10 10 00 01 01

z
z

Example: 2-bit counter with enable and ‘z’ output. The output ‘z’ is 1 when the present count is ‘11’. The count is the same as
the states encoded in binary.
 First step: Draw the State Diagram and State Table. If we were to implement the state machine in VHDL, this is the only
step we need.
E/z
resetn = 0 E PRESENT NEXT NEXT
0/0
STATE STATE COUNT z
1/0
0/0 S1 S2 0 S1 S1 00 0
0 S2 S2 01 0
1/1 1/0 0/0 0 S3 S3 10 0
0 S4 S4 11 1
1/0
0/1 S4 S3 1 S1 S2 01 0
1 S2 S3 10 0
1 S3 S4 11 0
1 S4 S1 00 1
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ECE-378: Digital Logic and Microprocessor Design Winter 2015

 Second step: State Assignment. We assign unique flip flop states to our state labels (S1, S2, S3, S4). Notice that this is
arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output ‘count’ is
just the flip flops’ outputs.

 S1: Q = 00
 S2: Q = 01
 S3: Q = 10
 S4: Q = 11

 Third step: Excitation table. Here, we replace the state labels by the flip flop states:
PRESENT STATE NEXTSTATE

E Q1(t) Q0(t) Q1(t+1) Q0(t+1) z

0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 1 1 1
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1

Example: BCD counter. Output ‘z’ becomes ‘1’ when the count is 1001.

resetn = '0'

S1 S2 S3 S4 S5
Q=0,z=0 Q=1,z=0 Q=2,z=0 Q=3,z=0 Q=4,z=0

S10 S9 S8 S7 S6
Q=9,z=1 Q=8,z=0 Q=7,z=0 Q=6,z=0 Q=5,z=0

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

ALGORITHMIC STATE MACHINE (ASM) CHARTS:

Sequence Detector (with overlap)
Gray counter, z=1 when Q=10
010011

x/z
E/z
resetn = 0 0/0 resetn = 0 0/0 1/0
1/0
0/0 S1 S2 0/0 1/0
S1 S2 S3
1/1 1/0 0/0 1/0
1/1 0/0 0/0 1/0
1/0
0/1 S4 S3
S6 S5 S4
1/0 0/0

0/0

resetn=0 resetn=0
S1 S1

0 1
E x

1 0
S2 S2

0 0
E x

1 1
S3 S3

0 1
E x

1 0
S4 S4
z1

1 0 1
E x
0
S5

0
x
1
S6

0 1
x z1

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ECE-378: Digital Logic and Microprocessor Design Winter 2015

Modifying the rate of change of a Finite State Machine:

 We usually would like to reduce the rate at which FSM transitions occur. A straightforward option is to reduce the frequency
of the input clock. But this is a very complicated problem when a high precision clock is required.

 Alternatively, we can reduce the rate at which FSM transitions occur by including an enable signal in our FSM: this means
including an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be ‘1’. Then we
assert the enable signal only when we need it. The effect is the same as reducing the frequency of the input clock.

 The figure below depicts a counter modulo-N (from 0 to N-1) connected to a comparator that generates a pulse (output
signal ‘z’) of one clock period every time we hit the count ‘N-1’. The number of bits the counter is given by 𝑛 = ⌈log 2 𝑁⌉.
The effect is the same as reducing the frequency of the FSM to 𝑓⁄𝑁, where 𝑓 is the frequency of the clock.

 A modulo-N counter is better designed using VHDL behavioral description, where the count is increased by 1 every clock
cycle and ‘z’ is generated by comparing the count to ‘N-1’. A modulo-N counter could be designed by the State Machine
method, but this can be very cumbersome if N is a large number. For example, if N = 1000, we need 1000 states.

resetn

E
Outputs
Inputs FSM
E E Q n

comparator z

Q=N-1?
counter
0 to N-1
clock

 As an example, we provide the timing diagram of the counter from 0 to N-1, when N=10. Notice that ‘z’ is only activated
when the count reaches “1001”. This ‘z’ signal controls the enable of a state machine, so that the FSM transitions only
occur every 10 clock cycles, thereby having the same effect as reducing the frequency by 10.

clk

resetn

Q 0000 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

 We can apply the same technique not only to FSMs, but also to any sequential circuit. This way, we can reduce the rate of
any sequential circuit by including an enable signal of every flip flop in the circuit.

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