20EC11T – Digital Electronics-Nov-21

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Scheme of valuation
Section-1

1. A. i) Definition of ASCII (1 Mark) + Listing any two features (1 x 2 =2 Marks)

1. A. ii) a) Octal equivalent (2 Marks) b) Hexadecimal equivalent (2 Marks) c) decimal equivalent (3
Mark)
1. B. i. a) Explanation of Octal system (2 Marks) b) Explanation of Hexadecimal system (3 Marks)
1. B. ii. Statement of Demorgan’s theorem (2 Marks) + Verification (3 Marks) [Any one theorem]
2. A. i) Listing any three-number system (1 x 3 =3 Marks)
2. A. ii) a) Subtraction (2 Marks) b) Addition (2 Marks) c) Multiplication (3 Marks)
2. B. i. Conversion steps (3 Marks) + Example (2 Marks)
2. B. ii. Realization of AND (2 Marks) + OR (2 Marks) + NOT (1 Mark)

Section-2

3. A. i) Definition of K-Map (1 Mark) + Need of K-Map (2 Marks)

3. A. ii) a) Kmap (1 Mark) +Simplified expression (1 Mark) + realization (1 Mark) b) Kmap (2 Mark)
+Simplified expression (1 Mark) + realization (1 Mark)
3. B. a) (2 x 5 =10 Marks) - Each gate realization carries 2 Marks each. [Symbol/Expression (1 Mark) +
Truth table (1 Mark) ]
4. A. i) Definition (1 Mark) + One example (2 Marks)
4. A. ii) a) For applying algebraic rule and simplifying carries 2 marks + realization (1 Mark) b) For
applying algebraic rule and simplifying carries 3 marks + realization (1 Mark)
4. B. i. SOP to POS Conversion using example problem – Step-1-(1 Mark) + Step-2-(2 Marks) + Final
Answer -(2 Marks)
4. B. ii. POS to SOP Conversion using example problem – Step-1-(1 Mark) + Step-2-(2 Marks) + Final
Answer -(2 Marks)

Section-3

5. A. i) Definition of Half Adder (1 Mark) + Truth table (1 Mark) + Logical expression (1 Mark) + Gate
level implement (2 Marks)
5. A. ii) Any 5 points. Each point carries 1 Mark each.
5. B. Block diagram (2 Mark) + Truth Table (3 Marks) + K-Map (A=B,A>B,A<B) (3 Marks) +
realization (2 Mark)

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6. A. i) Definition of Full Adder (1 Mark) + Truth table (2 Mark) + Logical expression (2 Mark)
6. A. ii) a) Block diagram (4 Marks) + Explanation (3 Marks)
6. B. Realization of AND (3 Marks) + OR (2 Marks) + EX-OR (3 Marks)

Section-4

7. A. i) Definition of Multiplexer (2 Mark) + Listing of any five applications carries 3 Marks.

7. A. ii) Block Diagram (3 Mark) + Truth Table (2 Marks)
7. B. a) Block diagram (4 Marks)
7. B. b) Block diagram (2 Mark) + Explanation (2 Marks) + Truth Table (2 Marks)
8. A. i) Definition of De-Multiplexer (2 Mark) + Listing of any five applications carries 3 Marks.
8. A. ii) Block Diagram (3 Mark) + Truth Table (2 Marks)
8. B. a) Final solution block diagram (4 Marks)
8. B. b) K-Map/Truth table (2 Marks) + Final solution block diagram (4 Marks)

Section-5

9. A. Logic Symbol (2 Marks) + Truth Table (3 Marks) + Boolean Expressions (2 Marks) + Gate level
implement (3 Marks)
9. B. i) Any 5 classification. Each carry 1 Mark each.
9. B. ii) Definition (1 Mark) + Diagram representation (1 Mark)
9. B. iii) Any three feature each carries 1 Mark each.
10. A. i) Logic circuit (2 Marks) + Truth Table (4 Marks) + Explanation (4 Marks)
10. B. i) Any 3 feature. Each carry 1 Mark each.
10. B. ii) Definition (1 Mark) + Diagram representation (1 Mark)
10. B. iii) Diagram (3 Marks) + Explanation (2 Marks)

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1) What is ASCII Code? List the any two features of ASCII code.

ASCII (AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE) CODE:

The standard binary code for the alphanumeric characters is the American Standard Code for Information
Interchange (ASCII), which uses seven bits to code 128 characters, It allows manufacturers to standardize
computer hardware such as keyboards, printers and video displays.

Features:

1. It has a total of 2^7(= 128) possible combinations to represent letters in the alphabet, punctuation
marks and numbers.
2. The code is divided into two groups as 3 + 4 bits. The first three bits in the code are used to identify
whether the remaining four bits represent letters, numerals, or punctuation marks. For example, 100
and 101 represent upper -case letters. Upper-case letter A is represented by 100 0001 (4116), B is
represented by 100 0001 (4216) and so on. 110 and 111 represent lower-case letters. Lower-case
letter a is represented by 110 0001 (6116), b is represented by 110 0001 (6216) and so on.
3. Redundant bits can be added for error-detection and correction.

1. ii)
a) Represent (1011100110)2 by its octal equivalent

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1. ii) b) Convert (423)10 to hexadecimal.

1. ii) c) Convert (24.6)8 to decimal

1. B. i) Explain Octal and Hexadecimal number system.

OCTAL NUMBER SYSTEM:

The octal number system has a base of 8, meaning that it has eight possible digits: 0, 1, 2, 3, 4, 5, 6
and 7. Thus, each digit of an octal number can have any value from 0 to 7. The octal system is a
positional-value system, wherein each digit has its own value or weight expressed as a power of 8.
The digit positions in an octal number have weights as shown in below table.

Examples of Octal Numbers : (256)8, (432.35)8, (250.06)8, (125.56)8 ,etc

HEXADECIMAL NUMBER SYSTEM:

The hexadecimal number system has a base of 16, meaning that it has 16 possible digits
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.. Thus, each digit of an hexadecimal number can have any value

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from 0 to F. This system is a positional-value system, wherein each digit has its own weight
expressed as a power of 16. The digit positions in a hexadecimal number have weights as shown

Hexadecimal numbers are used extensively in microprocessor based systems and computers. They
are shorter than binary numbers.
Examples of Hexadecimal Numbers : (24A6)16, (345F.50)16, etc

1. B. ii. State and prove Demorgan’s theorem

De Morgan’s First Theorem

DeMorgan’s first theorem is stated as follows in words:
The complement of a sum is equal to the product of the individual complements.
It says that the complement of two or more variables OR ed is the same as the AND of the
complements of each individual variable.

DeMorgan’s second theorem is stated as follows in words:

The complement of a product is equal to the sum of the individual complements.
It says that the complement of two or more variables ANDed is the same as the OR of the complements of
each individual variable.

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2. A. i) List different types of number system.

In general there are four different number system they are ;

1) Decimal Number System
2) Binary Number System
3) Octal Number System
4) Hexadecimal Number System

2. A. ii. a)(1101)2 - (111)2 = (?)2

2. A. ii. b) (4C)16 + (3A)16 = (?)16

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2. A. ii. c) (111)2 * (101)2 = (?)2

2. B. i. Illustrate the conversion from binary to gray code.

BINARY TO GRAY CONVERSION

In the conversion from binary to gray the following rules apply:
1. The most significant digit (left most) in the Gray code is same as the corresponding digit in the binary number.
2. Going from left to right, add each adjacent pair of binary digits to get the next Gray code digit, discard carry.
3. Let the binary number be B3B2B1B0 with B3being the MSB and B0 the LSB.
4. Let the corresponding Gray code be G3G2G1G0 with G3 being the MSB and G0 the LSB.
5. G3in the Gray code is the same as the corresponding digit B3in the binary number. That is,
G3= B3
The other bits in the Gray code are given by the following logical expressions:
G2= B3+ B2
G1= B2+ B1
G0= B1+ B0

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2. B. ii. Show realization of AND, OR and NOT gates using NOR gate.

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3. A. i. Define K-Map. Why it is used?

“Karnaugh Map is a graphical method, which consists of 2^n cells for n variables. The adjacent cells are
differed only in single bit position.”

Simplification of the Boolean functions having more than 4 variables using Boolean postulates and theorems is a
lengthy and time-consuming process. We must re-write the simplified expressions after each step which may add
error to the process. To overcome this difficulty, American physicist Maurice Karnaugh introduced a method for
simplification of Boolean functions in an easy way.

3. A. ii. Simplify following Boolean expression using K-Map and draw the logic diagram of simplified
expression.

a) Out = 𝐴 𝐵 + 𝐴̅ 𝐵 + 𝐴 𝐵
̅

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b) Out = 𝐴̅ 𝐵̅ 𝐶̅ + 𝐴̅ 𝐵̅ 𝐶 +𝐴̅ 𝐵 𝐶 + 𝐴̅ 𝐵 𝐶̅ + 𝐴 𝐵̅ 𝐶̅ + 𝐴 𝐵 𝐶̅

4. B. Explain following gates with symbol expression and truth table: AND, OR, NOR, NAND and
EXOR
AND Gate: The Symbol, expression, and the truth table of AND gate

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OR Gate: The Symbol, expression, and the truth table of OR gate

NOR Gate: The Symbol, expression and the truth table of NOR gate

NAND Gate: The Symbol, expression and the truth table of NAND gate

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EX-OR Gate: The Symbol, expression, and the truth table of EX-OR gate

4. A. i) Define Duality theorem and give examples

The duality theorem is one of those elegant theorems proved in advanced mathematics. We will state the
theorem without proof. Here is what the duality theorem says.
Starting with a Boolean relation, you can derive another Boolean relation by
1. Changing each OR sign to an AND sign.
2. Changing each AND sign to an OR sign.
3. Complementing any 0 or 1 appearing in the expression.
1) F or instance, Eq. says that
A+0=A .
The dual relation is A· 1 =A.
This dual property is obtained by changing the OR sign to an AND sign, and by complementing the 0 to get
a 1. The duality theorem is useful because it sometimes produces a new Boolean relation.

4. B. Simplify following Boolean expression using Boolean Algebra and realize using logic gates.
a) Out = 𝐴 𝐵 + 𝐴̅ 𝐵 + 𝐴 𝐵̅

Out = 𝐴 𝐵 + 𝐴̅ 𝐵 + 𝐴 𝐵
̅

= 𝐵 ( 𝐴 + 𝐴̅ ) + 𝐴 𝐵
̅ ( 𝐴 + 𝐴̅ = 1)

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̅
= 𝐵 ( 1) + 𝐴 𝐵 𝐵 ( 1) = 𝐵
̅
=𝐵+𝐴𝐵 𝐵 + 𝐴 𝐵̅ = 𝐵 + 𝐴
Out =𝐵+𝐴

Out =𝐴+𝐵

b) Out = 𝐴̅ 𝐵̅ 𝐶̅ + 𝐴̅ 𝐵̅ 𝐶 +𝐴̅ 𝐵 𝐶 + 𝐴̅ 𝐵 𝐶̅ + 𝐴 𝐵̅ 𝐶̅ + 𝐴 𝐵 𝐶̅

Out = 𝐴̅ 𝐵̅ 𝐶̅ + 𝐴̅ 𝐵̅ 𝐶 +𝐴̅ 𝐵 𝐶 + 𝐴̅ 𝐵 𝐶̅ + 𝐴 𝐵̅ 𝐶̅ + 𝐴 𝐵 𝐶̅

= 𝐴̅ 𝐵̅ ( 𝐶̅ + 𝐶) + 𝐴̅ 𝐵 ( 𝐶 + 𝐶̅ ) + 𝐴 𝐶̅ ( 𝐵̅+ 𝐵 )

= 𝐴̅ 𝐵̅ ( 1) + 𝐴̅ 𝐵 ( 1 ) + 𝐴 𝐶̅ ( 1 )

= 𝐴̅ 𝐵̅ + 𝐴̅ 𝐵 + 𝐴 𝐶̅

= 𝐴̅ (𝐵̅ + 𝐵) + 𝐴 𝐶̅

= 𝐴̅ (1) + 𝐴 𝐶̅

= 𝐴̅ + 𝐴 𝐶̅

Out = 𝐴̅ + 𝐶̅

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4. B a) Illustrate SOP to POS conversion: F (A, B, C) = ∑ (0, 2, 3, 5, 7).

To convert the SOP form into POS form, follow the steps below
Step 1: we should change the Σ to Π.
Step 2: write the numeric indexes of missing variables of the given Boolean function.

Step 1: changing the operational sign to Π

Step 2: writing the missing indexes of the terms, 001(1), 100(4) and 110(6). Now write the sum form for
these noted terms.

Writing down the new equation in the form of POS form,

4. B. b) Illustrate POS to SOP conversion: F (A, B, C) =Π (2, 3, 5)

To convert the POS form into SOP form, follow the steps below
Step 1: we should change the Π to Σ
Step 2: write the numeric indexes of missing terms of the given Boolean function.

Step 1: Changing the operational sign to Σ

Step 2: Writing the missing indexes of the terms, 000(0), 001(1), 100(4), 110(6) and 111(7). Now write the
product form for these noted terms.

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Writing down the new equation in the form of SOP form,

5. A. i) Define Half Adder. Write the truth table, logical expression, and gate level implementation of
Half Adder.
Half Adder is a combinational circuit that adds two binary digits (addend and augend) to produce sum (S)
and carry (C0).

Truth table of Half Adder:

Logic Equation:
From the above truth table, the simplified Boolean functions

Therefore, S can be implemented using an EX -OR and Co can be implemented using AND gate

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5. A. ii. Compare: Serial Adders and Parallel Adders

SERIAL ADDERS PARALLEL ADDERS

Adds only one bit at a time All bits are added at a time

Time required for addition depends on Time required for addition does not
number of bits depends on number of bits
Speed of response is slower Speed of response is faster

Requires only one full adder Number of full adders is equal to number of
bits in the binary number
They use shift registers They use registers with parallel load
capacity
They are cheaper They are expensive

5. B. Develop a 2-bit magnitude comparator, and implement it using gates.

Two-Bit magnitude comparator:

A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude comparator. It
consists of four inputs and three outputs.
The figure below shows the block diagram of a 2 - bit magnitude comparator.

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Truth table of 2-bit magnitude comparator:

K-map Simplification:

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GATE LEVEL IMPLEMENTATION

6. A. i. Define Full Adder. Write the truth table, logical expression, and gate level implementation of Full
Adder.
A FULL-ADDER is a combinational arithmetic logic circuit that performs addition of three binary digits and
generates two outputs. It is used for adding two input bits and an input carry and generates a sum and carry output.
The two inputs are taken as A and B, they represent the two significant bits to be added. The third input Cin, represents
the carry from the previous lower significant bit (LSB) position.

Figure below shows the block schematic of FULL-ADDER.

TRUTH TABLE

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Logic Equation:
From the above truth table, the simplified Boolean functions

Logic Diagram:

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6. A. ii) Explain working of 3-bit Parallel Adder with block diagram.

A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary numbers in parallel.
It consists of full adders connected in a chain, with the output carry from each full adder connected to the
input carry of next full adder in the chain. Thus several full adders are connected to form adders that add
several bits at one time. A three bit parallel adder consists of three full adders, with the output carry from
each full adder connected to the input carry of next full adder in the chain.

Working of 3-bit parallel Adder:

1) As shown in the above figure, the first full adder FA1 adds A1 and B1 along with
the carry Ci1 to generate the sum S1 (the first bit of the output sum) and the carry
Co1 which is connected to the next adder in chain.

2) The second full adder FA2 uses this carry bit as an input carry bit Ci2 to add with
the input bits A2 and B2 to generate the sum S2(the second bit of the output sum)
and the carry Co2 which is again further connected to the next adder in chain

3) The third full adder FA3 uses this carry bit as an input carry bit Ci3 to add with
the input bits A3 and B3 to generate the sum S3(the third bit of the output sum) and
the carry Co3 .

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6. B. Construct AND, OR and EXOR gate using 2:1 Multiplexer.

Implementation of AND gate using 2 : 1 Mux

Implementation of OR gate using 2 : 1 Mux

Implementation of EX-OR gate using 2 : 1 Mux

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7. A. i. Define Multiplexer and List any five applications.

A multiplexer (MUX), also known as a data selector, is a device that selects between several analog or digital input
signals and forwards the selected input to a single output line. The selection is directed a separate set of digital inputs
known as select lines. A multiplexer of inputs has select lines, which are used to select which input line to send to
the output.

APPLICATIONS OF MULTIPLEXERS.

A Multiplexer is used in numerous applications like, where multiple data can be transmitted using a single line.

Communication System: A Multiplexer is used in communication systems, which has a transmission system and
a communication network. A Multiplexer is used to increase the efficiency of the communication system by
allowing the transmission of data such as audio & video data from different channels via cables and single lines.

Computer Memory: A Multiplexer is used in computer memory to keep up a vast amount of memory in the
computers, and to decrease the number of copper lines necessary to connect the memory to other parts of the
computer.

Telephone Network: A multiplexer is used in telephone networks to integrate the multiple audio signals on a
single line of transmission.

Transmission from the Computer System of a Satellite: A Multiplexer is used to transmit the data signals from
the computer system of a satellite to the ground system by using a GSM communication.

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Data Routing: Multiplexers are extensively used in data routing applications to route the data to a one particular
destination from one of several sources.

Logic Function Generator: In place of logic gates, a logical expression can be generated by using a multiplexer.
It is possible to connect the multiplexer such that it duplicates the logic of any truth table. In such cases it can
generate the Boolean algebraic function of a set of input variables.

Parallel to Serial Conversion: A multiplexer circuit can be used to convert the parallel data to serial data, so as to
reduce parallel buses to serial signals. This type of conversion is needed in telecommunication, test and
measurement, military/aerospace, data communications applications.

Operation sequencing: Sequence of operation can be done by using multiplexer. Wave form generation: Wave
form can be generating by using multiplexer for different applications.

7. A. ii) Explain 2:1 Multiplexer with block diagram and truth table.
2:1 MULTIPLEXER

A 2-to-1 multiplexer is the digital multiplexer circuit that has two data inputs x1 and x2, one selects line S and one
output f. To implement a 2-to-1 multiplexer circuit we need 2 AND gates, an OR gate, and a NOT gate.

The block diagram, logic symbol and switching circuit analogy of 2-to-1 multiplexer is shown in the figure below.

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7. B. ii) a) Construct 4:1 Multiplexer using 2:1 Multiplexers.

REALIZATION OF 4:1 MUX USING 2:1 MUX

Let us implement 4x1 Multiplexer using 2x1 Multiplexers. We know that 2x1 Multiplexer has 2 data inputs, 1
selection lines and one output. Whereas, 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output.

So, we require two 2x1 Multiplexers in first stage to get the 4 data inputs. Since, each 2x1 Multiplexer produces
one output, we require a2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to
produce the final output.

Let the 4x1 Multiplexer has four data inputs I3 to I0, two selection lines S1 &S0 and one output Y. When we select
selection lines, makes sure that order is correct. I.e. First stage mux with selection line S0 and second stage mux
S1.

The Pin diagram, circuit connection, Truth table, and logical expression of 4x1 Multiplexer

is shown below.

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7. B. ii) b) Explain 1:8 Demultiplexer using gates with the help of truth table.
1-to-8 Demultiplexer
1) A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3 select lines. Let the input be D,
S1 and S2 are two select lines and eight outputs from Y0 to Y7.
2) The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of single input D,
three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
3) It distributes one input line to one of 8 output lines depending on the combination of select inputs.

The truth table of 1 to 8 demux is shown with 3 select inputs S0, S1, S2 & 8 outputs Y0 to Y7. From
truth table, the Boolean expressions for all the outputs can be
written as-

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8) A. i) Define De-Multiplexer and List any five applications.

A demultiplexer is a combinational logic circuit that receives the information on a single input and
transmits the same information over one of 2^n possible output lines.

Applications of Demux
1) A demultiplexer is used to connect a single source to multiple destinations. Demultiplexers are mainly
used in the field of the communication system.
2) A serial to parallel converter is used for reconstructing the parallel data from the incoming serial data
stream. In this technique, serial data from the incoming serial data stream is given as the input to the
DEMUX at regular intervals. When all data signals have been stored. The output of the demux can be
retrieved and read out in parallel.
3) Demultiplexer helps to store the output of the ALU in multiple registers and storage units in an ALU
circuit. The output of the data the ALU is fed as data input to the DEMUX. Each output of the
DEMUX is connected to the multiple registers which can be stored in the register.
4) Boolean function implementation
5) Security monitoring system (Mux used for selecting a particular surveillance camera at a time)
6) Extensively used in microprocessor or computer control systems

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8) A. ii) Explain 1:2 De-Multiplexer with block diagram and truth table.

In this demux, there are only two possible ways to connect the input to output lines by using one select signal.
When the select input is low, then the input is routed to Y0 When select input is high, then the input is routed to Y1.
The truth table of 1 : 2 demux is shown below:

8) B. a) Design the function F (A, B, C) = Σ (1, 2, 5, 7) using 8 to 1 MUX

We can implement it using all three variables at selection lines. We put 1 on the min term lines which are present in
functions and 0 on the rest.

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7) B. b) Design the function F (A, B, C) = Σ (1, 2, 5, 7) using 4 to 1 MUX

Solution: - Method 1:- Analyzing truth table

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Method 2:- Using implementation table

9. A. Sketch and Explain Decimal to BCD Encoder with Logic symbol, truth-table Boolean expression,
logic diagram using gates.

Decimal to BCD Encoder

1) The decimal to binary encoder usually consists of 10 input lines and 4 output lines.
2) Each input line corresponds to the each decimal digit(0 to 9) and 4 outputs correspond to the BCD
code.
3) This encoder accepts the decimal data as an input and encodes it to the BCD output which is available
on the output lines.

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Logic Symbol

Truth table

Boolean Expressions:
Y0 = D1 + D3 + D5 + D7 + D9
Y1 = D2 + D3 + D6 + D7
Y2 = D4 + D5 + D6 + D7
Y3 = D8 + D9

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Logic Diagram

9. B. i) List IC classification based on scale of integration

IC classification based on scale of integration:

As the technology is improving day by day, the number of transistors incorporated in a single IC chip is also
increasing. Depending uponthe number of transistors incorporated in a single chip the ICs are categorized in
five groups. Namely
a. Small Scale Integration (SSI)where the number of transistors incorporated in a single IC chip is up
to 100
b. Medium Scale Integration (MSI)where the number of transistors incorporated in a single IC chip is
from 100 to 1000
c. Large Scale Integration (LSI)where the number of transistors incorporated in a single IC chip is from
1000 to 20,000.
d. Very Large-Scale Integration (VLSI)where the number of transistors incorporated in a single IC chip
is from 20,000 to 10,00,000.
e. Ultra-Large-Scale Integration (ULSI)where the number of transistors incorporated in a single IC chip
is from 10,00,000 to 1,00,00,000
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9. B. ii) Explain Fan-out with respect to logic family specification.

Fan out:
The fan-out is defined as the maximum number of inputs (load) that can be connected to the output of a gate
without degrading the normal operation.

Fan Out is calculated from the amount of current available in the output of a gate and the amount of current
needed in each input of the connecting gate. It is specified by manufacturer and is provided in the data sheet.
Exceeding the specified maximum load may cause a malfunction because the circuit will not be able supply
the demanded power.
For example, a logic gate having fan out of 4 can drive at the maximum 4 logic inputs Only

9. B. iii) Describe the features of TTL family.

Features and Merits of TTL
a. High speed of operation.
b. Low cost of manufacturing.
c. Requires only one supply voltage.
d. Lesser immune to noise when compared to ECL, but more than CMOS.
e. Fastest saturation, when compared to other logic families.
f. Low output impedance for high/low states.
g. Good fan out.
h. Immune to static noise
i. Compatible with other logic families.
j. Good driving/Interfacing.
k. Moderate packing density.

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10. A. Sketch and Explain BCD-to-seven segment decoder (IC7447) with Logic circuit and truth-table.
BCD-to-7 segment decoder
In most of the practical applications seven segment displays are used to give visual indications (characters

and numbers) of the output states of digital IC’s such as decade counters, latches etc. Thus outputs are

usually in 4 bit BCD (Binary Coded Decimal) form and are thus notavailable for driving seven segment

displays.

So, the special BCD-to-seven segment decoder/driver ICs’ are used to convert BCD signal into a form

suitable for driving these displays. Seven segment decoder / driver is a digital circuit that can decode a

digital input to the seven-segment format and simultaneously drive a 7-segment LED display using the

decoded information. What that will be displayed on the 7-segment

display is the numerical equivalent of the input data. For example, a BCD to seven segment decoder driver

can decode a 4 line BCD (binary coded decimal) to 8 line seven segment format and can drive the display

using this information.Generally, it has 4 input lines and 8 output lines as shown in figure

IC 7447 BCD-to-seven segment Decoder/Driver

IC 7447 is a BCD -to- seven segment Decoder which translates the 8421 BCD code to a code that lights the

proper segments on the common -anode seven-segment LED display.

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 20EC11T – Digital Electronics-Nov-21

IC 7447 is one such IC with active low outputs. Seven segment displays make use of segments, and each

segment contains and the seven LED are labelled from a to g. The digits from 0 to 9 can be displayed by

forward biasing the different LEDS.

The IC is stand alone and requires no external components other than the LED current limiting resistors.

The display used here must be a common anode type because the IC has active low outputs.

Logic Circuit

Truth Table

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 20EC11T – Digital Electronics-Nov-21

10. B. i) List the features of CMOS Logic family.

Features and Merits of CMOS

a. MOSFETS are active switching elements.
b. CMOS supports a very large fan-out, more than 50 transistors.
c. Low power consumption.
d. It has excellent noise immunity amongst all families.
e. Requires very less chip area and it has greater packing density.
f. Excellent temperature stability.
g. Works well over a wide range of temperature.
h. They are used in portable electronics.
i. Large logic swing.
j. Simpler and inexpensive to fabricate because of the reduction in the number of external
connections.
k. Requires less chip area and it has greater packing density.
l. Higher reliability.

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m. CMOS devices can work with a single power supply over a range of 3 to 15V (simple and
inexpensive). The best compromise for speed, noise immunity, and overall performance is a supply
voltage from 9V to 12V

10. B. ii) Explain Fan-in with respect to logic family specification.

Fan in:
The fan-in defined as the maximum number of inputs that a logic gate can accept. If number of inputs exceeds,
the output will be undefined or incorrect. It is specified by manufacturer and is provided in the data sheet

10. B. iii) Describe the interfacing between CMOS to TTL.

The below figure shows a CMOS-to-TTL interface with both devices operating from 5V supply
and the CMOS IC driving a low-power TTL or a low-power Schottky TTL device.

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 20EC11T – Digital Electronics-Nov-21

Certificate
Certified that the model answers prepared by me for code no 20EC11T (Digital Electronics)
are from prescribed textbooks and model answers and scheme of valuation prepared by me are
correct.

SATHEESHA K M
LECTURER, E&C DEPT
KARNATAKA GOVT POLYTECHNIC,MANGALORE

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