Computer Architecture (CS F342)

Semester-I, 2023-24
Comprehensive Examination
Department of Computer Science and Information Systems (CSIS)
BITS-Pilani, K K Birla Goa Campus, Goa, India.
Date: Dec 13, 2023: 2 PM to 5 PM Marks: 95
Instructions:
Write down the assumptions along with the answer wherever required, and do not ask doubts. No marks will be
awarded for the questions if no reasoning is found in the answer script. You must continuously write all answers to
a question, not here and there, within the answer script. All questions are mandatory, and adjust time accordingly
while answering. Don’t waste time writing stories.

1. (a) [Marks: 3*2] Consider the shared bus-based MIPS processor’s datapath, given here, and write down the steps and
corresponding control signals associated with it for instruction fetch-and-decode operation, LW instruction, and BNE
instruction.
(b) [Marks: 10] What’s the purpose of ALUOut register in multi-cycle MIPS processor? The designer wants to remove
the ALUOut register from the processor. The datapath is available here. Help the designer modify the processor to
execute all the instructions discussed in the classes. What’s the clock period (T) of the modified processor?
(c) [Marks: 2] The designer wants to incorporate BNE, BEQ, BLEZ, and BGTZ instructions; detailed information is
available in Table-1 in a multi-cycle MIPS processor. Show the modification in the datapath and answer only the
modified parts.
(d) [Marks: 2] What’s horizontal microprogramming? How does the designer incorporate all instructions in (c) into a
horizontal microprogrammed control unit?
[Total marks: 20]
2. (a) [Marks: 1] How does the 5-stage pipelined MIPS microprocessor resolve the dependency in the H/W level between
the 5th stage and 2nd stage? Describe the concept only with some specific terminology used in MIPS.
(b) [Marks: 1] Which stages have the dependencies if the branch decision is taken at the 2nd stage instead of the 3rd
stage of the 5-stage pipeline MIPS microprocessor, and how does one resolve such dependencies? Describe the concept
only with some specific terminology used in MIPS.
(c) [Marks: 1] Can we directly program the stage registers MIPS microprocessor? Justify your answer.
(d) [Marks: 1 + 1] How do you create a 5-stage MIPS pipeline processor? Describe the concept only (don’t write
stories). What signals and/or values are available in the EX_MEM stage register for the instructions discussed in the
class?
(e) [Marks: 3] Write down the algorithmic steps to generate a general-purpose processor discussed in the classes.
(f) [Marks: 3] Derive the general equation for determining the trade-off between cost and performance for designing
the pipelined-based microprocessor. Describe all steps clearly.
(g) [Marks: 5] Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute
(EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle.
Assume that the ID stage merely decodes the instruction, and the register read is performed in the EX stage. The EX
stage takes one cycle for ADD instruction, and the register read is performed in the EX stage. The EX stage takes one
cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies.
Consider these sequence of instructions: MUL, ADD, MUL, ADD, MUL, ADD, MUL, ADD
Assume that every MUL instruction (except the first MUL) is data-dependent on the ADD instruction just before it,
and every ADD instruction is data-dependent on the MUL instruction just before it. The speedup is defined as
follows:
𝐸𝑥𝑒𝑐𝑢𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ𝑜𝑢𝑡 𝑜𝑝𝑒𝑟𝑎𝑛𝑑 𝑓𝑜𝑟𝑤𝑎𝑟𝑑𝑖𝑛𝑔
𝑆𝑝𝑒𝑒𝑑𝑢𝑝 =
𝐸𝑥𝑒𝑐𝑢𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 𝑤𝑖𝑡ℎ 𝑜𝑝𝑒𝑟𝑎𝑛𝑑 𝑓𝑜𝑟𝑤𝑎𝑟𝑑𝑖𝑛𝑔
Properly show the pipeline schedule table (Instructions, clock cycle) with stage usage for both cases and calculate the
speedup.
[Total Marks: 14]

3. (a) [Marks: 4.5] Consider a cache with 256 bytes. The word size is 4 bytes, the block size is 16 bytes, and the
replacement algorithm is LRU. Show the values in the cache and tag bits after each memory access operation for the
two-way associative cache memory. Also, mention whether the access was a hit or miss. Justify. The address is
presented in hexadecimal.

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 1. Read 0010, 2. Read 001C, 3. Read 0018, 4. Write 0010, 5. Read 0484, 6. Read 051C, 7. Read 001C, 8. Read 0210,
9. Read 051C
(b) [Marks: 3.5] Why is it called a “pseudo” in the pseudo-LRU algorithm? Explain the pseudoness as a case for a 3-
bit tree PLRU with an example.
(c) [Marks: 5] Consider the C declaration of the cache memory with 256 lines and a 64K memory.

typedef struct { int tag; char block[4]; } cache_line; cache_line cache[256]; char memory[65536];

Define the two functions: bool requestMemoryAddress(unsigned int addrs) and unsigned int
getPercentageOfHits(void). The 1-st function takes the address and checks to see if it exists in the cache. It returns a
value True if the address is found in the cache. Otherwise, it returns False. The second function returns an integer value
between 0 and 100, indicating the percentage of cache successful hits. Make valid assumptions and solve it.
(d) [Marks: 1+2+2+1] What’s the primary miss in the MSHR context? Describe the purpose of different fields in the
MSHR file. Define only the data structure using C for the MSHR file having eight entries in the MIPS processor
discussed in the class. Would there be an entry in the MSHR file for prefetch requests? Justify.
[Total Marks: 19]
4. (a) [Marks: 3] Consider the program’s reference pattern of accessing the blocks 0, 4, 0, 8, 0, 8, 0, 4, 0, 4, 0, 4. Assuming
that the set size is 2, find the hit ratio with a cache size of four cache lines and the hybrid replacement policy with 2-bit
SCTR discussed in class. An update to the SCTR would be based on the difference (minus) between the outcomes of
the two policies. Show all the steps in the calculation of the hit ratio; otherwise, marks will be deducted.
(b) [Marks: 8] Write a C/C++ code for the hybrid cache replacement policy controller, discussed in class for the fully
associative cache with parameters: cache size (C words), block size (B words), and 2bit SCTR. You have to define a
set of functions provided in Table 3. Update to the SCTR as in 4(a). The cache_trace.txt file contains the LW traces for
MIPS processor as in lab. assignment.
(c) [Marks: 4] Consider the systems with a byte-addressable main memory of 216-bytes. Assume that a direct-mapped
data cache consisting of 16 lines of 64 bytes each is used in the system. A 40 x 40 two-dimensional array of bytes is
stored in the main memory, starting from 1000H. Assume that the data cache is initially empty. The complete array is
accessed once. Assume that the contents of the data cache do not change during the access. How many data misses will
occur in total? Show each step clearly; otherwise, marks will be deducted.
(d) [Marks: 3] Now consider the same cache memory as in 4(d) with the tagged-based next-line prefetcher, and the
same array is accessed once. How many data misses will occur in total? Show each step clearly; otherwise, marks will
be deducted.
[Total Marks: 18]
5. (a) [Marks: 4] Show BTB organization having a 1-bit predictor with an initial state of 0. Is BTB a cache memory?
Justify your answer. Suppose 32-bit MIPS instructions are stored in the memory location, increasing order starting from
0x00000000. Show the steps for accessing the BTB with 8 entries when we fetch such instructions one after another
from Table-2. First fetch ADD $S0, $S1, $S2. What’s the overall size of such a BTB? Make valid assumptions and
solve it.
(b) [Marks: 4] Find a string where the prediction accuracy for a 1-bit predictor is 50%, and for a 2-bit saturation
counter, with state’s change, only single bit and the initial state is NT (01), is 0%, in steady-state. Can you think of a
programming pattern that fits this type of string?
(c) [Marks: 6] Write the C code for int getPrediction() and void updatePred(), the n-bit branch predictor, assuming
branch traces come from a file. The trace format is B_PC<\t><1/0>, and each trace is started in a new line. B_PC is the
PC value of the branch instruction, <\t> is a tab, and ‘1’ is if the branch decision is taken; otherwise, ‘0’. The
getPrediction() returns a ‘1’ or ‘0’, and updatePred() returns nothing. Choose the arguments of the functions correctly.
(d) [Marks: 3] Write a branchless C function (make your assumption for parameters) for counting the number of
elements in the array, “sets”, larger than and smaller than the given number “item” and print such counts.
(e) [Marks: 5] The designer wants to design a branch predictor with a combination of a bimodal (PB) and a GShare
(PG) branch predictor. Help the designer to combine the two predictors. Draw the proposed efficient architecture and
write down its working principle.
[Total Marks: 22]
Table-1
-: End :- Table-2
Instruction Operation
beq $s, $t, label If ($s == $t) pc += i << 2 ADD $S0, $S1, $S2
bgtz $s, label If ($s > 0) pc += i << 2
BNE LBL1
blez $s, label If ($s <= 0) pc += i << 2
bne $s, $t, label If ($s != $t) pc += i << 2 SUB $S2, $S1, $S3
Remember the BNE instr. discussed in classes.
Same goes for all other instructions. J LBL2

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 Fig. 1

Fig. 2

unsigned int ATDRan[lines][tags], ATDLru[lines][tags], MTD[lines][tags], MTD[lines][block], SCTR;

bool findATDRan(lineNo, blockNo, A_MTD); //returns true if blockNo is present in A_MTD and returns cache line using lineNo.
//The lineNo indicates expected block’s position, including replacement one.
//One can pass ATD or MTD using the A_MTD parameter.
bool findATDLRU(lineNo, blockNo, A_MTD); //returns true if blockNo is present in A_MTD and returns cache line using lineNo
//as in previous function.
updateSCTR(); //define it
updateRan(lineNo, blockNo, A_MTD); //define it
updateLRU(lineNo, blockNo, A_MTD); //define it Table-3
bool findMTD(lineNo, blockNo); //define it
//Valid assumption can be made if require. Don’t ask doubts.

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