Unit-IV

Q1. What is the need of memory expansion and I/O expansion in microcontroller.

Ans. Memory expansion and I/O expansion in a microcontroller are needed when the on-chip
memory or input/output pins provided by the microcontroller itself are not sufficient for the
application's requirements, allowing developers to add more memory storage and external devices
by connecting additional chips to the microcontroller through dedicated interfaces like SPI or I2C,
without needing to switch to a more expensive or powerful microcontroller with more built-in
resources.

Memory expansion:

• Larger data storage:

When an application needs to store a large amount of data, such as in complex sensor readings,
image processing, or large data buffers, the on-chip RAM might not be enough, requiring external
memory chips to be added for additional storage.

• Flexibility in memory types:

Depending on the application, different types of memory like flash memory for storing program
code or EEPROM for non-volatile data storage can be added through memory expansion.

I/O pins

• More input/output pins:

Many applications require a large number of input and output pins to interact with various sensors,
actuators, and other peripherals, which might exceed the limited number of I/O pins available on
the microcontroller.

• Cost-effective design:
Using I/O expander chips allows developers to choose a microcontroller that meets the core
processing needs while adding additional I/O functionality only where necessary, thus optimizing
the overall system cost.

Q2. What are control signals. How memory wait states affect the system in microcontroller.

Ans, When expanding the memory of an 8051 microcontroller, the key control signals used
are "PSEN" (Program Store Enable) for accessing external program memory and "ALE" (Address
Latch Enable) for latching the memory address, while "memory wait states" are added to the clock
cycle to accommodate slower external memory access times compared to the internal memory.

Key points about 8051 memory expansion and control signals:

• PSEN (Program Store Enable):

This is the primary signal used to activate external program memory access; when asserted high,
it enables the external EPROM or flash memory to output data onto the data bus.

• ALE (Address Latch Enable):

This signal is used to latch the address placed on the address bus onto the external memory chip
during a memory access cycle.

• Other control signals:

Depending on the memory type, additional signals like "RD" (Read) and "WR" (Write) might be
required to control data transfer direction.

Memory wait states:

• Function:

When accessing slower external memory, the 8051 can insert additional clock cycles (wait states)
into the memory access cycle to allow sufficient time for the external memory to respond.

• Implementation:
Wait states are configured by setting the appropriate pin connections on the memory chip and
adjusting the timing parameters in the system design.

How it works:

1. . Address generation:

The 8051 places the memory address on the address bus.

2. . ALE signal:

The ALE signal is asserted high to latch the address onto the external memory chip.

3. PSEN signal:

If accessing external program memory, the PSEN signal is activated, enabling the external memory
to output data.

4. Data transfer:

During the appropriate clock cycles (including any wait states), the data is read from or written to
the external memory.

Control Signals:

Control signals are digital signals used to coordinate and manage various operations within a
microcontroller system. They're like traffic signals that orchestrate the flow of data and operations.
Here are the key aspects:

1. Primary Control Signals:

- Read (RD): Indicates a memory or I/O read operation

- Write (WR): Signals a memory or I/O write operation

- Chip Select (CS): Activates specific memory or peripheral devices

- Address Latch Enable (ALE): Used to latch address information

- Program Store Enable (PSEN): Used to read from program memory

2. Functions:

- Synchronization between CPU and peripherals

- Managing data transfer between components

- Controlling bus access and timing

- Enabling/disabling various system components

- Coordinating memory operations

Memory Wait States:

Wait states are additional clock cycles inserted into memory access operations when the memory
device cannot operate at the same speed as the CPU. Here's how they affect the system:

1. Performance Impact:

- Each wait state adds one clock cycle to memory access time

- Slows down program execution

- Reduces overall system throughput

- Increases instruction execution time

2. Necessity:

- Required when using slower memory devices

- Helps prevent timing violations

- Ensures reliable data transfer

- Accommodates devices with different access times

3. System Effects:

- CPU must wait for memory operations to complete

- Increases power consumption due to longer execution times

- Can affect real-time response in time-critical applications

- May require software optimization to minimize impact

4. Configuration:

- Usually programmable through memory controller registers

- Can be set differently for different memory regions

- May be dynamic based on operating conditions

- Often configured during system initialization

To optimize system performance, developers should:

- Use fast memory devices when possible to minimize wait states

- Carefully place time-critical code in faster memory regions

- Consider using memory caching techniques

- Balance cost versus performance when selecting memory components

For example, if a microcontroller runs at 50 MHz (20ns cycle time) but the memory requires 70ns
access time, you would need to insert wait states to ensure reliable operation:

70ns ÷ 20ns = 3.5 cycles, rounded up to 4 cycles

Therefore, 3 wait states would be needed (1 normal cycle + 3 wait states = 4 cycles total)

This fundamental understanding of control signals and wait states is crucial for designing efficient
microcontroller systems and troubleshooting timing-related issues.

Q3. What do you mean by external memory. Why it is necessary in 8051 . how do we interface
with 8051 microcontroller.

Ans. The 8051 microcontroller is a popular microcontroller used in various applications, ranging
from small embedded systems to larger industrial applications. While the 8051 has a limited
amount of internal memory, it is possible to extend the memory capacity by interfacing it with
external memory devices.

External memory interfacing in 8051 microcontroller involves connecting external memory

devices such as RAM and ROM to the microcontroller to provide additional memory space. This
allows the microcontroller to execute larger and more complex programs, store more data, and
perform more complex operations.

External memory interfacing typically involves connecting the memory devices to the
microcontroller through a data bus and an address bus. The data bus is used to transfer data between
the microcontroller and the memory device, while the address bus is used to select a specific
memory location in the memory device.

To interface with external memory, the 8051 microcontroller uses dedicated pins such as ALE
(Address Latch Enable), PSEN (Program Store Enable), and RD (Read) and WR (Write) signals.
These signals are used to control the flow of data between the microcontroller and the external
memory device.

For minimal memory applications, the 8051 has internal data and code memory. In such a position.
For certain applications, this memory capacity will not be adequate. To expand the memory space
of the 8051 micro-controller, we must bind external ROM/EPROM and RAM. We also understand
that ROM serves as program memory and RAM serves as data memory. Let’s take a look at how
8051 accesses these memories.

Why need External Memory Interfacing in 8051 Microcontroller ?

External memory interfacing is necessary in the 8051 microcontroller for several reasons:

1. Limited internal memory: The 8051 microcontroller has a limited amount of internal
memory, including 128 bytes of RAM and 4KB of on-chip ROM. This memory may not
be sufficient for some applications that require larger program memory or more data
storage.

2. Larger programs: For applications that require larger programs, such as complex
algorithms or multiple functions, external memory interfacing can provide the necessary
program memory space to store these programs.

3. Data storage: Applications that require the storage of large amounts of data, such as data
logging or data analysis, may require external memory interfacing to store the data.

4. Flexibility: External memory interfacing provides greater flexibility in the design of

embedded systems, allowing for customization and adaptability to meet specific
application requirements.

5. Cost-effective: External memory devices such as RAM and ROM are relatively
inexpensive, making it cost-effective to interface them with the microcontroller instead of
using more expensive on-chip memory.
 Memory Capacity Address Line Required

1 K = 1024 memory locations 10

2 K = 2048 memory locations 11

4 K = 4096 memory locations 12

8K= 8192 memory locations 13

16 K = 16384 memory locations 14

 Memory Capacity Address Line Required

32 K = 32768 memory locations 15

64 K = 65536 memory locations 16

• The memory chip has 11 address lines A10-A0, one chip pick (CS), and two control lines,
as seen in the table. To allow the output buffer, press RD, and to enable the input buffer,
press WR.

• The address lines are decoded using the internal decoder: (b) displays the logic diagram of
a 4096 (4 K) register EPROM (Erasable Programmable Read-Only Memory).

• It has a total of 12 address blocks. One chip pick (CS) and one read control signal (A11-
A0). EPROM does not need the (WR) signal since it is a read-only memory.

• Memory and 1/0 modules are used in the microprocessor/microcontroller framework.

Since the data, address, and control buses are shared by all devices, the microprocessor can
only communicate (read/write) with one device at a time.

• It is essential to decoding the address from the microprocessor/microcontroller in order to

connect with memory or I/O devices.

Q4. Explain interfacing of 8K PROM to the microcontroller.

Ans

As we know 8k PROM =

8*1024 = 2 3 * 210 = 213

A0 – A12 lines are used for addressing the PROM remaining A13-A15 will act as low
i
 1. When we connect PSEN to the ground, then the 8051 microcontroller fetches the opcode
from the external ROM.

2. But, when we connect PSEN to VCC, the status of the PSEN is ‘not activated’ since it is
an active low pin. Hence, the program memory is saved in the internal ROM of 8051 itself.

To access the data memory space, we use the instruction MOVX A, @DPTR. Connect the RD pin
(PIN 3.7) to the OE of data ROM and give an active low signal to the Chip enable (CE) pin of data
ROM. Here we access the data from the external ROM containing the data and transferred to
internal RAM.

Interfacing external program ROM, data ROM and external RAM

with the 8051
Next, let’s interface both program ROM and data RAM to 8051, Let’s say we want to interface
16KB data RAM, 16KB program ROM, and 16KB of data RAM, then we’ll have to follow the
following steps:

1. Step 1: Calculate the number of address lines required to access 16KB of data, that is 214 =
16KB. Here, we require 14 address lines A0 – A13.

2. Step 2: Decide the location of RAM and ROM, here we are going to interface program
ROM from 0000H and data RAM from 8000H.

3. Step 3: Select the decoder circuit, here we’re going to select 74LS138 decoder.

4. Step 4: We do not need a decoder circuit for program ROM, but we have to connect the
74LS138 decoder to data ROM and data RAM.

5. Step 5: Connect G1 to VCC, G2A, and G2B to ground.

6. Step 6: Connect input A and B to P2.6 and P2.7 respectively, and the input C to ground.

7. Step 7: We connect external program and data ROM, for that we can use an AND gate with
its input being signal from RD (to access external data space) and PSEN (to access external
program space) and output to OE of external ROM.

8. Step 8: To interface the external RAM, we connect both RD and WR to WE and OE respectively
of external RAM