DIGITAL

ELECTRONICS

NOTES
Counters
Types of Counters
Shift Register
Types of Shift Register

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 DIGITAL COUNTER
Counter is a sequential circuit. A digital circuit which is used for a counting pulses
is known counter. Counter is the widest application of flip-flops. It is a group of
flip-flops with a clock signal applied. Counters are of two types:

• Asynchronous or ripple counters.

• Synchronous counters.
Difference between Asynchronous and synchronous counter
Asynchronous counter Synchronous counter
1. In case of asynchronous counter, all the In case of synchronous counter, all the
flip-flops are not clocked simultaneously. flip-flops are clocked simultaneously.

2. In the case of asynchronous counter, the In case of synchronous counter , there is

output of first flip-flop drives the clock for no interconnection between output of one
second flip-flop, the output of second flip-flop and clock of next flip-flop,
drives the third and so on.

3. The settling time of asynchronous The settling time of synchronous counter

counter is cumulative sum of individual is equal to highest settling time of all flip-
flip-flops. flops.

4. Asynchronous counter is known as Synchronous counter is known as parallel

serial counter counter.
5.Its design and implementation is very Synchronous counter design and
simple. implementation becomes tedious and
complex as the number of states increases.

6. Asynchronous counter is slow in speed Synchronous counter is faster in speed as

as compare of synchronous counter. compare to asynchronous counter.

7. Asynchronous Counter examples Synchronous Counter examples are: Ring

are: Ripple UP counter, Ripple DOWN counter, Johnson counter.
counter.

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Synchronous Counter:

A counter which is using the same clock signal from the same source at the same
time is called Synchronous counter. Ring Counter is example of Synchronous
counter.

Asynchronous Counter:

Asynchronous counter where only the first flip-flop is clocked by an external

clock. All subsequent flip-flops are clocked by the output of the preceding flip-
flop. Ripple Counter is examples of asynchronous counter.

Figure A 2-bit asynchronous counter

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 ✓ Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T)
flip-flop are being used. But we can use the JK flip-flop also with J and K
connected permanently to logic 1. External clock is applied to the clock input of
flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-
B.

Logical Diagram

Operation

S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially

2 After 1st negative clock edge As soon as the first negative

clock edge is applied, FF-A will
toggle and QA will be equal to
1.
QA is connected to clock input
of FF-B. Since QA has changed
from 0 to 1, it is treated as the
positive clock edge by FF-B.
There is no change in
QB because FF-B is a negative
edge triggered FF.
QBQA = 01 after the first clock
pulse.

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3 After 2nd negative clock edge On the arrival of second
negative clock edge, FF-A
toggles again and QA = 0.
The change in QA acts as a
negative clock edge for FF-B.
So it will also toggle, and
QB will be 1.
QBQA = 10 after the second
clock pulse.
4 After 3rd negative clock edge On the arrival of 3rd negative
clock edge, FF-A toggles again
and QA become 1 from 0.
Since this is a positive going
change, FF-B does not respond
to it and remains inactive. So
QB does not change and
continues to be equal to 1.
QBQA = 11 after the third clock
pulse.
5 After 4th negative clock edge On the arrival of 4th negative
clock edge, FF-A toggles again
and QA becomes 1 from 0.
This negative change in QA acts
as clock pulse for FF-B. Hence
it toggles to change QB from 1
to 0.
QBQA = 00 after the fourth
clock pulse.434

Truth Table

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 ✓ Synchronous Counters

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously,
then such a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle
flip-flop. The JB and KB inputs are connected to QA.

Logical Diagram

Operation
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S.N. Condition Operation

1 Initially let both the FFs be in the reset state QBQA = 00 initially.

2 After 1st negative clock edge As soon as the first negative

clock edge is applied, FF-A
will toggle and QA will
change from 0 to 1.
But at the instant of
application of negative
clock edge, QA , JB = KB =
0. Hence FF-B will not
change its state. So QB will
remain 0.
QBQA = 01 after the first
clock pulse.
3 After 2nd negative clock edge On the arrival of second
negative clock edge, FF-A
toggles again and
QA changes from 1 to 0.
But at this instant QA was 1.
So JB = KB= 1 and FF-B
will toggle. Hence
QB changes from 0 to 1.
QBQA = 10 after the second
clock pulse.
4 After 3rd negative clock edge On application of the third
falling clock edge, FF-A
will toggle from 0 to 1 but
there is no change of state
for FF-B.
QBQA = 11 after the third
clock pulse.

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5 After 4th negative clock edge On application of the next
clock pulse, QA will change
from 1 to 0 as QB will also
change from 1 to 0.
QBQA = 00 after the fourth
clock pulse.

✓ Classification of Counters

Depending on the way in which the counting progresses, the synchronous or

asynchronous counters are classified as follows −

• Up counters
• Down counters
• Up/Down counters

UP/DOWN Counter

Up counter and down counter is combined together to obtain an UP/DOWN

counter. A mode control (M) input is also provided to select either up or down
mode. A combinational circuit is required to be designed and used between each
pair of flip-flop in order to achieve the up/down operation.

• Type of up/down counters

• UP/DOWN ripple counters
• UP/DOWN synchronous counter

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UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either
T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock
directly. But the clock to every other FF is obtained from (Q = Q bar) output of
the previous FF.

• UP counting mode (M=0) − The Q output of the preceding FF is connected

to the clock of the next stage if up counting is to be achieved. For this
mode, the mode select input M is at logic 0 (M=0).

• DOWN counting mode (M=1) − If M = 1, then the Q bar output of the

preceding FF is connected to the next FF. This will operate the counter in
the counting mode.

Example

3-bit binary up/down ripple counter.

• 3-bit − hence three FFs are required.

• UP/DOWN − So a mode control input is essential.

• For a ripple up counter, the Q output of preceding FF is connected to the

clock input of the next one.

• For a ripple up counter, the Q output of preceding FF is connected to the

clock input of the next one.

• For a ripple down counter, the Q bar output of preceding FF is connected to

the clock input of the next one.

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 • Let the selection of Q and Q bar output of the preceding FF be controlled by
the mode control input M such that, If M = 0, UP counting. So connect Q to
CLK. If M = 1, DOWN counting. So connect Q bar to CLK.

Block Diagram

Truth Table

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Operation

S.N. Condition Operation

1 Case 1 − With M = 0 (Up counting mode) If M = 0 and M bar = 1, then
the AND gates 1 and 3 in fig.
will be enabled whereas the
AND gates 2 and 4 will be
disabled.
Hence QA gets connected to the
clock input of FF-B and QB gets
connected to the clock input of
FF-C.
These connections are same as
those for the normal up counter.
Thus with M = 0 the circuit
work as an up counter.
2 Case 2: With M = 1 (Down counting If M = 1, then AND gates 2 and
mode) 4 in fig. are enabled whereas
the AND gates 1 and 3 are
disabled.
Hence QA bar gets connected to
the clock input of FF-B and
QB bar gets connected to the
clock input of FF-C.
These connections will produce
a down counter. Thus with M =
1 the circuit works as a down
counter.

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 ✓ Ring Counter

‘N’ bit Ring counter performs the similar operation as Shift Register (SIPO).
But, the only difference is that the output of rightmost D flip-flop is given as input
of leftmost D flip-flop instead of applying data from outside. Therefore, Ring
counter produces a sequence of states (pattern of zeros and ones) and it repeats for
every ‘N’ clock cycles.

The block diagram of 3-bit Ring counter is shown in the following figure.

The 3-bit Ring counter contains only a 3-bit SIPO shift register. The output of
rightmost D flip-flop is connected to serial input of left most D flip-flop.

We can understand the working of Ring counter from the following table.

No of positive edge of Serial Input = Q0 Q2(MSB) Q1 Q0(LSB)

Clock
0 - 0 0 1
1 1 1 0 0
2 0 0 1 0
3 0 0 0 1

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Therefore, the following operations take place for every positive edge of clock
signal.

• Serial input of first D flip-flop gets the previous output of third flip-flop. So,
the present output of first D flip-flop is equal to the previous output of third
flip-flop.

• The previous outputs of first and second D flip-flops are right shifted by one
bit. That means, the present outputs of second and third D flip-flops are
equal to the previous outputs of first and second D flip-flops.

✓ Johnson Ring Counter

The operation of Johnson Ring counter is similar to that of Ring counter. But,
the only difference is that the complemented output of rightmost D flip-flop is
given as input of leftmost D flip-flop instead of normal output. Therefore, ‘N’ bit
Johnson Ring counter produces a sequence of states (pattern of zeros and ones)
and it repeats for every ‘2N’ clock cycles.

Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring
counter. The block diagram of 3-bit Johnson Ring counter is shown in the
following figure.

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The 3-bit Johnson Ring counter also contains only a 3-bit SIPO shift register. The
complemented output of rightmost D flip-flop is connected to serial input of left
most D flip-flop.

We can understand the working of Johnson Ring counter from the following
table.

No of positive edge of Serial Input = Q0 Q2(MSB) Q1 Q0(LSB)

Clock
0 - 0 0 0
1 1 1 0 0
2 1 1 1 0
3 1 1 1 1
4 0 0 1 1
5 0 0 0 1
6 0 0 0 0

Therefore, the following operations take place for every positive edge of clock
signal.

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 • Serial input of first D flip-flop gets the previous complemented output of
third flip-flop. So, the present output of first D flip-flop is equal to the
previous complemented output of third flip-flop.

• The previous outputs of first and second D flip-flops are right shifted by one
bit. That means, the present outputs of second and third D flip-flops are
equal to the previous outputs of first and second D flip-flops.

✓ Modulus Counter (MOD-N Counter)

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is
called as MOD-8 counter. So in general, an n-bit ripple counter is called as
modulo-N counter. Where, MOD number = 2n.

Type of modulus

• 2-bit up or down (MOD-4)

• 3-bit up or down (MOD-8)
• 4-bit up or down (MOD-16)

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Mod 3 Counter Design and Circuit

A modulo 3 (MOD-3) counter can be made using three D-type flip-flops. We

simply look for the count of 3 which is 011 in binary. In this type of counter
application, this is the only time when those bits will be 1’s at the same time,
therefore we simply feed them into an AND gate to generate the RESET control
signal. When the counter reaches this number, the output from the AND gate will
initiate a reset on all the D-type flip-flops, and the count will begin again.

Application of Counters

• Frequency counters
• Digital clock
• Time measurement
• A to D converter
• Frequency divider circuits
• Digital triangular wave generator.

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 SHIFT REGISTER
Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, we have to use a group of
flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will
consist of n number of flip-flop and it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers.
There are four mode of operations of a shift register.

What is a Shift Register?

Shift Registers are sequential logic circuits, capable of storage and transfer of
data. They are made up of Flip Flops which are connected in such a way that the
output of one flip flop could serve as the input of the other flip-flop, depending on
the type of shift registers being created.

Types of Shift Registers

• Serial Input Serial Output

• Serial Input Parallel Output
• Parallel Input Serial Output
• Parallel Input Parallel Output

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 Fig: Types of Shift Registers

✓ Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If

an entry of a four bit binary number 1 1 1 1 is made into the register, this number
should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e.
D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the
input of the next flip-flop i.e. D2 and so on.

Block Diagram

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Operation

Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of
the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first
falling edge of clock, the FF-3 is set, and stored word in the register is
Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the
clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to D in. Apply the clock pulse. As soon as the
third negative clock edge hits, FF-1 will be set and output will be modified to
Q3 Q2 Q1 Q0 = 1110.

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Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored
word in the register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

Waveforms

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 ✓ Serial Input Parallel Output

• In such types of operations, the data is entered serially and taken out in
parallel fashion.

• Data is loaded bit by bit. The outputs are disabled as long as the data is
loading.

• As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.

• 4 clock cycles are required to load a four bit word. Hence the speed of
operation of SIPO mode is same as that of SISO mode.

Block Diagram

✓ Parallel Input Serial Output (PISO)

• Data bits are entered in parallel fashion.

• The circuit shown below is a four bit parallel input serial output register.

• Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.

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 • The binary input word B0, B1, B2, B3 is applied though the same
combinational circuit.

• There are two modes in which this circuit can work namely - shift mode or
load mode.

Load mode

When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active
they will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going
edge of clock, the binary input B0, B1, B2, B3 will get loaded into the
corresponding flip-flops. Thus parallel loading takes place.

Shift mode

When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive.
Hence the parallel loading of the data becomes impossible. But the AND gate 1,3
and 5 become active. Therefore the shifting of data from left to right bit by bit on
application of clock pulses. Thus the parallel in serial out operation takes place.

Block Diagram

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 ✓ Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0,
D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is
applied, the input binary bits will be loaded into the flip-flops simultaneously. The
loaded bits will appear simultaneously to the output side. Only clock pulse is
essential to load all the bits.

Block Diagram

✓ Bidirectional Shift Register

• If a binary number is shifted left by one position then it is equivalent to

multiplying the original number by 2. Similarly if a binary number is
shifted right by one position then it is equivalent to dividing the original
number by 2.

• Hence if we want to use the shift register to multiply and divide the given
binary number, then we should be able to move the data in either left or
right direction.

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 • Such a register is called bi-directional register. A four bit bi-directional shift
register is shown in fig.

• There are two serial inputs namely the serial right shift data input DR, and
the serial left shift data input DL along with a mode select input (M).

Block Diagram

Operation

S.N. Condition Operation

1 With M = 1 − Shift right operation If M = 1, then the AND
gates 1, 3, 5 and 7 are
enabled whereas the
remaining AND gates
2, 4, 6 and 8 will be
disabled. The data at
DR is shifted to right bit
by bit from FF-3 to FF-
0 on the application of
clock pulses. Thus with
M = 1 we get the serial
right shift operation.

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2 With M = 0 − Shift left operation When the mode control
M is connected to 0
then the AND gates 2,
4, 6 and 8 are enabled
while 1, 3, 5 and 7 are
disabled.
The data at DL is
shifted left bit by bit
from FF-0 to FF-3 on
the application of clock
pulses. Thus with M =
0 we get the serial right
shift operation.

✓ Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-
directional shift register. A shift register which can shift the data in both directions
is called a bi-directional shift register. Applying the same logic, a shift register
which can shift the data in both directions as well as load it parallely, is known as
a universal shift register. The shift register is capable of performing the following
operation −

• Parallel loading
• Left Shifting
• Right shifting

The mode control input is connected to logic 1 for parallel loading operation
whereas it is connected to 0 for serial shifting. With mode control pin connected

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to ground, the universal shift register acts as a bi-directional register. For serial
left operation, the input is applied to the serial input which goes to AND gate-1
shown in figure. Whereas for the shift right operation, the serial input is applied to
D input.

Block Diagram

Applications of Shift Registers:

• Shift register is used as Parallel to serial converter, which converts the

parallel data into serial data. It is utilized at the transmitter section after
Analog to Digital Converter (ADC) block.
• Shift register is used as Serial to parallel converter, which converts the
serial data into parallel data. It is utilized at the receiver section before
Digital to Analog Converter (DAC) block.
• Shift register along with some additional gate(s) generate the sequence of
zeros and ones. Hence, it is used as sequence generator.

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 • Shift registers are also used as counters. There are two types of counters
based on the type of output from right most D flip-flop is connected to the
serial input. Those are Ring counter and Johnson Ring counter.

✓ Difference Between Counter & Shift Register

SNO. COUNTER SHIFT REGISTER

1. Counter count the clock pulses. Shift register shifts the data left or right.
2. Type of counters are: Types of shift register are: Serial in
Asynchronous , Synchronous , Parallel out, Serial in Serial out ,Parallel
Decade ,MOD-N, Johnson , in Parallel Out , Parallel in Serial Out ,
Ring etc. Bidirectional , Universal etc.
3. It uses T-Flip-Flop J-K Flip-Flop Its uses D-Flip Flop.
4. These Are used in There Are used in Memories Like
Banks,Railway station etc. RAM,ROM etc.
5. A counter is a special case of a Shift registers are a type of sequential
register. Usually, it can only be logic circuit, mainly for storage of digital
loaded, stored, or incremented, or data. They are a group of flip-flops
used for the stack or as the connected in a chain so that the output
program counter. from one flip-flop becomes the input of
the next flip-flop.

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