Test Plan for I2C v
Test
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7
Test Plan for I2C verificati
Feature and directed test strategy
Basic testcase to check for clock and reset.
writing testcase for 128 bit address generation and 256 bit address generation
Writing test case for halfduplex operation
To set the start and stop bit.
To set the R/W bit for master read and write operation.
verifying transaction multiple scenario,
1.single master single slave communication
2.single master multiple slave communition
3.multiple mater single slave communication
4.multiple master multiple slave communication
To set ACK and NACK bit
verification
Feature and directed test strategy Verification Criteria
clock generatin for testbench environment and
to reset the device
logic for reset
constraint addr1{addr_i==[0:128];} constraint
addr2{addr_j==[0:256];} and also selcting devices based on the
creating coverpoints for functional coverage of address bits
address.
master constraint
transaction1{addr=100 ; data=0xaa} To verify single way
slave communation between the
monitor the devices
reception;
start:
assert property @(posedge scl) ($rose sda);
To verify the start and stop bit
stop :
of the device.
assert property @(posedge scl) ($fell
sda);
if(r/w==0)
master_write==1;
To verify writing operation of
if(r/w==1) mastter_write==0;
master.
Assert the condition
writing sequences according to transfer of data to verify multiple master slave
from master to slave communication.
if(scl==1 && sda == 0)
To verify the
ack==1;
acknow;edgement an no
if(scl==1 && sda==1) NACK==1;
acknowlwdgement condition
assert the condition
through assertions.
