SoC-ADV: Advanced topics for Embedded Systems with AMD adaptive SOC

SoC-ADV: Sistemas Embebidos en SOC adaptativos de AMD-Xilinx: SOC Avanzado

Language: The classes are in Spanish, but • Utilizing advanced Cortex-A9/A53

working material is in English (available also in processor services
English at In-Company). • Analyzing the DMA controller in the Zynq
and Zynq UltraScale+
Who Should Attend Hardware, software, • Examining the various library services for
firmware, and system design engineers who are peripherals such as Ethernet and USB
interested in fully using the Zynq extensible controllers
processing platform. • Develop a Simple Linux image using
PetaLinux tools
Duration: 24 h (3 days, 8 h/day).
The Advanced HW and SW of Embedded
Prerequisites: Embedded Systems Systems Design (SoC-ADV) course builds on
Development Course (SoC-ESS) or experience the skills gained in the Essential Embedded
with embedded systems design and the Vivado Systems Design with AMD Adaptive SoC FPGA
Design Suite, C or C++ programming. Working (SoC-ESS).
knowledge of the UltraScale+ MPSoC
processors (Cortex-A53), Zynq SoC (Cortex- Material: Each student will have a computer
A9), or MicroBlaze. Conceptual understanding
with the development tools (Vivado, Vitis and
of embedded processing systems, including
device drivers, interrupt routines, Xilinx Vitis-HLS 2022.2), documentation, repository
Standalone library services, user applications, whit exercises (and solutions) and a FPGA-SOC
and boot loader operation. development board for exercises that require it.

Introduction: Learn how to use advanced Skills Gained: After completing this
components of embedded systems design for comprehensive training, you will have the
architecting a complex system using for the necessary skills to:
Adaptive SoCs (System on a Chip) like Zynq
• Assemble an advanced embedded system
UltraScale+ MPSoC, Zynq 7000, Versal or
taking advantage of the various features of
MicroBlaze soft processor. Hands-on labs
the Zynq UltraScale+ MPSoC, Zynq SoC, and
provide experience with:
MicroBlaze, including the AXI interconnect,
• Developing, debugging, and simulating an and the various memory controllers.
embedded system • Apply advanced debugging techniques,
• Utilizing memory resources and including the use of the Vivado logic analyzer
implementing high-performance DMA tool for debugging an embedded system.
• Improving designs by using the Vivado IP • Integrate an interrupt controller and
Integrator and download designs to board. interrupt handler into an embedded design.
• Implementing an effective Zynq SoC / • Design a flash memory-based system and
MPSoC boot design methodology boot load from off-chip flash memory,
• Creating an FSBL image for flash • Implement an effective Zynq SoC / MPSoC
boot design methodology.

More information and schedule at (detalles y calendario en) http://www.electratraining.org

• Create an appropriate FSBL image for flash Streaming capabilities. Connecting different
• Identify advanced Cortex-A9/A53/A72/R5 types of AXI IP.
processor services for fully utilizing the • DMA operation of various IP that supports
capabilities of the Zynq devices. DMA and DMA-like functionality. DMA
• Analyze the operation and capabilities of the block design and the DMA interrupts.
DMA controller in the Zynq MPSoC Concepts behind reading and writing DMA.
• Describe the Standalone library services • PS-PL Interface in Zynq and Zynq MPSoC
available for low-speed peripherals, Ethernet Device discussing the various connection
and USB controllers that are contained in the points between the PS and PL.
Zynq MPSoC / SoC PS • PS Peripherals: Introduction to High-Speed
(USB and Gigabit Ethernet) and Low-Speed
• Create a PetaLinux project to configure and
(CAN, I2C, SD/SDIO, SPI and UART).
build a Linux Image. Understand what is an
embedded Linux kernel, a device tree and • QEMU: Introduction to the Quick Emulator,
the device driver architecture. Access to PL which allow to run software for the Zynq
core using user space I/O (UIO) framework. device when hardware is not available.
• Booting. Overview of booting Zynq devices
Topics Covered: This course covers the and MicroBlaze processors. Boot Memory
following topics and concepts: Technologies. Low-level view of the booting
process. PS Processors, the concepts behind
• Reminder of Embedded HW and SW
a single-core boot, a multi-core boot, and
development Flow with Vitis, including how
symmetric or asymmetric processing.
the compiler and linker behave, basics of
Configuring the PL at boot. Secure Boot.
makefiles, DMA usage, and variable scope.
Introduction to the FSBL (First Stage Boot
• More details in Zynq UltraScale+, MPSoC Loader). Flash Image Generator tool.
Zynq-7000 and Versal architecture.
• Sharing PS Resources (Hardware
• Debugging: Hardware Introduction for in- Perspective). How a master in the PL can
chip testing of hardware designs. Marking leverage resources within the PS.
Nets (to monitor nets without having to
• Processor Caching, SCLR (System-Level
explicitly instantiate ILA cores). Hardware-
Control Register) and NEON Co-
Software Co-Debugging (Cross-Triggering),
Processing.
describes how to enable events in hardware
to pause the software and breakpoints in • Accelerator Coherency Port (ACP). Purpose
software to cause an ILA trigger. and general behavior
• Memory Types and operation: Overview of • Linux. Embedded Linux Overview and the
the different types of memory available. PetaLinux Tools. Device Drivers, User Space
Block RAM Controllers. Static Memory I/O, and Loadable Kernel Modules. Accessing
Controllers. Introduction to DDRx Memory Hardware Devices from User Space
Operation. Dynamic Memory Controller (PS • Multi-Processor Hardware Architecture.
of Zynq-7000 / MPSoC / Versal Devices) key Support for cross-processor communica-
behaviors. tions. Introduction to OpenAMP and Xen
• Interrupts. In deep concept of interrupts, Hypervisor
terminology, and implementation. Interrupts
in Zynq devices from both a hardware and Related Courses:
software perspective. General Interrupt SoC-ESS: Essential HW and SW of Embedded
Controller (GIC), its features, and some
Systems Design
examples of its use.
• AXI advanced concepts. AXI Streaming HLS01: High Level Synthesis for Xilinx FPGAs
background and configuration. AXI using Vitis-HLS

More information and schedule at (detalles y calendario en) http://www.electratraining.org

SoC-RF: Designing with the Zynq UltraScale+ Visit www.electratraining.org
RFSoC
Price & Course Packs and Discounts:
VIV-ESS: Designing FPGAs Using the Vivado
design Suite Essential • SoC-ADV: 1240€
• SoC-ESS: 1230€
VIV-ADV: Designing FPGAs Using the Vivado
• SoC-ESS + SoC-ADV: (-20%): 1980€
design Suite Advanced
For more than one engineer from same
Dates, location and registration: company / institution additional discounts.

More information and schedule at (detalles y calendario en) http://www.electratraining.org