Experiment No:3 310 8 DECODER -74138 AIM: To write a VHDL program for 3 to 8 Decoder and simulate it by using XILINX9.2i Soft ware, SOFTWARE: 1. ILINX 9.2i 2.1SE Simulator PROGRAM: library IEEE; use IEEESTD_LOGIC_1164.4LL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity del is Port (en: in STD_LOGIC; x: in STD_LOGIC_VECTOR (2 downto 0); y+ out STD_LOGIC_VECTOR (7 downto 0)}; end del; architecture Behavioral of del is begin process(en,x) begin if en='0' then y<="00000000"; else case xis, end case; end if; end process; end Behavioral;RTL SCHEMATIC DIAGRAM:OUTPUT WAVEFORMS (AFTER SIMULATION): TRUTH TABLE: en | x2 [ x1 [ xo [ v7 [ Yo [ Ws [ va [ v3 [ v2 [ ¥I [ vo 0 x x x 0 0 0 0 o 0 0 0 1 0 0 0 0 0 0 ° o 0 0 1 1 0 0 c 0 0 0 ° 0 0 T 0 T 0 T 0 0 0 0 ° 0 T 0 0 1 0 T 1 0 0 0 ° T 0 0 0 1 1 0 0 0 0 0 1 0 0 o 0 1 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 Start the Xilinx IS oftware by Double clicking on the Icon or Start + All Progeams + Xilinx ISE 9.2i —+ Project Navigator 2.Create a new project by Selecting File > New Project. 3. Create a VHDL source file, then, continue either to the “Creating a VHDL Souree” section below.4. The next step in creating the new source is to add the behavioral description for the pro 5. Place the cursor just below the begin statement within the program architecture. 6, Save the file by sele ing File + Save. 7.When the source files are complete, check the syntax of the design to find errors and types. 8, Verify the Functionality using Behavioral Simulation. 9.0 A test bench waveform containing input stimulus you can use to verify the functionality of the program module, 10, Save the waveform, RES LT: The VHDL program for 3 to 8 Decoder is written and simulated by using XLINX9.2i version and the Output is verified,8 to 3 Encoder (with and without priority) ABSTRACT: To study and simulate design of 8 to 3 Encoder (with and without priority) using VHDL. THEORY: 8 to 3 encoder has 8 inputs and only one output based on the select inputs ( stress out one output n. Priority encoders are available in standard IC form and the TTL 7ALS148 is an 8-t0-3 bit priority encoder which has eight active LOW (logic “O") inputs and provides a 3-bit code of the highest ranked input at its output. PROCEDURE: a The 8 to 3 encoder Design is entered through VDL. a The design is simulated by applying test vectors- ENABLE_L, D_IN and observing output D-OUT, a Afier simulation obtain the RTL, technology schematics and synthesis report. a Itis required to lock the pins and give timing constraints. a Implement the design by passing the design by various stages by mapping, time analysis and bit stream, For locking the pins write UCF file before implementation and guide the same through option set control files. Output can be directly programmed into target device FPGA. VHDL PROGRAM FOR 8 TO 3 ENCODER (with out priority): LIBRARY IE USE IEEE.STD_LOGIC_1164.ALL; USE IEEE,STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ENCODERS8_3 IS PORT (ENABLE _L : IN STD_LOGIC; D_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0); D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END ENCODERS _ ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS BEGIN PROCESS(ENABLE_L,D_IN) BEGINIF (ENABLE_L = 'l') THEN D_OUT < ‘ ELSE CASE D_IN IS WHEN "00000001" => D_OUT <= "000"; WHEN "00000010" => D_OUT <= "001"; WHEN "00000100" => D_OUT <= "010"; WHEN "00001000" => D_OUT <= "O11"; WHEN "00010000" => D_OUT <= "100"; WHEN "00100000" => D_OUT <= "101"; WHEN "01000000" => D_OUT <= "110"; WHEN “10000000” => D_OUT <= "111"; WHEN OTHERS => NULI END CASE; END IF; END PROCE LOGIC DIAGRAM:ERNAL DIAGRAM: VHDL PROGRAM FOR 8 TO 3 ENCODER (with out priority); Library IEEE; Use IEEE. std_logic_1164.all; Entity V74x 148 is Port ( ELL: in std_logic; LLL: in std_logic_vector(7 downto 0); A_L: out std_logic_vector(2 downto 0); EO_L,GS. L: out std_logie); End V74x148; Architecture behavioral of V74x148 id Signal El; std_logic; Signal I: std_logic_vector(7 downto 0);Signal EO,GS: std_logic; Signal A: std_logic_vector(2 downto 0); Begi process(EL_L,_L,BI,E0,GS,L,A) variable j jeger range 7 downto 0: begin Ele= not BLL; Tes not LL; BO<="'1'; Gs<="0"; A<="000"; If(ED="0" then EO<="0"; Else for j in 7 downto 0 loop I 1G)" then GS<="1"; EO<="0"; A<=conv_std_logic_vector(j,3) Exit‘TRUTH TABLE: ELL] 100 [a 15_L [161] 17 | A2L] ALL] AOL] GS_L] EOL rf x {x x|x{[xfi 1 1 1 1 0; xi[x x/xfo;fofofo|so 1 o;xi[xX xfof?tfofo H 0 H oy; xi]xX oyiryiy]o T o | 0 1 oO; xi]x ry if a] o 1 1 0 1 0; xi[xX ryt fd 1 oy; oy] °o 1 0; x {xo ry af H 0 1 0 H o;xiforfi a H 7 a) H o;ofiryi ryt fd 1 1 1 0 1 | ry tfd 1 1 1 1 0 End ify End loop; End if; EO_L<= not EO; GS_L<= not G! A Les not A; End process; End behavioral; RESULT: