Training Report

On
Schematic and Layout Design of VLSI
Circuits
Submitted by

ANUJ RAGHAV
2100320310018

Department of Electronics and Communication

Engineering
ABES ENGINEERING COLLEGE,
GHAZIABAD, UTTAR PRADESH
 Table of Contents

1. Introduction to VLSI
2. VLSI Physical Design Flow and its importance and challenges
3. Importance of CAD in VLSI
4. DC Circuit
5. Diode
5.1. Basic Diode Circuit
5.2. Half Wave Rectifier
5.3. Full Wave Rectifier
6. Basic Circuits
6.1. Clipper
6.2. Clamper
7. MOSFET Fundamentals
7.1. Drain and Transfer Characteristics of NMOS
7.2. Drain and Transfer Characteristics of PMOS
8. Vsb Effect
9. Designing of Digital Circuits at lower technology
9.1. NOT gate and its analysis using NMOS
9.2. NOT gate and its analysis using CMOS
9.3. NAND gate and its analysis using CMOS
9.4. NOR gate and its analysis using CMOS
10. CS Amplifier
10.1. Design CS Amplifier and find critical frequency and bandwidth
10.2. Design CS Amplifier with load resistance 10k ohm and find critical
frequency and bandwidth
11. OP-AMP
11.1. Inverting OP-AMP (Gain 1E6 and Gain 1)
11.2. Non-Inverting OP-AMP (Gain 1E6 and Gain 1)
11.3. OP-AMP as Inverting Comparator
 11.4. OP-AMP as Non Inverting Comparator
12. Project
12.1. Introduction
12.2. Circuit
12.3. Software Implementation
12.3. Result
12.5. Conclusion
12.6. Reference
 1. INTRODUCTION TO VLSI
Integrated circuits are tiny electronic circuit used to perform a specific function, such as
amplification. The first integrated circuit was invented by Jack Kilby in 1958.As suggested
by Moore, the capacity doubled roughly every 18 months. Today, a large single VLSI chip
can contain over one billion transistors. These days, VLSI chiefly comprises of Frontend
and Backend design. Frontend design using HDL and design verification through
simulation and other techniques. The Backend design comprises of CMOS library design
and its characterization. It also covers the physical design and fault simulation.

2. VLSI PHYSICAL DESIGN FLOW AND ITS

IMPORTANCE AND CHALLENGES
A simplified view of VLSI design flow is given below. It is taking into account the various
representations, or abstractions of design behavioural, logic, circuit and mask layout. Note
that the verification of design plays a very important role in every step during this process.

The failure to properly verify a design in its early phases typically causes significant and
expensive re-design at a later stage, which ultimately increases the time-to-market.
Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighbouring steps,
and occasionally even remotely separated pairs.
3. CHALLENGES TO VLSI TECHNOLOGY
Shrinking geometries, lower power voltages, and higher frequencies of integrated circuits
have a negative impact on reliability. All these factors increase the number of occurences of
intermittent and transient faults. The approach of fault avoidance and fault tolerance is used
to increase the reliability of VLSI circuits. As technology scales, many new opportunities
emerge for VLSI designers. There are several difficult and exciting challenges facing the
design of complex integrated circuits. To continue its phenomenal historical growth and
continue to follow Moore’s law, the semiconductor industry will require advances on all
fronts.
4. DC CIRCUIT
 CIRCUIT

ANUJ RAGHAV 2100320310018 DC CIRCUIT

 NETLIST

 ANALYSIS
5. DIODE
5.1. Basic Diode Circuit
 CIRCUIT

ANUJ RAGHAV 2100320310018 DIODE

 NETLIST

 ANALYSIS
5.2. HALFWAVE RECTIFIER
A half wave rectifier is a type of rectifier which converts the positive half cycle (positive
current) of the input signal into pulsating DC (Direct Current) output signal.
 CIRCUIT

ANUJ RAGHAV 2100320310018 HALF WAVE RECTIFIER

 NETLIST

 ANALYSIS
5.3. FULLWAVE RECTIFIER
A bridge rectifier is a type of full wave rectifier which uses four or more diodes in a bridge
circuit configuration to efficiently convert the Alternating Current (AC) into Direct Current
(DC).
 CIRCUIT
ANUJ RAGHAV 2100320310018 FULLWAVE RECTIFIER

 NETLIST
 ANALYSIS
6. BASIC CIRCUITS
6.1. CLIPPER
Clipper circuits are the electronic circuits that clip off or remove a portion of an AC signal,
without causing any distortion to the remaining part of the waveform. These are also
known as clippers, clipping circuits, limiters, slicers, etc. The clipping (removal) of the
input AC signal is done in such a way that the remaining part of the input AC signal will
not be distorted.
 CIRCUIT

ANUJ RAGHAV 2100320310018 CLIPPER

 NETLIST
  ANALYSIS

6.2. CLAMPER
A clamper is an electronic circuit that changes the DC level of a signal to the desired level
without changing the shape of the applied signal. The construction of the clamper circuit is
almost similar to the clipper circuit. The only difference is the clamper circuit contains an
extra element called capacitor. A capacitor is used to provide a dc offset (dc level) from the
stored charge.
 CIRCUIT

ANUJ RAGHAV 2100320310018 CLAMPER

 NETLIST

 ANALYSIS
7. MOSFET FUNDAMENTALS
A metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET)
is a field-effect transistor (FET with an insulated gate) where the voltage determines the
conductivity of the device.
 Why MOS?
MOSFETs are particularly useful in amplifiers due to their input impedance being
nearly infinite which allows the amplifier to capture almost all the incoming signal.
The main advantage is that it requires almost no input current to control the load
current, when compared with bipolar transistors. The various types of MOSFET are
given below:
 Depletion Type: The transistor requires the Gate-Source voltage (VGS) to switch
the device “OFF”. The depletion-mode MOSFET is equivalent to a “Normally
Closed” switch.
 Enhancement Type: The transistor requires a Gate-Source voltage(VGS) to switch
the device “ON”. The enhancement-mode MOSFET is equivalent to a “Normally
Open” switch.

N-Channel MOSFET
7.1. DRAIN AND TRANSFER CHARACTERISTIC OF NMOS
 CIRCUIT

ANUJ RAGHAV 2100320310018 NMOS

 DRAIN CHARACTERISTIC ANALYSIS

 DRAIN NETLIST

 TRANSFER CHARACTERISTIC ANALYSIS

  TRANSFER NETLIST

7.2. DRAIN AND TRANSFER CHARACTERISTIC OF PMOS

 CIRCUIT

ANUJ RAGHAV 2100320310018 PMOS

 DRAIN CHARACTERISTIC ANALYSIS

 DRAIN NETLIST
 TRANSFER CHARACTERISTIC ANALYSIS

 TRANSFER NETLIST
8. Vsb EFFECT
Body effect refers to the change in the transistor threshold voltage (VT) resulting from a
voltage difference between the transistor source and body. Because the voltage
difference between the source and body affects the VT, the body can be thought of as a
second gate that helps determine how the transistor turns on and off.
8.1. Vsb EFFECT ON NMOS
 CIRCUIT
ANUJ RAGHAV 2100320310018 VSB
EFFECT

 NETLIST
  ANALYSIS

8.2. Vsb EFFECT ON PMOS

 CIRCUIT
ANUJ RAGHAV 2100320310018 PMOS VSB EFFECT
 NETLIST

 ANALYSIS
9. Designing of Digital Circuits at lower technology
A digital circuit is just a collection of gates and flip flops that are connected together. So,
the essence of the design process is to specify exactly what gates and flip flops should be
used and how they should be connected in order to produce a circuit that behaves in a
desired way. As the complexity of digital systems has increased, computer-aided design
tools were developed to reduce the amount of manual effort required to specify circuits and
verify that they worked correctly.

9.1. NOT gate and its analysis using NMOS

A NOT gate is a logic gate that inverts the digital input signal. A NOT gate always has
high (logical 1) output when its input is low (logical 0). Conversely, a logical NOT gate
always has low (logical 0) output when the input is high (logical 1).
 CIRCUIT

ANUJ RAGHAV 2100320310018

INVERTER

 NETLIST
  ANALYSIS

9.2. NOT gate and its analysis using CMOS

 CIRCUIT

ANUJ RAGHAV 2100320310018 CMOS

INVERTER
 NETLIST

 ANALYSIS
9.3. NAND gate and its analysis using CMOS
A NAND gate (NOT-AND) is a logic gate which produces an output which is false only if
all its inputs are true; thus its output is complement to that of an AND gate. A LOW (0)
output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a
HIGH
(1) output results. The truth table is given below:

 CIRCUIT
ANUJ RAGHAV 2100320310018 CMOS
NAND
 NETLIST

 ANALYSIS
 9.4. NOR gate and its analysis using CMOS
A NOR gate (NOT-OR) is a logic gate which produces an output which is true only if all
its inputs are false ; thus its output is complement to that of an OR gate. A HIGH (1) output
results only if all the inputs to the gate are LOW (0); if any input is HIGH (1), a LOW(0)
output results. The truth table is given below:
INPUT OUTPUT
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

 CIRCUIT

ANUJ RAGHAV 2100320310018 NOR GATE (CMOS)

 NETLIST

 ANALYSIS
10. CS Amplifier
When the input signal is applied at the gate terminal and source terminal, then the output
voltage is amplified and obtained across the resistor at the load in the drain terminal. This is
called a common source amplifier.
The Common-source (CS) configuration is the most widely used of all MOSFET amplifier
circuits. Observe that to establish a signal ground we have connected a large capacitor,
CS, between the source and ground. This capacitor, usually in uF range, is required to
provide very small impedance at signal frequencies of interest. In this way, the signal
current passes through CS to ground and thus bypasses the resistance RS, Hence CS is
called bypass capacitor.
10.1. Design CS Amplifier and find critical frequency and bandwidth
 CIRCUIT

ANUJ RAGHAV
2100320310018 CMOS
AMPLIFIER
 NETLIST

 ANALYSIS
10.2. Design CS Amplifier with load resistance 10k ohm and find critical
frequency and bandwidth
 CIRCUIT

ANUJ RAGHAV 2100320310018

CS AMPLIFIER LOAD 10K

 NETLIST
 ANALYSIS
11. OP-AMP
11.1. Inverting OP-AMP (Gain 1E6 and Gain 1)
In the inverting operational amplifier circuit, the signal is applied at the inverting input and
the non-inverting input is connected to the ground. In this type of amplifier, the output is
180⁰ out of phase to the input, i.e. when positive signal is applied to circuit, the output of
the circuit will be negative.
 CIRCUIT
ANUJ RAGHAV 2100320310018 OP AMP INVERTING

 NETLIST (GAIN 1E6)

 ANALYSIS (GAIN 1E6)

  NETLIST (GAIN 1)

 ANALYSIS (GAIN 1)

11.2. Non-Inverting OP-AMP (Gain 1E6 and Gain 1)

When the signal is applied at the non-inverting input, the resulting circuit is known as Non-
Inverting Op-Amp. In this amplifier the output is exactly in phase with the input i.e. when a
positive voltage is applied to the circuit, the output will also be positive.

 CIRCUIT

ANUJ RAGHAV 2100320310018 OP AMP NON

INVERTING
 NETLIST (GAIN 1E6)

 ANALYSIS (GAIN 1E6)

 NETLIST (GAIN 1)
  ANALYSIS (GAIN 1)

11.3. OP-AMP as Inverting Comparator

An inverting comparator is an op-amp based comparator for which a reference voltage is
applied to its non-inverting terminal and the input voltage is applied to its inverting
terminal. This comparator is called as inverting comparator because the input voltage,
which has to be compared is applied to the inverting terminal of op-amp.
 CIRCUIT
ANUJ RAGHAV 2100320310018 INVERTING COMPARATOR
  NETLIST

 ANALYSIS

11.4. OP-AMP as Non Inverting Comparator

A non-inverting comparator is an op-amp based comparator for which a reference voltage
is applied to its inverting terminal and the input voltage is applied to its non-inverting
terminal. This op-amp based comparator is called as non-inverting comparator because the
input voltage, which has to be compared is applied to the non-inverting terminal of the op-
amp.
 CIRCUIT
 NETLIST

 ANALYSIS
12. Project

12.1. Introduction
Vedic mathematics is the term given to the ancient Indian system of mathematics based on
the holy scriptures called Vedas also called the source of knowledge. It is a unique
technique of calculations based on simple rules and principles with which any mathematical
problem can be solved be it arithmetic, algebra, calculus, geometry. It is designed the way
our mind naturally works and thus makes it the fastest way to calculate easily. It is believed
to be created around 1500 BC and was rediscovered between 1911 and 1918 by Sri Bharti
Krishna Tirthaji. He was a scholar of Sanskrit, mathematics, science, history and
philosophy. He studied these texts during his meditation and classified Vedic mathematics
into 16 sutras. “The sutras of Vedic Mathematics are the software for the cosmic computer
that runs this universe.” Due to coherence and symmetry in these algorithms it can have a
regular silicon layout and consume less area along with lower power consumption.
Research is being carried out on how to develop more powerful and easy applications of the
Vedic sutras. There is a need for faster processing speed which is continuously driving
major improvements in processing technologies.
This project aims on the use of these Vedic Sutras to create a 4-bit multiplier which has a
fast-processing speed and is far more superior than existing multipliers.
It is a completely software-based project which uses OrCAD Capture and PSPICE to
simulate and achieve the results.

12.2. Circuit
All n-bit multipliers can be easily made from n/2-bit multipliers. The basic building block
for all multipliers is a 2-bit multiplier.
A 4-bit multiplier can be made using 2-bit multipliers easily with CLA adders.
12.3. Software Implementation
(a) 2-bit Multiplier

It uses 4 digital clocks for 2 inputs- A1A0 and B1B0 and the result is R3R2R1R0.
(b) 4-bit Multiplier
It uses 8 digital clocks for 2 inputs- A3A2A1A0 and B3B2B1B0 and the result is
R7R6R5R4R3R2R1R0.
12.3. Result
After completing our design and implementing it we can easily observe the result. It
completely matches with the truth table of a 4-bit multiplier.
Here we can see
S.No. A B Output
1. 0011 0011 00001001
2. 0100 0100 00010000
3. 0101 0101 00011001

12.5. Conclusion
A 4 bit Vedic multiplier was designed using CLA adders which is highly efficient in terms
of the speed. It is used to limit the raise propagation time and to optimize the hardware
complexity degree for operation. One of the main advantages is that delay increases slowly
as the input bits increases. A lot of mathematical DSP algorithm such as Fourier
transforms, fast Fourier transforms, digital filters etc. require fast multiplication to be
efficient. Hence, this multiplier can be used to implement DSP algorithms.

12.6. Reference
[1] R.K. Bathija, R.S. Meena, S. Sarkar and Rajesh Sahu TINJRIT. “Low Power
High Speed 16x16 bit Multiplier using Vedic Mathematics”. International Journal
of Computer Applications (0975 – 8887) Volume 59– No.6, December 2012
[2] S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A.
“Implementation of Vedic Multiplier for Digital Signal Processing”.
[3] Harpreet Singh Dhillon and Abhijit Mitra. “A Digital Multiplier Architecture
using
Urdhva Tiryakbhyam Sutra of Vedic Mathematics”
[4] Yogita Bansal, Charu Madhu and Pardeep Kaur. “High Speed Vedic Multiplier
Designs".
[5] Vaishali Sharma , R. P. Agarwal. “Design, Implementation & Performance of
Vedic
Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths”
[6] Weste-Nhe & Harris-D CMOS Vlsi Design " A circuit & System Perspective
[7] W.Wolf Modern VLSI Design: System on Chip
[8] P. Gray, R. Meyer Analysis and Design of Analog Integrated Circuits
[9] Sung-Mo Kang & Yosuf Leblebic
CMOS Digital Integrated Circuits: Analysis & Design