CSSE2010 / CSSE7201 Device Pinouts and Symbols

Power and Ground

Device ID Logic Diagram Circuit Schematic
Device Pinout
& Function Symbol Symbol(s)
Logic High VCC
1
/ Power

Logic Low
0
/ Ground or
Power and ground connections for devices are shown separately. These symbols are used, for example, when
connecting a device input to logic low or logic high

Basic Gates
74HCT00 U1:A U1:C
74HCT00
Quad 1
74HCT00
3
9
8
2-input 2 10

NAND gate U1:B U1:D

74HCT00 74HCT00
4 12
6 11
5 13

74HCT04 U1:A U1:C U1:E

Hex 74HCT04 74HCT04 74HCT04
1 2 5 6 11 10
Inverter
U1:B U1:D U1:F
74HCT04 74HCT04 74HCT04
3 4 9 8 13 12

74HCT08 U1:A U1:C

74HCT08 74HCT08
Quad 1
3
9
8
2-input 2 10

AND gate U1:B U1:D

74HCT08 74HCT08
4 12
6 11
5 13

74HCT32 U1:A U1:C

74HCT32 74HCT32
Quad 1
3
9
8
2-input 2 10

OR gate U1:B U1:D

74HCT32 74HCT32
4 12
6 11
5 13

74HCT86 U1:A U1:C

74HCT86 74HCT86
Quad 1
3
9
8
2-input 2 10

XOR gate U1:B U1:D

74HCT86 74HCT86
4 12
6 11
5 13

Flip-Flops and MSI Devices

74HCT74 VCC
14
CLR2
13
D2
12
CLK2
11
SET2
10
Q2
9
Q2
8
Dual D-type D
SET
Q
D
SET
Q
U1:A
74HCT74
4 U1:B
74HCT74
10

Flip-flop CLR Q
2
D
SET
Q
5 12
D
SET
Q
9

D
SET
Q
CLR Q 3 11

6 8
Q CLR Q CLR Q
(Set and clear inputs can be
CLR

1 13
1 2 3 4 5 6 7 omitted if not needed)
CLR1 D1 CLK1 SET1 Q1 Q1 GND
Device ID Logic Diagram Circuit Schematic
Device Pinout
& Function Symbol Symbol(s)
74HCT157 (Several options possible)
Quad 2- A0 U1
74HCT157
input A1 2
A0

Multiplexer
A2
5
Y0 A1
A3
VCC ENABLE A3 B3 Y3 A2 B2 Y2 Y1 11
A2 4
16 15 14 13 12 11 10 9 B0 Y2 Y0
14
B1 Y3 4 A3 7
A A A Y1
B
Y
L B
Y
L B2 4
SE SE
Y 3 9
4 B0 Y2
B3
B
A A
L
Y Y
SE L 6 12
SE B1 Y3
B L B L
SE SE

10
1 2 3 4 5 6 7 8 B2
13
LE
SELECT A0 B0 Y0 A1 B1 Y1 GND
B3
A A A A AB
EN
L
SE
Y Y Y Y
B L B L B L B L
SE SE SE SE 1 15

(Add enable input if needed)

74HCT175 4
D
SET
Q 4 U1
74HCT175
Quad D- VCC Q3 Q3 D3 D2 Q2 Q2 CLK 4 D0 Q0
2
16 15 14 13 12 11 10 9 5 7
Type Flip- 12
D1 Q1
10
D
SET
D
SET

CLR Q 4
D2 Q2
flop
Q Q

13 15
CLR Q CLR Q D3 Q3

D
SET
Q D
SET
Q 3
Q0
CLR Q CLR Q
or Q1
6
D
SET
Q D
SET
Q D
SET
Q D
SET
Q 9 11
1 2 3 4 5 6 7 8 Q2
14
CLR Q0 Q0 D0 D1 Q1 Q1 GND Q3
CLR Q CLR Q CLR Q CLR Q
CLR
1

74HCT283 7 U1
4 bit full VCC
16
B2
15
A2
14
S2
13
A3
12
B3
11
S3
10
C4
9
A0
A1
C0 5
3
A0
A1
C0
74HCT283

A2 14
adder Full Full
A3 12
A2
A3
C3 C4
S0 4

+
Adder Adder

+
S0
S1 1
S1
S2 13
S2
S3 4 10
C2 Full C1 Full C0 A C0 S3
Adder Adder B0 6
4
1 2 3 4 5 6 7 8
B1
B2
+S 2
15
B0
B1
C4 4 B2
B3 B C4 11 C4
S1 B1 A1 S0 A0 B0 C0 GND B3
9
or

Inputs and Outputs

IO Board
IO1 IO1
IOBOARD IOBOARD
12 25
B3 A
13 26
B2 B
14 27
B1 C
15 28
B0 D
29
E
30
F
A 31
Input: G
32
H
X0
Output: IO1 IO1 IO1
IOBOARD IOBOARD IOBOARD
17
1: TX B3
12
A
25 X0
2: RX (Use sensible names)
13 26 18
X1
B2 B
19
3: SSD Cathode B1
14
C
27 X2
4: SSD Decimal Point B0
15
D
28 20
X3
5-11: SSD Segments G to A 29
21
X4
E
12-15: Buttons B3 to B0 30 22
X5
16: Logic Probe F
31 23
COUT
17-24: LEDs L0 to L7 G
24
32 OFLOW
25-32: Switches S0 to S7 H