University of Southern Mindanao

Kabacan, North Cotabato

College of Engineering and Information Technology
Department of Electronics Engineering

Plate Number 3: 4-bit Binary Using Dipswitch to 7

Segment
EcE 08: LOGIC CIRCUITS AND SWITCHING THEORY

Submitted by:
Nicholas Jude Andrei H. Arnado
Christian Lloyd F. Carillo
Chrismary Vien T. Pujol
Lawrence H. Salvador

Submitted to:
Engr. Marc Macbeth M. Toledo, MSEE
Instructor

December 2024
Introduction
The activity is about creating a 4-bit binary to 7-segment display hexadecimal
converter. This demonstrates how binary numbers, made up of 4 bits, are converted into
hexadecimal values (0 to F) and displayed using a 7-segment display. A 7-segment display
is a common electronic component used to show numbers or simple characters, often seen
in devices like calculators and digital clocks.
By carefully designing the logic, the circuit determines which segments should light up
to correctly represent the hexadecimal value based on the binary input. The design
highlights the relationship between binary numbers, hexadecimal values, and how digital
displays work. It utilizes basic logic gates (AND, OR, NOT) and applies Boolean algebra,
truth table analysis Karnaugh mapping (K-mapping) to derive the logic functions that drive
the individual segments of a common-cathode (CC) seven-segment display. Also, the
process involves understanding how to control each segment of the display and using
logical connections to ensure the output matches the expected value.

Objective:
To design and implement a 4-bit binary to 7-segment display decoder capable of
displaying both decimal (0-9) and hexadecimal (A-F) values. This involves creating a truth
table and using Karnaugh mapping (K-mapping) to simplify the logic expressions for each
segment of the display to ensure efficient and accurate operation. The project also aims to
provide practical experience in assembling digital circuits using basic logic gates such as
AND, OR, and NOT, which are implemented through integrated circuits (ICs) like the
7404, 7408, and 7432. Additionally, the circuit is tested to validate its functionality and
accuracy across all 16 possible 4-bit binary input combinations to practice our
understanding of digital logic design, circuit optimization, and troubleshooting.

Materials
1. Breadboard
2. Jumper Wires
3. Logic Gate IC:
o NOT Gate: 7404 IC (Hex Inverter) – 2 pcs
o AND Gate: 7408 IC (Quad 2-input AND Gate) – 9 pcs
o OR Gate: 7432 IC (Quad 2-input OR Gate) – 5 pcs
4. Power Supply:
o 5V DC power supply or 9V battery with a voltage regulator (7805)
5. Resistors:
o 10kΩ resistor – 4 pcs (pull-down resistors for DIP switch)
 o 330Ω resistor – 1pc (current limiting for 7-segment display)
6. 4-bit DIP switch (to represent input)
7. 7-segment Common Cathode Display

Overview

1. Binary to 7-Segment Display for Hexadecimal Representation

A seven-segment display is an electronic display device that shows decimal or hexadecimal

characters by lighting up specific segments (a to g). In hexadecimal mode, the display must
show digits 0-9 and letters A-F for binary inputs ranging from 0000 (0) to 1111 (F).

Hexadecimal Digit Binary Input (D3, D2, D1, D0) Segments Lit (a-g)
0 0000 a, b, c, d, e, f
1 0001 b, c
2 0010 a, b, g, e, d
3 0011 a, b, g, c, d
4 0100 f, g, b, c
5 0101 a, f, g, c, d
6 0110 a, f, g, e, c, d
7 0111 a, b, c
8 1000 a, b, c, d, e, f, g
9 1001 a, b, c, d, f, g
A 1010 a, b, c, e, f, g
B 1011 f, e, g, c, d
C 1100 a, f, e, d
D 1101 b, c, g, e, d
E 1110 a, f, g, e, d
F 1111 a, f, g, e

2. Karnaugh Mapping (K-Map) and Minterm Simplification

The conversion of a 4-bit binary input (D3, D2, D1, D0) to a hexadecimal output on a 7-
segment display requires seven Boolean equations which means one for each segment (a,
b, c, d, e, f, g). Each equation determines when a segment should be turned on based on the
binary input. To simplify the equations, we use Karnaugh Maps (K-maps), which help
reduce the number of logic gates needed, making the circuit more efficient.

Hexadecim Inputs 7 Segment Output

al D C B A a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
 A 1 0 1 0 1 1 1 0 1 1 1
B 1 0 1 1 0 0 1 1 1 1 1
C 1 1 0 0 1 0 0 1 1 1 0
D 1 1 0 1 0 1 1 1 1 0 1
E 1 1 1 0 1 0 0 1 1 1 1
F 1 1 1 1 1 0 0 0 1 1 1

Table 1. Truth table for..

K-Map Simplification for Each Segment

Segment a
The minterms for segment a (when it should be ON) are:
m(0,2,3,5,6,7,8,9,10,12,14,15)

K-Map for Segment a:

D1D0 00 01 11 10
00 1 0 1 1
01 1 1 1 1
11 1 0 1 1
10 1 1 1 0

Simplified Equation:
a=D1′D0+D2′D0′+D2D0a=D1′D0+D2′D0′+D2D0

Segment b
The minterms for segment b are:
m(0, 1, 2, 3, 7, 8, 9, 10, 13).

m(0,1,2,3,4,7,8,9,10,13)
m(0,1,3,4,5,6,7,8,9,10,11,13)
m(0,2,3,5,6,8,9,11,12,13,14)
m(0,2,4,5,6,8,9,10,11,12,14,15)
m(0,4,5,6,8,9,10,11,12,14,15)
m(2,3,4,5,6,8,9,10,11,12,13,14,15)

K-Map for Segment b:

D1D0 00 01 11 10
00 1 1 1 1
01 1 1 1 0
11 0 1 1 0
10 1 0 1 0

Simplified Equation:
b=D3D0′+D1′D0+D3D1b=D3D0′+D1′D0+D3D1

Segment c
The minterms for segment c (i.e., when it should be ON) are:
m(0, 1, 3, 4, 5, 6, 7, 8, 9, 11, 13)

K-Map for Segment c:

D1D0 00 01 11 10
00 1 1 0 1
01 1 1 0 0
 11 1 1 1 0
10 0 1 0 1
Simplified Equation:
c=D3+D1′D0′+D1D0c=D3+D1′D0′+D1D0

Segment d
The minterms for segment d are:
m(0, 2, 3, 5, 6, 8, 9, 10, 11, 12, 14)

K-Map for Segment d:

D1D0 00 01 11 10
00 1 0 1 0
01 1 1 1 1
11 1 0 1 1
10 1 0 1 1

Simplified Equation:
d=D2′D1D0+D2D1′+D0D1′+D2′D0′d=D2′D1D0+D2D1′+D0D1′+D2′D0′

Segment e
The minterms for segment e are:
m(0, 2, 6, 8, 10, 11, 12, 14, 15)

K-Map for Segment e:

D1D0 00 01 11 10
00 1 0 0 1
01 1 0 0 0
11 1 1 0 1
10 1 0 1 1

Simplified Equation:
e=D2′D0+D3D1D0+D1′D0e=D2′D0+D3D1D0+D1′D0

Segment f
The minterms for segment f are:
m(0, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15)

K-Map for Segment f:

D1D0 00 01 11 10
00 1 1 1 1
01 1 1 0 1
11 1 1 0 1
10 1 0 1 1

Simplified Equation:
f=D3D0+D2D1′D0+D3D1′f=D3D0+D2D1′D0+D3D1′

Segment g
The minterms for segment g are:
m(2, 3, 4, 5, 6, 8, 9, 10, 11, 13, 14)

K-Map for Segment g:

D1D0 00 01 11 10
00 1 0 1 1
01 1 1 0 1
11 1 1 1 1
 10 1 0 1 1
Simplified Equation:
g=D1D0+D2′D0′+D3D1′g=D1D0+D2′D0′+D3D1′

Circuit Diagram

NOR 1
NOR 4

NOR 5
NOR 2

NOR 3

Figure 1. Half Adder using Minimum NOR Gates.

Figure 2. Pin Configuration for 7402 (Quad 2-Input NOR Gates).

Figure 3. Schematic Diagram of Half Adder using NOR Gate.

Procedure for Implementing the Half-Adder

1. Set Up the DIP Switch (4-bit Input)

 o Place the 4-bit DIP switch on the breadboard to allow binary input selection.
o Connect one terminal of each switch to the power rail (Vcc) or ground, depending
on the DIP switch configuration.
o Link the other terminal of each switch to the input pins of the logic gates.

2. Add Pull-Down Resistors

o Attach a 10kΩ pull-down resistor to each DIP switch input pin to prevent floating
inputs and ensure stable operation.
o Connect the other end of each pull-down resistor to the ground rail.

3. Prepare the 7-Segment Display

o Connect the common cathode (CC) pin of the 7-segment display to the ground rail.
o Prepare the anode terminals (a, b, c, d, e, f, g) for wiring to the logic gate outputs.

4. Wire the Logic Gates (7404, 7408, 7432 ICs)

o Use the 7404 IC for implementing the NOT gates, wiring two of them for the
necessary logic operations.
o Wire the inputs of the NOT gates to the DIP switch output and connect their
outputs to the corresponding 7-segment display segments via resistors.
o Implement the 7408 ICs for the AND gates and wire them according to the Boolean
logic for the circuit.
o Connect the inputs of the AND gates to combinations of DIP switch outputs and
NOT gate outputs, and link the outputs to the 7-segment display segments.
o Wire the 7432 ICs for OR gates and combine signals from DIP switches or other
gates, controlling the display segments.

5. Link Logic Gate Outputs to 7-Segment Display

o Route each output of the logic gates to the appropriate segment (a-g) of the 7-
segment display.
o Connect each segment’s anode to the output of the corresponding logic gate.

6. Add Current-Limiting Resistors

o Place 330Ω resistors in series with each 7-segment display segment to limit current
and protect the LEDs.
o Wire the resistors between the logic gate outputs and the 7-segment display.

7. Make Power and Ground Connections

o Attach the positive rail of the breadboard to a 5V DC power supply and the
negative rail to the ground.
o Connect the Vcc pin of each logic gate IC to the power rail and the GND pin to the
ground rail.

8. Test the Circuit

o Power on the circuit by connecting the 5V power supply.

o Toggle the DIP switches to apply different binary inputs (0000 to 1111) and
observe the display for the corresponding hexadecimal output.
o Verify the displayed output and ensure it matches the expected result according to
the truth table.
9. Troubleshoot if Necessary

o Check all connections to ensure they are correct, focusing on power and ground.
o Test the logic gate inputs and outputs using a multimeter or logic probe to confirm
functionality.
o Ensure all resistors are of the correct values (10kΩ for pull-down resistors and
330Ω for current-limiting resistors).
o Revisit the Boolean equations and K-map implementation to verify the logic
design.

Results and Discussion

Output:

Figure 4. Breadboard Setup of Half Adder using NOR Gate.

The circuit worked as expected with all input combinations providing the correct Sum
and Carry outputs. When both input switches (A and B) were in the OFF position (A = 0, B
= 0), both the Sum and Carry LEDs remained off, indicating a Sum of 0 and Carry of 0, as
expected. Upon pressing one of the switches, either for A or B, the Sum LED lit up while
the Carry LED remained off, demonstrating the correct behavior for A = 0, B = 1 or A = 1,
B = 0. These results match the expected output for a half-adder, where the Sum is 1 and the
Carry is 0 for these inputs.

When both input switches were pressed (A = 1, B = 1), the Carry LED lit up, while the
Sum LED turned off. This confirmed the correct operation for the Sum and Carry outputs
when both inputs are set to 1. In this case, the Sum is 0, and the Carry is 1, which aligns
with the truth table of a half-adder. This outcome further demonstrates the ability of NOR
gates to perform the logical operations needed to add binary numbers and handle the Carry
operation.

The use of NOR gates in this implementation showed that a simple set of logic gates
can perform complex arithmetic operations when connected properly. The consistent
results across all test cases demonstrate the accuracy and reliability of the circuit in
mimicking the behavior of a half-adder.

Conclusion
In conclusion, the physical implementation of the half-adder circuit using a 7402 NOR
gate IC successfully produced the expected outputs for all input combinations. The Sum
and Carry outputs were correctly displayed through the LEDs, confirming the functionality
of the circuit. This experiment illustrates the practicality of NOR gates in digital logic
design, specifically in constructing basic arithmetic circuits like the half-adder. Through
this hands-on implementation, we gained a deeper understanding of how logic gates can be
used to build complex circuits from fundamental components.