SEMBODAI RUKMANI VARATHARAJAN ENGINEERING

COLLEGE
SEMBODAI, VEDARANIAM [T.K],
NAGAPATTINAM [Dist] -614809.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

University Register No:

CERTIFICATE

Certified that this is the Bonafide Record of the work done by

Selvan / Selvi ………………………………………………semester of
…………………….year M.E.,(VLSI DEGIGN) in………………….
……………………….during the academic year ………….to ………

Signature of the Signature of the

Staff- In charge Head of the Department

Submitted for university practical examination held on ……………. at

Sembodai Rukmani Varatharajan Engineering College, Sembodai.

Internal Examiner External Examiner

 CONTENTS

EX. PAGE
NO: DATE NAME OF THE EXPERIMENT MARK SIGN
NO.
EXTRACTION OF PROCESS PARAMETERS OF
1
CMOS PROCESS TRANSISTORS
CMOS INVERTER DESIGN AND PERFORMANCE
2
ANALYSIS
USE SPICE TO BUILD A THREE STAGE AND FIVE
STAGE RING OSCILLATOR CIRCUIT AND
3 COMPARE ITS FREQUENCIES. USE FFT AND
VERIFY THE AMPLITUDE AND FREQUENCY
COMPONENTS IN THE SPECTRUM.

SINGLE STAGE AMPLIFIER DESIGN AND

4 PERFORMANCE ANALYSIS OF TRANS
CONDUCTANCE AMPLIFIER

5 OPERATIONAL AMPLIFIER

6 LAYOUT OF CMOS INVERTER

SCHEMATIC ENTRY AND SPICE SIMULATION FOR

7
DIFFERENTIAL AMPLIFIER
Expt. No :1 EXTRACTION OF PROCESS PARAMETERS OF CMOS PROCESS
Date : TRANSISTORS

AIM:
To Extract the process parameters of CMOS process transistors and to
observe the below characteristics,
a. Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
b. Plot ID vs. VGS at particular drain voltage for NMOS, PMOS and determine
Vt.
c. Plot log ID vs. VGS at particular gate voltage for NMOS, PMOS and
determine IOFF and subthreshold slope.
d. Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine
Channel length modulation factor.
e. Extract Vth of NMOS/PMOS transistors (short channel and long channe
l). Use VDS of appropriate voltage To extract Vth use the following procedure.
i. Plot gm vs VGS using SPICE and obtain peak gm point.
ii. Plot y=ID/(gm) as a function of VGS using SPICE.
iii. Use SPICE to plot tangent line passing through peak gm point in y (VGS)
plane and determine Vth.
f. Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load
line and calculate gm, gds, gm/gds, and unity gain frequency. Tabulate result
according to technologies and comment on it.

Software Required:

Theory:

Metal-Oxide-Semiconductor device theory covers a wide range of

complexity, from simple first order effects up through extremely detailed
descriptions. To avoid some of this complexity, most texts on MOS VLSI
design techniques use the simplified MOS device equations. A basic
understanding of MOS device operation will be assumed, although a brief
review follows. What is important to understand when extracting model
parameters is how the particular parameters relate to not only the model, but
also how they relate to the physical device itself. Circuit designers may be
content with using a model, without knowledge ofthe physical aspects of the
device, or with using models which are not directly related to any physical part
of the device.
Figure 1.1 shows the basic structure of an n-channel MOS transistor. The
transistor is made up of a P-type substrate, two N+ doped regions, called the
drain and the source, and a gate region between the drain and source regions,
which is insulated from the substrate by a thin layer of oxide. There are three
very important physical dimensions of the transistor, the gate oxide thickness,
TOX, the length of the space between the drain and the source, L, and the width
of the transistor, W.

The threshold voltage can also be calculated from knowledge of the

process parameters. An equation for VT is given in (1.1) below:

Vto is the extrapolated threshold voltage when the source and substrate
are at the same potential, and VT is the threshold voltage due to body effect,
which is a potential difference between the source and the substrate, VSB. The
terms which are related to the structure ofthe device are the remaining terms,
φB, y, and VFB.

NMOS: N type MOSFET is form by taking p substrate and two high doped n is
diffused in this p substrate. These two are taking as drain and source. Between
drain and source channel is formed. NMOS is in the cut off region when gate to
source voltage (Vgs) is negative. So for enhancement mode Vgs is greater than
threshold voltage. Doing in cadence we give positive supply to gate and drain.
Value of this positive supply is 1.2V (Because we are working in 65nm process
technology so that the maximum supply voltage is 1.2V). we do the analysis in
the range of 0 to 1.2V

Schematic diagram of NMOS in Cadence:

Two different types of analysis:

1) Curve B/W Id and Vds Taking Vgs constant (1.2V). (Output characteristics).
It comes in 1st quadrant.

2). Curve B/W Id and Vgs Taking Vds constant(1.2V) (Input characteristics).
This comes in 1st quadrant.

PMOS: PMOS is behaving just opposite to NMOS. PMOS is made by taking N

type substrate and doped TWO high doped P in N type substrate. PMOS is
working when gate to source voltage is negative. So in this analysis we apply
negative voltage to gate and drain. Also do it analysis to -1.2 to 0.
We do analysis of two types:

1). Curve B/W Id and Vds Taking Vgs constant. (Output characteristics) This
curve is B/W Id and Vds for different values of Vgs (-1.2 to 0 linear steps 4).
Values of Vgs is varies by taking a variable and do it simulation. Characteristic
is come 3rd quadrant.

2). Curve B/W Id and Vgs Taking Vds constant.( input characteristics) This
curve is B/W Id and Vgs for different values of Vds (-1.2 to 0 linear steps 4).
The characteristic is come 3rd quadrant.
RESULT

Thus the Extraction of the process parameters of CMOS process

transistors is observed for the various characteristics.
Expt. No : 2 CMOS INVERTER DESIGN AND PERFORMANCE
Date : ANALYSIS

AIM:
To design CMOS inverter and verify to performance characteristics.

APPARATUS REQUIRED:

 Tanner EDA Tool

 Personal computer

THEORY:

CMOS Inverter consists of nMOS and pMOS transistor in series

connected between VDD and GND. The gate of the two transistors are shorted
and connected to the input. When the input to the inverter A = 0, nMOS
transistor is OFF and pMOS transistor is ON. The output is pulled-up to VDD.
When the input A = 1, nMOS transistor is ON and pMOS transistor is OFF. The
Output is Pulled-down to GND.

PROCEDURE

• Draw the schematic of CMOS Inverter using S-Edit.

• Perform Transient Analysis of the CMOS Inverter.

• Go to ‘setup’, in that select ‘spice simulation’. Choose Transient

Analysis and set the parameters as explained in the instructions above.

• Obtain the output waveform from W-Edit.

• Obtain the spice code using T-Edit.

SCHEMATIC DIAGRAM:

SIMULATED WAVEFORM:
RESULT

Thus the CMOS Inverter was constructed and its functionality was
verified using transient analysis.
Exp. No :3 USE SPICE TO BUILD A THREE STAGE AND FIVE STAGE RING
Date : OSCILLATOR CIRCUIT AND COMPARE ITS FREQUENCIES. USE FFT
AND VERIFY THE AMPLITUDE AND FREQUENCY COMPONENTS IN
THE SPECTRUM.

AIM:

To build a three stage and five stage ring oscillator circuit and
compare its frequencies. Use FFT and verify the amplitude and
frequency components in the spectrum.
APPARATUS REQUIRED:

 PC with Windows XP.

 Microwind 3.1,DSCH 03.

THEORY:

RING OSCILLATOR:

A ring oscillator is comprised of a number of delay stages, with the output

of the last stage fed back to the input of the first. To achieve oscillation, the ring
must provide a phase shift of 2π and have unity voltage gain at the oscillation
frequency. Each delay stage must provide a phase shift of π /N, where N is the
number of delay stages.

The most basic ring oscillator is simply a chain of single ended digital
inverters, with the output of the last stage fed back to the input of the first stage.
Note that to provide the DC inversion, an odd number of stages must be used.
To see why this circuit will oscillate, assume that the output of the first inverter
is a ‘0’. Therefore, the output of the Nth inverter, where N is odd, must also be
‘0’. However, this output is also the input to the first inverter, so the first
inverter’s output must switch to a ‘1’. By the same logic, the output of the last
inverter will eventually switch to a ‘1’, switching the output of the first inverter
back to ‘0’. This process will repeat indefinitely, resulting in the voltage at each
node oscillating.

.
Fig 4.1, Ring Oscillator Using Single Ended in CMOS Inverter

To determine the frequency at which this circuit will oscillate, assume that the
delay through each inverter is td. The signal must go through N inverters, each
with delay td, for a total time of N•td, to obtain the first p phase shift. Then, the
signal must go through each stage a second time to obtain the remaining p phase
shift, resulting in a total period of 2N•td. The frequency is the reciprocal of the
period, resulting in the frequency.

(8)

To make this circuit useful, the oscillation frequency must be controllable.

The only parameters that affect the frequency are the number of stages, N, and
the delay per stage, td. It is difficult to implement a circuit that can vary the
number of stages in the ring. Therefore, to make this oscillator voltage-
controlled, td must be variable. One way to control the delay is to control the
amount of current available to charge or discharge the capacitive load of each
stage.
RING OSCILLATOR TYPE:
1. Single-ended ring oscillator
2. Differential ring oscillator

Fig 4.2, Types ring oscillator

Fig 4.3, Layout of three stage ring oscillator

PROPERTIES OF RING OSCILLATOR:

1. Oscillation may occur if the circuit multiple stages and hence multiple
poles.
2. The total number of inversion in the loop must be odd, so that the circuit
does not latch up.
3. The number of stages in ring oscillators is determined by various
requirements, including speed, power dissipation, noise immunity etc.
 4. Three to five stages provide optimum performance.
5. The ring oscillator is a member of the class of time delay oscillator.
6. Changing the supply voltage changes the delay through each inverter,
with higher voltages typically decreasing the delay and increasing the
oscillator frequency.
SIMULATION RESULT:
THREE STAGE RING OSCILLATOR:

THREE STAGE RING OSCILLATOR TIMING DIAGRAM:

LAYOUT DIAGRAM:
VOLTAGE Vs TIME OUTPUT:

VOLTAGE AND CURRENT OUTPUT:

VOLTAGE Vs VOLTAGE OUTPUT:

FREQUENCY Vs TIME OUTPUT:

EYE DIAGRAM :

RESULT:

Thus build a three stage and five stage ring oscillator circuit and
compare its frequencies. Use FFT and verify the amplitude and
frequency component in the spectrum was verified.
Expt. No : 4 SINGLE STAGE AMPLIFIER DESIGN AND
Date : PERFORMANCE ANALYSIS OF TRANS CONDUCTANCE
AMPLIFIER

AIM:

a) To construct the Trans Conductance Amplifier in Tanner EDA v13.1 and to

do the DC analysis.

b) To analyze the response with appropriate wave forms. And to verify

the Spice.

APPARATUS REQUIRED:

 Tanner Tools v13.1

 Schematic-Edit

 Layout -Edit

 Wave- Edit

 Tanner Spice.

PROCEDURE:

1. Open S-Edit window.

2. Go to File ,New , New design

3. Go to Cell, New View

4. Add libraries file to the New Cell.

5. Instance the devices by using appropriate library files.

6. Save the design and setup the simulation.

7. Run design and observe waveforms.

8. Observe DC inputs and outputs by giving appropriate inputs.

SCHEMATIC DIAGRAM:

Trans Conductance Amplifier Schematic

TANNER SPICE CODE:

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 N_1 N_2 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MNMOS_2 Out N_4 N_3 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MNMOS_3 N_3 N_5 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MPMOS_1 N_1 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MPMOS_2 Out N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 N_2 Gnd DC 2

VVoltageSource_3 N_5 Gnd DC 700m

VVoltageSource_4 Out Gnd DC 2.5

VVoltageSource_5 N_4 N_2 DC 0

********* Simulation Settings - Analysis section *********

.dc lin source VVOLTAGESOURCE_5 -1 1 0.01

.print dc id(MNMOS_1) id(MNMOS_2)

.print dc i(vvoltagesource_4,out)

*.tran 350ns 500ns

********* Simulation Settings - Additional SPICE commands *********

.end
OUTPUT RESPONSES:

i(VPMOS_1)

i1(VNMOS_3)

i1(VNMOS_2)

Trans Conductance Amplifier Waveforms

RESULT:

Thus The Trans Conductance Amplifier is constructed in Tanner

EDA v13.1, the spice code is generated and wave forms are verified.
Ex. No :5
OPERATIONAL AMPLIFIER
Date :

AIM:

a) To construct the Operational Amplifier in Tanner EDA v13.1 and to

do the

AC analysis.

b) To analyze the response with appropriate wave forms. And to verify

the Spice.

APPARATUS REQUIRED:
1. Tanner Tools v13.1
2. Schematic-Edit
3. Layout -Edit
4. Wave- Edit
5. Tanner Spice
Procedure:

1. Open S-Edit window.

2. Go to File  New  New design
3. Go to Cell New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe DC inputs and outputs by giving appropriate inputs.
Schematic Diagram:

Tanner Spice Code:

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\user11\My Documents\Tanner EDA\Tanner

Tools v13.0\Libraries\Models\Generic_025.lib " TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

CCapacitor_1 N_3 Out 1p

CCapacitor_2 Out Gnd 1p

MNMOS_1 N_2 N_6 N_11 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MNMOS_2 N_3 N_5 N_11 N_4 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MNMOS_3 N_11 N_10 Gnd N_7 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MNMOS_4 N_9 N_10 Gnd N_8 NMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MPMOS_1 N_3 N_2 Vdd N_12 PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MPMOS_2 N_2 N_2 Vdd N_13 PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

MPMOS_3 N_9 N_3 Vdd N_14 PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u

VVoltageSource_2 N_6 Gnd DC 5

VVoltageSource_3 N_10 Gnd DC 5

VVoltageSource_4 N_5 N_6 DC 0 AC 1 0

********* Simulation Settings - Analysis section *********

*.tran 5ns 500ns

.ac lin 10 0 10

.print ac vm(out,gnd) vp(out,gnd)

********* Simulation Settings - Additional SPICE commands *********

.end
Output responses:

VP(OUT)

Vdb(OUT)

V(OUT)

Operational Amplifier Waveforms

RESULT:

The Operational Amplifier is constructed in Tanner EDA v13.1, the

spice code is generated and wave forms are verified.
Expt. No : 6
LAYOUT OF CMOS INVERTER
Date :

AIM
To draw the layout of CMOS Inverter using L-Edit and extract the SPICE
code.

APPARATUS REQUIRED:

 L-Edit & T-SPICE - Tanner Tool.

PROCEDURE:

 Draw the CMOS Inverter layout by obeying the Lamda

Rules using L edit.
o Poly - 2λ
o Active contact - 2 λ
o Active Contact – Metal - 1 λ
o Active Contact – Active region - 2 λ
o Active Region – Pselect - 3 λ
o Pselect – nWell - 3λ
 Check DRC to verify whether any region violate the lamda
rule.
 Setup the extraction and extract the spice code using T-spice.
CMOS INVERTER:
LAYOUT DIAGRAM:

SIMULATED WAVEFORM:
RESULT

Thus draw the layout of CMOS Inverter using L-Edit and extract the
SPICE code and the output also verified successfully.
Expt. No : 7 SCHEMATIC ENTRY AND SPICE SIMULATION FOR DIFFERENTIAL
Date : AMPLIFIER

AIM
To calculate the gain, bandwidth and CMRR of a differential amplifier
through schematic entry

APPARATUS REQUIRED:

 S-Edit using Tanner Tool.

THEORY:
A differential amplifier is a type of electronic amplifier that multiplies
the difference between two inputs by some constant factor (the differential
gain). Many electronic devices use differential amplifiers internally. The output
of an ideal differential amplifier is given by:

Where Vin+ and Vin- are the input voltages and Ac is the differential gain.In
practice, however, the gain is not quite equal for the two inputs. This means that
if Vin+ and Vin- are equal, the output will not be zero, as it would be in the
ideal case. A more realistic expression for the output of a differential amplifier
thus includes a second term.

Ac is called the common-mode gain of the amplifier. As differential amplifiers

are often used when it is desired to null out noise or bias-voltages that appear at
both inputs, a low common-mode gain is usually considered good. The
common-mode rejection ratio, usually defined as the ratio between differential-
mode gain and common-mode gain, indicates the of the amplifier to accurately
cancel voltages that are common to both inputs.
Common-mode rejection ratio (CMRR):
PROCEDURE:

 Draw the schematic of differential amplifier using S-edit and generate the
symbol.
 Draw the schematic of differential amplifier circuit using the generated
symbol.
 Perform AC Analysis of the differential amplifier.
 Obtain the frequency response from W-edit.
 Obtain the spice code using T-edit.

SCHEMATIC DIAGRAM:
SIMULATED WAVEFORM:

RESULT:

Thus the calculation of the gain, bandwidth and CMRR of a differential

amplifier through schematic entry verified successfully.